diff options
| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2015-12-10 12:00:23 +0000 |
|---|---|---|
| committer | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2015-12-10 12:00:23 +0000 |
| commit | 486aa5752f5cc293a4195402b679444546c22921 (patch) | |
| tree | 576c0f3ef17cd44fff796ac1499d9686e2dc49ba | |
| parent | 7d295707ccc9c273e4764a588723d39e1693d057 (diff) | |
arm: dts: apq8064: fix clock names according to new rpmccqcomlt-v4.3-20151211
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064-coresight.dtsi | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064-coresight.dtsi b/arch/arm/boot/dts/qcom-apq8064-coresight.dtsi index d69ec6675a49..6a8c4f2222f5 100644 --- a/arch/arm/boot/dts/qcom-apq8064-coresight.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-coresight.dtsi @@ -11,13 +11,14 @@ * GNU General Public License for more details. */ +#include <dt-bindings/clock/qcom,rpmcc.h> &soc { etb@1a01000 { compatible = "coresight-etb10", "arm,primecell"; reg = <0x1a01000 0x1000>; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; port { @@ -32,7 +33,7 @@ compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0x1a03000 0x1000>; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; port { @@ -46,7 +47,7 @@ replicator { compatible = "arm,coresight-replicator"; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; ports { @@ -79,7 +80,7 @@ compatible = "arm,coresight-funnel", "arm,primecell"; reg = <0x1a04000 0x1000>; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; ports { @@ -134,7 +135,7 @@ compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x1a1c000 0x1000>; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU0>; @@ -150,7 +151,7 @@ compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x1a1d000 0x1000>; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU1>; @@ -166,7 +167,7 @@ compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x1a1e000 0x1000>; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU2>; @@ -182,7 +183,7 @@ compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x1a1f000 0x1000>; - clocks = <&rpmcc QCOM_RPM_QDSS_CLK>; + clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU3>; |