diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2012-02-14 12:09:08 +0000 |
|---|---|---|
| committer | Jon Medhurst <tixy@linaro.org> | 2012-04-17 19:48:03 +0100 |
| commit | f121fe07ef478d6e141a2c266f39a3d26e28763c (patch) | |
| tree | 8d2eccdd4fb39e237786c25c453fd33c63aa2158 | |
| parent | 56da8738f1e758a4f00163fed8298b409c6b8011 (diff) | |
ARM: Set bit 22 in the PL310 (cache controller) AuxCtlr registertracking-armlt-arm-arch-fixes-3.4-rc3-2012.04-0
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
This patch ensures that bit 22 is set in the l2x0_init() function if
PL310 and not rely on the platform code to specify it. It also modifies
the 'aux' variable only if the actual register is written so that the
final printk displays the real hardware value.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Kyungmin Park <kyungmin.park@samsung.com>
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index a53fd2aaa2f4..361a6286ad29 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -320,9 +320,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); - aux &= aux_mask; - aux |= aux_val; - /* Determine the number of ways */ switch (cache_id & L2X0_CACHE_ID_PART_MASK) { case L2X0_CACHE_ID_PART_L310: @@ -331,6 +328,13 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) else ways = 8; type = "L310"; + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + aux_val |= 1 << 22; break; case L2X0_CACHE_ID_PART_L210: ways = (aux >> 13) & 0xf; @@ -361,6 +365,9 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) /* Make sure that I&D is not locked down when starting */ l2x0_unlock(cache_id); + aux &= aux_mask; + aux |= aux_val; + /* l2x0 controller is disabled */ writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); |