diff options
Diffstat (limited to 'HisiPkg/Include/Library')
| -rw-r--r-- | HisiPkg/Include/Library/BrdCommon.h | 358 | ||||
| -rw-r--r-- | HisiPkg/Include/Library/BspUartLib.h | 95 | ||||
| -rw-r--r-- | HisiPkg/Include/Library/EblProvisionLib.h | 59 | ||||
| -rw-r--r-- | HisiPkg/Include/Library/PinIo_Api.h | 60 | ||||
| -rw-r--r-- | HisiPkg/Include/Library/ResetWdtLib.h | 34 | ||||
| -rw-r--r-- | HisiPkg/Include/Library/Std.h | 147 | ||||
| -rw-r--r-- | HisiPkg/Include/Library/SysUtilLib.h | 41 | ||||
| -rw-r--r-- | HisiPkg/Include/Library/config.h | 436 |
8 files changed, 0 insertions, 1230 deletions
diff --git a/HisiPkg/Include/Library/BrdCommon.h b/HisiPkg/Include/Library/BrdCommon.h deleted file mode 100644 index 87973a455..000000000 --- a/HisiPkg/Include/Library/BrdCommon.h +++ /dev/null @@ -1,358 +0,0 @@ -/*******************************************************************
-#
-#
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-
-#ifndef __BRDCOMMON_H
-#define __BRDCOMMON_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-#define HDF_FIRST_BOOTROM_FLAG 0x0
-#define HDF_SECOND_BOOTROM_FLAG 0x1
-
-#define DEFAULT_FIRST_BOOTROM_SPACE_SIZE (0x200000)
-#define DEFAULT_SECOND_BOOTROM_SPACE_SIZE (0x700000)
-#define DEFAULT_BSP_PARA_SPACE_SIZE (0x300000)
-
-
-#define DEFAULT_FIRST_BOOTROM_BINDFILE_SIZE (0x200000)
-#define DEFAULT_SECOND_BOOTROM_BINDFILE_SIZE (0x200000)
-
-#define DEFAULT_BOOTLINE_OFFSET_IN_PARA (0x20000+0x2000)
-
-#define FLASH_BASE_ADDR 0xf0000000
-
-#define FLASH_FIRST_HDF_ADDR (0)
-#define FLASH_FIRST_HDF_SIZE (0x20000)
-#define FLASH_FIRST_HDF_RSV_SIZE (0x60000)
-
-#define FLASH_SECOND_HDF_ADDR (FLASH_FIRST_HDF_ADDR + FLASH_FIRST_HDF_SIZE + FLASH_FIRST_HDF_RSV_SIZE)
-#define FLASH_SECOND_HDF_SIZE (FLASH_FIRST_HDF_SIZE)
-#define FLASH_SECOND_HDF_RSV_SIZE (FLASH_FIRST_HDF_RSV_SIZE)
-
-#define FIRST_BOOTROM_ADRS (0x100000)//(FLASH_SECOND_HDF_ADDR + FLASH_SECOND_HDF_SIZE + FLASH_SECOND_HDF_RSV_SIZE)
-
-#define FIRST_BOOTROM_SIZE 0x200000
-
-#define FLASH_PROTECT_BLOCK0 (0x0)
-#define FLASH_PROTECT_BLOCK8 (0x8)
-#define FLASH_PROTECT_BLOCK9 (0x9)
-#define FLASH_PROTECT_BLOCK10 (0xa)
-#define FLASH_PROTECT_BLOCK11 (0xb)
-
-#define RESERVE_AFTER_FIRST_BOOTROM_SIZE (0x200000)
-#define DDR_DIAGNOSE_START_ADRS ((FIRST_BOOTROM_ADRS) + (FIRST_BOOTROM_SIZE) + RESERVE_AFTER_FIRST_BOOTROM_SIZE)
-#define DDR_DIAGNOSE_LENGTH_ADRS (DDR_DIAGNOSE_START_ADRS + (0x4))
-
-#define SECOND_BOOTROM_ADRS ((FIRST_BOOTROM_ADRS) + (FIRST_BOOTROM_SIZE))
-#define SECOND_BOOTROM_SIZE 0x700000 //size of L2 BIOS
-#define BOARD_WORK_INFO_ADRS ((SECOND_BOOTROM_ADRS) + (SECOND_BOOTROM_SIZE))
-#define BOARD_WORK_INFO_SIZE (0x20000) /* 128K byte*/
-
-#define BOARD_HARD_INFO_ADRS ((BOARD_WORK_INFO_ADRS)+(BOARD_WORK_INFO_SIZE))
-#define BOARD_HARD_INFO_SIZE (0x20000) /* 128K byte*/
-
-#define BOARD_AGING_INFO_ADRS ((BOARD_HARD_INFO_ADRS)+(BOARD_HARD_INFO_SIZE))
-#define BOARD_AGING_INFO_SIZE (0x18000) /* 96K byte */
-
-#define BOARD_AGING_LOG_ADRS ((BOARD_AGING_INFO_ADRS)+(BOARD_AGING_INFO_SIZE))
-#define BOARD_AGING_LOG_SIZE (0x8000) /* 32K byte */
-#define BOARD_AGING_CHIP_LOG_SIZE (0x800)
-
-#define APPLICATION_INFO_ADRS ((BOARD_AGING_LOG_ADRS)+(BOARD_AGING_LOG_SIZE))
-#define APPLICATION_INFO_SIZE (0x60000) /* 128*3K byte */
-
-#define FLASH_BLOCK_RSV_ADDRS (APPLICATION_INFO_ADRS + APPLICATION_INFO_SIZE)
-#define FLASH_BLOCK_RSV_SIZE (0xc0000) /*128*6K byte*/
-
-#define BOARD_DRV_MEND_INFO_ADDRS (FLASH_BLOCK_RSV_ADDRS + FLASH_BLOCK_RSV_SIZE)
-#define BOARD_DRV_MEND_INFO_SIZE (0x80000) /*128*4K byte*/
-
-#define SECOND_BOOTROM_VALID_FLAG_ADDR (BOARD_WORK_INFO_ADRS + 0)
-#define SECOND_BOOTROM_VALID_FLAG_SIZE (0x04)
-#define SECOND_BOOTROM_VALID_FLAG_VALUE (0x5A5A5A5A)
-
-#define FLASH_BSP_PARA_START ((BOARD_WORK_INFO_ADRS) + 0x2000) //a00000+0xe0000
-#define FLASH_BSP_PARA_SIZE (0x2000)
-
-#define FAST_STARTUP_VALID_FLAG_ADDR (FLASH_BSP_PARA_START + FLASH_BSP_PARA_SIZE)
-#define FAST_STARTUP_VALID_FLAG_SIZE (0x04)
-#define FAST_STARTUP_VALID_FLAG_VALUE (0x5A5A5A5A)
-#define FAST_STARTUP_FILE_START_BLOCK_ADDR (FAST_STARTUP_VALID_FLAG_ADDR + FAST_STARTUP_VALID_FLAG_SIZE)
-#define FAST_STARTUP_FILE_START_BLOCK_SIZE (0x04)
-#define FAST_STARTUP_FILE_LENGTH_ADDR (FAST_STARTUP_FILE_START_BLOCK_ADDR + FAST_STARTUP_FILE_START_BLOCK_SIZE)
-#define FAST_STARTUP_FILE_LENGTH_SIZE (0x04)
-
-#define FLASH_UET_PARA_START (BOARD_HARD_INFO_ADRS) /*BOARD_HARD_INFO_ADRS*/
-
-#define FLASH_UET_PARA_SIZE 0x2000
-
-#define SIZE_4KB 0x00001000
-#define SIZE_2KB 0x00000800
-#define FLASH_TELNET_USER (FLASH_UET_PARA_START + FLASH_UET_PARA_SIZE -SIZE_4KB)
-#define FLASH_TELNET_USER_SIZE SIZE_2KB
-#define FLASH_TELNET_USER_SET_FLAG (FLASH_TELNET_USER +FLASH_TELNET_USER_SIZE)
-#define FLASH_TELNET_USER_SIZE SIZE_2KB
-#define FLASH_TELNET_FLAG 0x5a5aa6a6
-
-#define FLASH_CLOCK_PARA_START (APPLICATION_INFO_ADRS + 0x0)
-#define FLASH_CLOCK_PARA_SIZE 0x1000
-
-#define FLASH_NET_PARA_START (APPLICATION_INFO_ADRS + 0x20000)
-#define FLASH_NET_PARA_SIZE 0x1000
-
-#define FLASH_BSPLOG_PARA_START (FLASH_NET_PARA_START + 0x20000)
-#define FLASH_BSPLOG_PARA_SIZE 0x1000
-
-#define FLASH_UPPER_PARA_START (BOARD_DRV_MEND_INFO_ADDRS + BOARD_DRV_MEND_INFO_SIZE)
-#define FLASH_UPPER_PARA_SIZE 0x200000
-
-#define SECOND_BTRM_TEXT_START (FIRST_BOOTROM_ADRS + FIRST_BOOTROM_SIZE)
-
-#define STA_SRAM_MEM_BASE 0xe0000000//HDFINF_CpuBaseAddrAutoMatch(4) /*4=SRAM*/ /* 0x2ff00000 */
-#define STA_SRAM_MEM_SIZE (0x40000) /* 256K */
-
-#define CPU_RAM_USED_TOTAL_SIZE (0x200)
-#define CPU_RAM_USED_START_ADRS (STA_SRAM_MEM_BASE)
-
-#define CPU_RAM_START_TYPE_ADRS (CPU_RAM_USED_START_ADRS) /*addr : 0x2ff00000*/
-#define CPU_RAM_START_TYPE_SIZE (0x04)
-#define BOOTROM_LEVEL1_START_VALUE (1)
-#define BOOTROM_LEVEL2_START_VALUE (2)
-#define SAFE_VERSION_START_VALUE (0)
-#define FAST_VERSION_START_VALUE (3)
-
-#define CPU_RAM_RESET_FLAG_ADRS (CPU_RAM_START_TYPE_ADRS + CPU_RAM_START_TYPE_SIZE)/*addr : 0x2ff00004*/
-#define CPU_RAM_RESET_FLAG_SIZE (0x04)
-#define CPU_RAM_RESET_FLAG_VALUE (0x5A5A5A5A)
-#define CPU_PWR_RESET_FLAG_VALUE (0x4B4B)
-
-#define CPU_RAM_LOAD_IMAGE_ADRS (CPU_RAM_RESET_FLAG_ADRS + CPU_RAM_RESET_FLAG_SIZE) /*addr : 0x2ff00008*/
-#define CPU_RAM_LOAD_IMAGE_SIZE (0x04)
-
-#define CPU_RAM_EXAM_RESULT_ADRS (CPU_RAM_LOAD_IMAGE_ADRS + CPU_RAM_LOAD_IMAGE_SIZE)/*addr : 0x2ff0000c*/
-#define CPU_RAM_EXAM_RESULT_SIZE (40)
-
-#define CPU_RAM_SEC_BTRM_FAIL_FLAG_ADRS (CPU_RAM_EXAM_RESULT_ADRS + CPU_RAM_EXAM_RESULT_SIZE)
-#define CPU_RAM_SEC_BTRM_FAIL_FLAG_SIZE (0x04)
-#define CPU_RAM_SEC_BTRM_FAIL_FLAG_VALUE (0x5A5A5A5A)
-#define CPU_RAM_SEC_BTRM_FIRST_RUN_VALUE (0xb0aec7e9)
-
-#define CPU_RAM_SEC_BTRM_FAIL_COUNTER_ADRS ((CPU_RAM_SEC_BTRM_FAIL_FLAG_ADRS)+(CPU_RAM_SEC_BTRM_FAIL_FLAG_SIZE))
-#define CPU_RAM_SEC_BTRM_FAIL_COUNTER_SIZE (0x04)
-
-#define CPU_RAM_AGING_INFO_ADRS ((CPU_RAM_SEC_BTRM_FAIL_COUNTER_ADRS)+(CPU_RAM_SEC_BTRM_FAIL_COUNTER_SIZE))
-#define CPU_RAM_AGING_INFO_SIZE (0x48)
-
-#define CPU_AGING_STAT_ADRS ((CPU_RAM_AGING_INFO_ADRS)+(CPU_RAM_AGING_INFO_SIZE))/*addr : 0x2ff00084*/
-#define CPU_AGING_STAT_SIZE (0x4)
-#define CPU_AGING_STAT_VAL (0x5a5a5a5a)
-#define CPU_AGING_STAT_NO_VAL (0x00000000)
-
-#define CPU_HDF_VER_SELECT_ADRS ((CPU_AGING_STAT_ADRS)+(CPU_AGING_STAT_SIZE))/*addr : 0x2ff00088*/
-#define CPU_HDF_VER_SELECT_SIZE (0x4)
-
-#define CPU_RAM_DEC_WDT_TIME_ADDR ((CPU_HDF_VER_SELECT_ADRS) + CPU_HDF_VER_SELECT_SIZE)/*addr : 0x2ff0008c*/
-#define CPU_RAM_DEC_WDT_TIME_SIZE (0x4)
-
-#define CPU_RAM_UART_ADDR (CPU_RAM_DEC_WDT_TIME_ADDR + CPU_RAM_DEC_WDT_TIME_SIZE)/*addr : 0x2ff00090*/
-#define CPU_RAM_UART_SIZE (0x4)
-
-#define CPU_MBIST_AGING_INFO_ADRS (CPU_RAM_UART_ADDR + CPU_RAM_UART_SIZE) /*addr : 0xaff00094*/
-#define CPU_MBIST_AGING_INFO_SIZE (64)
-#define MEM_MANAGE_ADDR (CPU_RAM_UART_ADDR + CPU_RAM_UART_SIZE)/*addr : 0xaff00094*/
-#define MEM_MANAGE_SIZE (4*8)
-
-#define CPU_RAM_TEST_FAIL_COUNT_ADDR (MEM_MANAGE_ADDR+MEM_MANAGE_SIZE)/*0x2ff000b4*/
-#define CPU_RAM_TEST_FAIL_COUNT_SIZE (4)
-
-#define FAST_STARTUP_PROCESS_FLAG_ADDR (CPU_RAM_TEST_FAIL_COUNT_ADDR + CPU_RAM_TEST_FAIL_COUNT_SIZE)/*0x2ff000b8*/
-#define FAST_STARTUP_PROCESS_FLAG_SIZE (0x4)
-#define FAST_STARTUP_SUCCESS_FLAG (0x5a5a5a5a)
-#define FAST_STARTUP_FAIL_FLAG (0x4b4b4b4b)
-
-#define CPU_RAM_HDF_CURRENT_VERSION_ADDR (FAST_STARTUP_PROCESS_FLAG_ADDR + FAST_STARTUP_PROCESS_FLAG_SIZE) /*0x2ff000bc*/
-#define CPU_RAM_HDF_CURRENT_VERSION_SIZE (4)
-#define CPU_RAM_HDF_BAK_VERSION_MAGIC_FLAG (0xb5a4b5a4)
-
-#define CPU_RAM_HDF_RESOLVE_FAIL_COUNT_ADDR (CPU_RAM_HDF_CURRENT_VERSION_ADDR + CPU_RAM_HDF_CURRENT_VERSION_SIZE) /*0x2ff000c0*/
-#define CPU_RAM_HDF_RESOLVE_FAIL_COUNT_SIZE (4)
-
-
-
-
-
-#define MCLOAD_INFO_ADDR 0xaff000c4 /*addr : 0xaff000c4*/
-#define MClOAD_INFO_SIZE (12*8)
-
-
-#define CONTROL_SLAVE_STATUS_INFO 0xaff00124 /*addr : 0xaff00124*/
-#define CONTROL_SLAVE_STATUS_INFO_SIZE (4*8)
-
-#define CPU_RAM_WFI_STATUS_ADDR (CONTROL_SLAVE_STATUS_INFO + CONTROL_SLAVE_STATUS_INFO_SIZE)/*addr : 0xaff00144*/
-#define CPU_RAM_WFI_STATUS_SIZE (4*8)
-
-#define CPU_RAM_CONTROL_SLAVE_HART_BEAT_ADDR (CPU_RAM_WFI_STATUS_ADDR + CPU_RAM_WFI_STATUS_SIZE) /*addr : 0xaff00164*/
-#define CPU_RAM_CONTROL_SLAVE_HART_BEAT_SIZE (4*8)
-
-#define CPU_RAM_SLAVE_CORE_TYPE_ADDR (CPU_RAM_CONTROL_SLAVE_HART_BEAT_ADDR + CPU_RAM_CONTROL_SLAVE_HART_BEAT_SIZE)/*addr : 0xaff00184*/
-#define CPU_RAM_SLAVE_CORE_TYPE_SIZE (4)
-
-#define CPU_RAM_CLUSTER0_SCU_EN_FLAG_ADDR (CPU_RAM_SLAVE_CORE_TYPE_ADDR + CPU_RAM_SLAVE_CORE_TYPE_SIZE)/*0xaff00188*/
-#define CPU_RAM_CLUSTER0_SCU_EN_FLAG_SIZE (4)
-#define CPU_RAM_CLUSTER1_SCU_EN_FLAG_ADDR (CPU_RAM_CLUSTER0_SCU_EN_FLAG_ADDR + CPU_RAM_CLUSTER0_SCU_EN_FLAG_SIZE)/*0xaff0018c*/
-#define CPU_RAM_CLUSTER1_SCU_EN_FLAG_SIZE (4)
-
-#define CPU_RAM_SCU_EN_FLAG (0xaaaaaaaa)
-#define CPU_RAM_SCU_UNEN_FLAG (0xbbbbbbbb)
-
-#define CPU_RAM_SLAVE_CORE_RUN_COUNT_ADDR (CPU_RAM_CLUSTER1_SCU_EN_FLAG_ADDR+CPU_RAM_CLUSTER1_SCU_EN_FLAG_SIZE)/*0xaff00190*/
-#define CPU_RAM_SLAVE_CORE_RUN_COUNT_SIZE (4)
-
-#define CPU_RAM_CPU1_RST_SRC_ADDR (CPU_RAM_SLAVE_CORE_RUN_COUNT_ADDR+CPU_RAM_SLAVE_CORE_RUN_COUNT_SIZE)/*0xaff00194*/
-#define CPU_RAM_CPU1_RST_SRC_SIZE (4)
-
-#define CPU_RAM_SAVE_HIMEM_FLAG ((CPU_RAM_CPU1_RST_SRC_ADDR)+(CPU_RAM_CPU1_RST_SRC_SIZE)) /*0xaff00198*/
-#define CPU_RAM_SAVE_HIMEM_FLAG_SIZE (4)
-
-#define CPU_RAM_DDR_WRITE_LEVELING_FLAG ((CPU_RAM_SAVE_HIMEM_FLAG) + (CPU_RAM_SAVE_HIMEM_FLAG_SIZE)) /*0xaff0019c*/
-#define CPU_RAM_DDR_WRITE_LEVELING_SIZE 4
-
-#define CPU_RAM_IPI_BASE_ADDR (CPU_RAM_DDR_WRITE_LEVELING_FLAG + CPU_RAM_DDR_WRITE_LEVELING_SIZE) /* 0xAFF001A0 */
-#define CPU_RAM_IPI_SIZE (4* 8 * 8)
-
-#define CPU_RAM_STACK_ADRS (STA_SRAM_MEM_BASE + STA_SRAM_MEM_SIZE-0x100)
-
-#define FLASH_CPU_CHIP_INDEX 0
-#define FLASH_MAX_CHIP_INDEX FLASH_CPU_CHIP_INDEX
-
-
-
-/******************************************************************************
-Memory configuration
-*******************************************************************************/
-#define HDF_COPY_TO_DRAM_ADRS (0x900000)
-
-/*** RAM Information ***/
-#define BSP_LOG_SIZE (0x00080000)
-
-#define BSP_REPORT_MAX_SIZE (0x00010000)
-
-#define BSP_REALTIME_REPORT_ADDR (0x00020000)
-#define BSP_LASTWORD_REPORT_ADDR (0x00040000)
-
-#define BSP_FILESYS_RESERVED_ADDR (0x00030000)
-
-#define TASK_SWITCH_TRACE_BASEADDR (0x00050000+0x10)/*Addr=0x50000*/
-
-
-#define BSP_WARM_RESET_TABLE_ADRS (IMAGE_LOW_ADRS - 0x200)
-#define BSP_WARM_RESET_TABLE_SIZE 0X04
-#define BSP_WARM_RESET_TABLE_VALUE 0x3C5AA5C3
-
-#define BSP_SOFT_RESET_TABLE_ADRS (BSP_WARM_RESET_TABLE_ADRS + BSP_WARM_RESET_TABLE_SIZE)
-#define BSP_SOFT_RESET_TABLE_SIZE 0x04
-#define BSP_SOFT_RESET_TABLE_VALUE0 0xa5a5a5a5
-#define BSP_SOFT_RESET_TABLE_VALUE1 0x4b4b4b4b
-#define BSP_SOFT_RESET_TABLE_VALUE2 0
-
-#define BSP_1588_RESERVED_BEGIN (0x5ff800)
-#define BSP_1588_RESERVED_SIZE (2048)
-#define BSP_1588_RESERVED_END (0x600000)
-
-#define BSP_VECTOR_SAVE_BASEADDR (0)
-#define BSP_VECTOR_SAVE_SIZE (0)
-#define BSP_MEM_RECORD_BASEADDR (0x600000)
-#define BSP_MEM_RECORD_MAX_LEN (0x300000)
-#define BSP_MEM_RECORD_BAK_BASEADDR (0)
-#define BSP_MEM_RECORD_BAK_MAX_LEN (0)
-#define DEDICATED_TASKTCB_INFO_BASEADDR (0)
-#define DEDICATED_TASKTCB_INFO_MAX_LEN (0)
-#define ISR_STACK_INFO_BASEADDR (0)
-#define ISR_STACK_INFO_MAX_LEN (0)
-#define BOARD_REALTIME_RECORD_BASEADDR (0)
-#define BOARD_REALTIME_RECORD_MAX_LEN (0)
-
-#define HDF_RAM_MAPAREA_ADDR (0x900000)
-#define HDF_RAM_MAPAREA_SIZE (0x20000) /* 128K */
-
-#define FIQ_TASK_INFO_ADDR (0x920000)
-#define FIQ_STACK_ADDR (FIQ_TASK_INFO_ADDR + 0x4000)
-#define BOARD_NAME "MPTXb"
-#define SYS_CLK_FREQ (13000000)
-
-#define PENDING (0x0)
-#define RST_HANDLE (0x1)
-#define SYS_INIT (0x2)
-#define USR_INIT (0x3)
-#define USR_ROOT (0x4)
-#define RUNNING (0x5)
-#define INIT_START (0x1)
-#define RUN_NORMAL (0x2)
-#define INIT_FAIL (0x3)
-#define RUN_ABNORMAL (0x4)
-#define RUN_LOOP (0x5)
-#define STATUS_NULL (0x0)
-
-#define FE_ELE_NET_ID 0
-#define FE_DDI_NET_ID 1
-#define CBUS_NET_ID 2
-#define BACK_NET_ID 3
-#define MAX_NET_ID 4
-
-#define GE_IPADDR_ID 0
-#define TARGET_IPADDR_ID 1
-#define HOST_IPADDR_ID 2
-
-#define PORT_TYPE_DEBUG 0
-#define PORT_TYPE_CAN 1
-#define PORT_TYPE_TRAFFIC 2
-#define PORT_TYPE_BACK 3
-#define PORT_TYPE_MAX_NUM 3
-
-#define PORT_DEBUG_ID 0
-#define PORT_CAN_ID 0
-#define PORT_TRAFFIC_ID_0 0
-#define PORT_TRAFFIC_ID_1 1
-#define PORT_CAN_DEBUG_ID 0
-
-#define SC_SYSSTAT15 (HDFINF_CpuBaseAddrAutoMatch(CPU_SYSCTRL) + 0x444)
-#define SC_MSCPU_BIT (20)
-#define SC_MSCPU_MASK (0x1)
-#define PORT_INTERLINK_ID 0
-#define BSP_SLAVE_CPU_START_FLAG_ADDR 0x91b00000
-#define BSP_SLAVE_CPU_START_FLAG 0x5A6A7A8A
-#define BSP_MS_CPU_SHARE_ADDR 0x91b00004
-#define BSP_CPU1_FILELOAD_MEM_ADDR (0x92A00000)
-#define BSP_CPU1_FILELOAD_MEM_LEN (0x2400000)
-#define BSP_MAX_FILE_LENS_FOR_ONE_FILE (BSP_CPU1_FILELOAD_MEM_ADDR - BSP_MS_CPU_SHARE_ADDR)
-
-#define BSP_CPU1_FILELOAD_OK_FLAG 0x5A576767
-#define HDF_DDR_Addr (0x900000)
-#define L1_CACHE_MBIST_End 0xA5A5A5A5
-#define L1_CACHE_MBIST_FLAG 0x12345678
-#define L1_CACHE_MBIST_FLAG_B 0x87654321
-#define MBIST_CTRL_ADDR 0x2FF3FCC0
-#define MBIST_STRL_ADDR 0x2FF3FD00
-#define SRAM_HDF_WDT_FLAG1 0x2ff3fc00
-#define SRAM_HDF_WDT_FLAG2 0x2ff3fc04
-#define SRAM_HDF_WDT_FLAG3 0x2ff3fc08
-#ifdef __cplusplus
-}
-#endif
-#endif /* __BRDCOMMON_H */
-
diff --git a/HisiPkg/Include/Library/BspUartLib.h b/HisiPkg/Include/Library/BspUartLib.h deleted file mode 100644 index 3faca886d..000000000 --- a/HisiPkg/Include/Library/BspUartLib.h +++ /dev/null @@ -1,95 +0,0 @@ -/*******************************************************************
-#
-#
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-
-
-#ifndef __BSP_UART_H
-#define __BSP_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-#include "Std.h"
-#define UART_SEND_DELAY (500000)
-
-#define SERIAL_0_BASE_ADR 0xe4007000
-#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_RBR)
-#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_THR)
-#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL)
-#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH)
-#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL)
-#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR)
-#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR)
-#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR)
-#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR)
-#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR)
-
-#define UART_RBR 0x00
-#define UART_THR 0x00
-#define UART_DLL 0x00
-#define UART_DLH 0x04
-#define UART_IEL 0x04
-#define UART_IIR 0x08
-#define UART_FCR 0x08
-#define UART_LCR 0x0C
-#define UART_MCR 0x10
-#define UART_LSR 0x14
-#define UART_USR 0x7C
-
-/* register definitions */
-#define UART_FCR_EN 0x01
-#define UART_FCR_RXCLR 0x02
-#define UART_FCR_TXCLR 0x04
-#define UART_FCR_CLEARFIFO 0x00
-
-#define UART_LCR_DLAB 0x80
-#define UART_LCR_EPS 0x10
-#define UART_LCR_PEN 0x08
-#define UART_LCR_STOP 0x04
-#define UART_LCR_DLS8 0x03
-#define UART_LCR_DLS7 0x02
-#define UART_LCR_DLS6 0x01
-#define UART_LCR_DLS5 0x00
-
-#define UART_LSR_TEMT 0x40
-#define UART_LSR_THRE 0x20
-#define UART_LSR_BI 0x10
-#define UART_LSR_FE 0x08
-#define UART_LSR_PE 0x04
-#define UART_LSR_R 0x02
-#define UART_LSR_DR 0x01
-
-#define UART_USR_BUSY 0x01
-#define UART_USR_TFNF 0x02
-#define UART_USR_TFE 0x04
-#define UART_USR_RFNE 0x08
-#define UART_USR_RFF 0x10
-
-#define HI1210_SC_PRECTRL3 0x34
-#define HI1380_SC_PRECTRL1 0x20
-#define HI1380_SC_PRECTRL9 0x50
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-extern void BspSendChar(char scShowChar);
-extern char BspGetChar(U32 ulTimeout);
-
-#ifdef __cplusplus
- }
-#endif /* __cplusplus */
-
-#endif /* __BSP_UART_H */
diff --git a/HisiPkg/Include/Library/EblProvisionLib.h b/HisiPkg/Include/Library/EblProvisionLib.h deleted file mode 100644 index 8dcc7ba18..000000000 --- a/HisiPkg/Include/Library/EblProvisionLib.h +++ /dev/null @@ -1,59 +0,0 @@ -/**********************************************************************
-#
-#
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-#ifndef _PROVISION_PATH_H
-#define _PROVISION_PATH_H
-
-#include <Protocol/DevicePath.h>
-#include <Protocol/DevicePathToText.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/DebugLib.h>
-#include <Uefi/UefiBaseType.h>
-#include <Protocol/SimpleFileSystem.h>
-#include <Protocol/SimpleNetwork.h>
-
-typedef struct {
- CHAR16 *Str;
- UINTN Length;
- UINTN Capacity;
-} POOL_PRINT;
-
-EFI_FILE_HANDLE
-LibOpenRoot (
- IN EFI_HANDLE DeviceHandle
- );
-
-EFI_STATUS
-EditHIInputStr (
- IN OUT CHAR16 *CmdLine,
- IN UINTN MaxCmdLine
- );
-
-EFI_STATUS
-EditHIInputAscii (
- IN OUT CHAR8 *CmdLine,
- IN UINTN MaxCmdLine
- );
-
-EFI_STATUS
-GetHIInputAscii (
- IN OUT CHAR8 *CmdLine,
- IN UINTN MaxCmdLine
- );
-
-EFI_STATUS
-GetHIInputInteger (
- OUT UINTN *Integer
- );
-
-#endif
diff --git a/HisiPkg/Include/Library/PinIo_Api.h b/HisiPkg/Include/Library/PinIo_Api.h deleted file mode 100644 index c11ba0c28..000000000 --- a/HisiPkg/Include/Library/PinIo_Api.h +++ /dev/null @@ -1,60 +0,0 @@ -#
-#
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-#ifndef __PINIO_H__
-#define __PINIO_H__
-
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C"{
-#endif
-#endif /* __cplusplus */
-
-#include "Std.h"
-#ifndef INPUT_PIN
-#define INPUT_PIN 0
-#endif
-
-#ifndef OUTPUT_PIN
-#define OUTPUT_PIN 1
-#endif
-#ifndef OPEN_DRAIN
-#define OPEN_DRAIN 1
-#endif
-
-#ifndef NO_OPEN_DRAIN
-#define NO_OPEN_DRAIN 0
-#endif
-
-#ifndef LOW_LEVEL
-#define LOW_LEVEL 0
-#endif
-
-#ifndef HIGH_LEVEL
-#define HIGH_LEVEL 1
-#endif
-
-
-extern U32 GetPortLevel( U32 port, U32 pin );
-extern void PortInit( U32 port, U32 pin, U32 dir, U32 openDrain );
-extern void SetPortLevel( U32 port, U32 pin, U32 level );
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif
-#endif /* __cplusplus */
-
-
-#endif /* __PINIO_H__ */
diff --git a/HisiPkg/Include/Library/ResetWdtLib.h b/HisiPkg/Include/Library/ResetWdtLib.h deleted file mode 100644 index 6b157ad90..000000000 --- a/HisiPkg/Include/Library/ResetWdtLib.h +++ /dev/null @@ -1,34 +0,0 @@ -/*******************************************************************************
-#
-#
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-#ifndef __WATCHDOG_RESET__
-#define __WATCHDOG_RESET__
-extern void Delay(unsigned long ulCount);
-extern void WDT_ResetWatchdog(void);
-
-#define GPIO_MASK(index) (0x1UL << index)
-
-#define GPIO3_BASE_ADDR 0xe4003000
-
-#define HIP04_IOPAD_REG 0xe400c000
-#define HIP04_WDOG_PORT 0x1A0 //GPIO98
-#define HIP04_SGMI_PORT 0x1AC //GPIO101
-#define HIP04_MII_PORT 0x1B0 //GPIO102
-#define HIP04_RST_PORT 0x1B4 //GPIO103
-
-#define writel_wdt(val,addr) ((*(volatile unsigned int *)(addr)) = (val))
-#define outl_wdt(val,addr) ((void) writel_wdt ((val),addr))
-#define readl_wdt(addr) (*(volatile unsigned int *)(addr))
-#define inl_wdt(addr) (readl_wdt(addr))
-
-#endif
diff --git a/HisiPkg/Include/Library/Std.h b/HisiPkg/Include/Library/Std.h deleted file mode 100644 index 60648477c..000000000 --- a/HisiPkg/Include/Library/Std.h +++ /dev/null @@ -1,147 +0,0 @@ -/*******************************************************************
-#
-#
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-
-
-
-
-#ifndef __std_H
-#define __std_H
-
-
-#ifndef _ASMLANGUAGE
-
-typedef int STATUS;
-typedef int INT;
-typedef unsigned int size_t;
-
-typedef signed char S8;
-typedef signed short S16;
-typedef signed int S32;
-
-#ifndef VC_DEBUG_MODE
-typedef long long S64;
-#else
-typedef __int64 S64;
-#endif
-
-#ifndef U8
-typedef unsigned char U8;
-#endif
-
-#ifndef U16
-typedef unsigned short U16;
-#endif
-
-#ifndef U32
-typedef unsigned int U32;
-#endif
-
-#ifndef VC_DEBUG_MODE
-typedef unsigned long long U64;
-#else
-typedef unsigned __int64 U64;
-#endif
-
-#ifndef LONG
-typedef long LONG;
-#endif
-#ifndef CHAR
-typedef char CHAR;
-#endif
-
-typedef volatile unsigned char V8;
-typedef volatile unsigned short V16;
-typedef volatile unsigned int V32;
-
-#ifndef VC_DEBUG_MODE
-typedef volatile unsigned long long V64;
-#else
-typedef volatile unsigned __int64 V64;
-#endif
-
-#ifndef VC_DEBUG_MODE
-typedef char BYTE;
-#endif
-
-typedef unsigned char UBYTE;
-typedef short HWORD;
-typedef unsigned short UHWORD;
-
-#ifndef VC_DEBUG_MODE
-/*typedef long WORD;*/
-typedef unsigned long UWORD;
-#endif
-
-
-
-
-typedef volatile char VBYTE;
-typedef volatile unsigned char VUBYTE;
-typedef volatile short VHWORD;
-typedef volatile unsigned short VUHWORD;
-typedef volatile long VWORD;
-typedef volatile unsigned long VUWORD;
-
-#ifndef ERROR
-#define ERROR -1
-#endif
-
-#ifndef OK
-#define OK 0
-#endif
-#ifndef BOOL
-#define BOOL int
-#endif
-#ifndef BYTE_SWAP32
-#define BYTE_SWAP32(x) ((((unsigned)(x) & 0x000000ff) << 24) | \
- (((x) & 0x0000ff00) << 8) | \
- (((x) & 0x00ff0000) >> 8) | \
- (((x) & 0xff000000) >> 24))
-#endif
-
-#ifndef BYTE_SWAP16
-#define BYTE_SWAP16(x) ((((x) & 0x00ff) <<8) | \
- (((x) & 0xff00) >> 8))
-#endif
-#define CPU_RAM_HDF_BAK_VERSION_FLAG (0)
-#define CPU_RAM_HDF_MAIN_VERSION_FLAG (1)
-#define REG_WRITE(addr,data) (*(volatile UINT32 *)(addr) = (data))
-#define REG_READ(addr,data) ((data) = *(volatile UINT32 *)(addr))
-
-#define SYS_CTRL_REG_WRITE(offset,data) (REG_WRITE((offset), (data)))
-#define SYS_CTRL_REG_READ(offset,data) do \
- { \
- (REG_READ((offset), (data))); \
- }while(0)
-#ifndef MEM_MMU_OFFSET
-//#define MEM_MMU_OFFSET 0x80000000
-#define MEM_MMU_OFFSET 0x00
-#endif
-#define NELEMENTS(array) (sizeof (array) / sizeof ((array) [0]))
-
-
-#define REG64(Addr) (*(volatile unsigned long long *)(Addr))
-#define REG32(Addr) (*(volatile unsigned int *)(Addr))
-#define REG16(Addr) (*(volatile unsigned short *)(Addr))
-#define REG8(Addr) (*(volatile unsigned char *)(Addr))
-
-U32 vxImmrGet (void);
-
-#endif
-
-#define SIZE_1 1
-#define SIZE_4 4
-#define SIZE_59 59
-#endif /* __std_H */
diff --git a/HisiPkg/Include/Library/SysUtilLib.h b/HisiPkg/Include/Library/SysUtilLib.h deleted file mode 100644 index bf778f48f..000000000 --- a/HisiPkg/Include/Library/SysUtilLib.h +++ /dev/null @@ -1,41 +0,0 @@ -/*************************************************************
-#
-#
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-#ifndef __SYS_UTIL_LIB__
-#define __SYS_UTIL_LIB__
-
-#include "Std.h"
-
-#define SC_PCB_BIT (16)
-#define SC_PCB_MASK (0xF)
-
-
-extern U32 GET_ClkFreq(U32* psysClkReg);
-extern U32 GET_InterTimerRefPreq(void);
-extern U32 BSP_GetStartBootNo(void);
-
-extern void TMBInit (void);
-extern void sysUsDelay(U32 delay);
-extern void delayUSec(U32 delay);
-extern U32 BSP_GetTimeBaseVal(U32 *pulTimeL, U32 *pulTimeH );
-extern U32 BSP_GetTimeBase(U32 *pulTimeL, U32 *pulTimeH );
-extern void TMB_Read(U32* pulValueHigh, U32* pulValueLow);
-extern int bUnzipPlus(
- long lInputLen,
- void* pInputBuf,
- void* pOutputBuf,
- long* plOutputLen,
- long lCheckLen ,
- char compresstype
- );
-#endif
diff --git a/HisiPkg/Include/Library/config.h b/HisiPkg/Include/Library/config.h deleted file mode 100644 index 3911e236c..000000000 --- a/HisiPkg/Include/Library/config.h +++ /dev/null @@ -1,436 +0,0 @@ -/* config.h - Mistral OMAP35xx configuration header */
-
-/*
- * Copyright (c) 2008-2009 Wind River Systems, Inc.
- * Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
- *
- * The right to copy, distribute, modify or otherwise make use
- * of this software may be licensed only pursuant to the terms
- * of an applicable Wind River license agreement.
- */
-
-/*
-modification history
---------------------
-01f,25mar09,m_h add support for copyback cache & RTP
-01e,19mar09,m_h Cache is writethrough not copyback
-01d,19feb09,m_h cleanup
-01c,22jan09,m_h OneNand Flash Support
-01b,24nov08,m_h Configure to add networking
-01a,16jun08,m_h created.
-*/
-
-/*
-DESCRIPTION
-This module contains the configuration parameters for the Mistral OMAP35xx BSP.
-*/
-
-#ifndef __INCconfigh
-#define __INCconfigh
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* BSP version/revision identification, before configAll.h */
-
-#define BSP_VER_1_1 1 /* 1.2 is backwards compatible with 1.1 */
-#define BSP_VER_1_2 1
-#define BSP_VERSION "2.0"
-#define BSP_REV "/0" /* 0 for first revision */
-
-//#include <configAll.h>
-/*
- * vxbus support
- */
-#ifdef _BSP_BUILD_VXWORKS
-#define INCLUDE_VXBUS
-#else
-#undef INCLUDE_VXBUS
-#endif
-#ifdef INCLUDE_VXBUS
-#define INCLUDE_HWMEM_ALLOC
-#define INCLUDE_VXB_CMDLINE
-
-#define HWMEM_POOL_SIZE 50000
-
-#endif /* INCLUDE_VXBUS */
-
-/*
- * SYS_MODEL define
- *
- */
-
-#define SYS_MODEL "HISILICON - CortexA9 (ARM)"
-
-
-/* Support network devices */
-#define INCLUDE_NET_DAEMON
-#undef INCLUDE_APPL_LOG_UTIL
-#undef INCLUDE_END2_LINKBUFPOOL
-
-#define DEFAULT_BOOT_LINE \
- "HiFE(0,0)OMC:vxWorks.bin h=192.168.0.200 e=192.168.0.100 u=aa pw=123"
-
-
-
-#ifndef HDF_MASTER_CORE_FLAG
-#define HDF_MASTER_CORE_FLAG 0
-#define HDF_SLAVE_CORE_FLAG 1
-#define HDF_BOOTROM_COMPILE_FLAG 0
-#define HDF_VXWORKS_COMPILE_FLAG 1
-#endif
-
-
-
-
-
-/* Memory configuration */
-#undef LOCAL_MEM_AUTOSIZE /* run-time memory sizing */
-
-#ifndef _BSP_BUILD_VXWORKS
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#else
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#endif
-#else
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#else
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#endif
-#endif
-
-#define LOCAL_MEM_LOCAL_ADRS (0x0)
-
-
-
-#ifndef _BSP_BUILD_VXWORKS
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#else
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#endif
-#else
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#else
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#endif
-
-#endif
-#define LOCAL_MEM_END_ADRS (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE)
-
-
-/*
- * Boot ROM is an image written into Flash. Part of the Flash can be
- * reserved for boot parameters etc. (see the Flash section below).
- *
- * The following parameters are defined here and in the Makefile.
- * They must be kept synchronized; effectively config.h depends on Makefile.
- * Any changes made here must be made in the Makefile and vice versa.
- *
- * ROM_BASE_ADRS is the base of the Flash ROM/EPROM.
- * ROM_TEXT_ADRS is the entry point of the VxWorks image
- * ROM_SIZE is the size of the part of the Flash ROM/EPROM allocated to
- * the VxWorks image (block size - size of headers)
- *
- * Two other constants are used:
- * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
- * (e.g. in uncompressed boot ROM)
- * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
- *
- * The values are given as literals here to make it easier to ensure
- * that they are the same as those in the Makefile.
- */
-
-#undef RAM_LOW_ADRS
-#undef RAM_HIGH_ADRS
-
-#define IMAGE_LOW_ADRS 0x00a00000
-
-/* VxWorks entry link address */
-#define VXWORKS_ENTRY IMAGE_LOW_ADRS
-
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define RAM_LOW_ADRS 0x00200000 /* VxWorks image entry point */
-#define RAM_HIGH_ADRS 0x03000000 /* RAM address for ROM boot */
-
-#else
-
-#ifndef _BSP_BUILD_VXWORKS
-#define ROM_BASE_ADRS (HDFINF_GetTextBase())
-#define ROM_TEXT_ADRS (HDFINF_GetTextBase())
-#define RAM_LOW_ADRS 0x05000000 /* VxWorks image entry point */
-#define RAM_HIGH_ADRS 0x06000000 /* RAM address for ROM boot */
-#else
-#define ROM_BASE_ADRS 0x40200000 /* base of Flash/EPROM */
-#define ROM_TEXT_ADRS 0x40200000 /* code start addr in ROM */
-#define RAM_LOW_ADRS IMAGE_LOW_ADRS /* VxWorks image entry point */
-#define RAM_HIGH_ADRS 0x05000000 /* RAM address for ROM boot */
-#endif
-
-#endif
-
-#undef ROM_SIZE
-#define ROM_SIZE 0x00200000 /* size of ROM holding VxWorks*/
-
-
-/*
- * Flash/NVRAM memory configuration
- *
- * A block of the Flash memory (FLASH_SIZE bytes at FLASH_ADRS) is
- * reserved for non-volatile storage of data.
- *
- */
-
-#undef INCLUDE_FLASH
-
-/* Serial port configuration */
-
-#define N_SIO_CHANNELS 3
-
-#undef NUM_TTY
-#define NUM_TTY N_SIO_CHANNELS
-
-#define DEFAULT_BAUD (HDF_GetUartBaudRate())
-
-/* Console baud rate reconfiguration. */
-#undef CONSOLE_BAUD_RATE
-#define CONSOLE_BAUD_RATE DEFAULT_BAUD /* Reconfigure default baud rate */
-
-/*
- * Define SERIAL_DEBUG to enable debugging
- * via the serial ports
- */
-
-#undef SERIAL_DEBUG
-#undef INCLUDE_BOOT_WDB
-
-#undef INCLUDE_WDB
-
-
-
-#if defined(INCLUDE_WDB) || defined (INCLUDE_BOOT_WDB)
-# undef WDB_COMM_TYPE
-# undef WDB_TTY_BAUD
-# undef WDB_TTY_CHANNEL
-# undef WDB_TTY_DEV_NAME
-# ifdef SERIAL_DEBUG
-# define WDB_NO_BAUD_AUTO_CONFIG
-# define WDB_COMM_TYPE WDB_COMM_SERIAL /* WDB in Serial mode */
-# define WDB_TTY_BAUD 38400 /* Baud rate for WDB Connctn */
-# define WDB_TTY_CHANNEL 1 /* COM PORT #2 */
-# define WDB_TTY_DEV_NAME "/tyCo/1" /* deflt TYCODRV_5_2 dev name */
-# else /* SERIAL_DEBUG */
-# define WDB_COMM_TYPE WDB_COMM_END
-# define WDB_TTY_BAUD DEFAULT_BAUD /* Baud rate for WDB Connctn */
-# define WDB_TTY_CHANNEL 0 /* COM PORT #1 */
-# define WDB_TTY_DEV_NAME "/tyCo/0" /* deflt TYCODRV_5_2 dev name */
-# endif /* SERIAL_DEBUG */
-#endif /* INCLUDE_WDB || INCLUDE_BOOT_WDB */
-
-
-/*
- * We use the generic architecture libraries, with caches/MMUs present. A
- * call to sysHwInit0() is needed from within usrInit before
- * cacheLibInit() is called.
- */
-
-/*
- * Cache/MMU configuration
- *
- * Note that when MMU is enabled, cache modes are controlled by
- * the MMU table entries in sysPhysMemDesc[], not the cache mode
- * macros defined here.
- */
-#define SYS_CACHE_UNCACHED_ADRS 0xffffffff/*OMAP35XX_L4_MPU_INTC*/
-
-# undef USER_I_CACHE_MODE
-# define USER_I_CACHE_MODE CACHE_COPYBACK
-
-# undef USER_D_CACHE_MODE
-# define USER_D_CACHE_MODE CACHE_COPYBACK
-
-
-/* Include MMU BASIC and CACHE support for command line and project builds */
-
-# define INCLUDE_MMU_BASIC
-# define INCLUDE_BOOT_MMU_BASIC
-# define INCLUDE_CACHE_SUPPORT
-
-#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
-# define INCLUDE_MMU
-#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
-
-/* Include MMU BASIC and CACHE support for command line and project builds */
-
-# define INCLUDE_MMU_BASIC
-# define INCLUDE_BOOT_MMU_BASIC
-# define INCLUDE_CACHE_SUPPORT
-
-#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
-# define INCLUDE_MMU
-#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
-
-#ifndef MEM_MMU_OFFSET
-#define MEM_MMU_OFFSET 0x00
-#endif
-
-/*
- * Network driver configuration.
- *
- * De-select unused (default) network drivers selected in configAll.h.
- */
-
-#undef INCLUDE_ENP /* include CMC Ethernet interface*/
-#undef INCLUDE_EX /* include Excelan Ethernet interface */
-#undef INCLUDE_SM_NET /* include backplane net interface */
-#undef INCLUDE_SM_SEQ_ADDR /* shared memory network auto address setup */
-
-#define INCLUDE_IPCOM_USE_AUTH_RADIUS
-
-
-/* Enhanced Network Driver (END) Support */
-
-#define INCLUDE_END
-
-#ifdef INCLUDE_END
-# ifndef SERIAL_DEBUG
-# define WBD_AGENT_END
-# else
-# undef WBD_AGENT_END
-# endif /* SERIAL_DEBUG */
-
-#endif /* INCLUDE_END */
-
-#ifdef _BSP_BUILD_VXWORKS
-#ifndef _CONTROL_SLAVE_CORE_IMG
-#if 1
-#define INCLUDE_USB
-#define INCLUDE_USB_INIT
-
-/*ehci*/
-#define INCLUDE_EHCI
-#define INCLUDE_EHCI_INIT
-#define INCLUDE_EHCI_BUS
-
-/*ohci*/
-#define INCLUDE_OHCI
-#define INCLUDE_OHCI_INIT
-#define INCLUDE_OHCI_BUS
-
-/*MASS STORGY device*/
-#define INCLUDE_USB_MS_BULKONLY
-#define INCLUDE_USB_MS_BULKONLY_INIT
-#define INCLUDE_USB_MS_CBI
-#define INCLUDE_USB_MS_CBI_INIT
-#define INCLUDE_NOR_FILESYS
-#endif
-#endif
-#endif
-
-#define INCLUDE_BSP_WATCHDOG
-
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#undef _INCLUDE_FILESYS
-#else
-#define _INCLUDE_FILESYS
-#endif
-
-#undef INCLUDE_TFFS
-
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#undef INCLUDE_DOSFS
-#else
-/*define for FS*/
-#define INCLUDE_DOSFS
-#endif
-
-#define INCLUDE_XBD_RAMDRV /*ramDisk*/
-
-#ifdef INCLUDE_DOSFS
-#define INCLUDE_ERF
-#define INCLUDE_DEVICE_MANAGER
-#define INCLUDE_FS_EVENT_UTIL
-#define INCLUDE_FS_MONITOR
-#define INCLUDE_XBD
-#define INCLUDE_XBD_BLK_DEV
-#define INCLUDE_XBD_TRANS
-#define INCLUDE_DOSFS_DIR_FIXED
-#define INCLUDE_DOSFS_DIR_VFAT
-#define INCLUDE_DOSFS_FAT
-#define INCLUDE_DOSFS_FMT
-#define INCLUDE_DOSFS_CHKDSK
-#define INCLUDE_DOSFS_MAIN
-#endif /* INCLUDE_DOSFS*/
-
-/* I2C not supported */
-#undef INCLUDE_I2C
-
-/* touch screen not supported */
-#undef INCLUDE_TOUCHSCREEN
-
-/*
- * Interrupt mode. Preemptive interrupts are not supported by the interrupt
- * driver so INT_MODE must be set to INT_NON_PREEMPT_MODEL.
- */
-
-#define INT_MODE INT_NON_PREEMPT_MODEL
-
-/*
- * miscellaneous definitions
- * Note: ISR_STACK_SIZE is defined here rather than in ../all/configAll.h
- * (as is more usual) because the stack size depends on the interrupt
- * structure of the BSP.
- */
-
-#define ISR_STACK_SIZE 0x2000 /* size of ISR stack, in bytes */
-
-/* Optional timestamp support */
-
-#undef INCLUDE_TIMESTAMP /* define to include timestamp driver */
-#define INCLUDE_TIMESTAMP
-
-#ifndef INCLUDE_LOADER
-#define INCLUDE_LOADER
-#endif
-#ifndef INCLUDE_LOADER_HOOKS
-#define INCLUDE_LOADER_HOOKS
-#endif
-#ifndef INCLUDE_PTYDRV
-#define INCLUDE_PTYDRV /* pseudo terminal driver */
-#endif
-/*script*/
-#ifndef INCLUDE_STARTUP_SCRIPT
-#define INCLUDE_STARTUP_SCRIPT
-#endif
-
-
-#define INCLUDE_SHELL_INTERP_C /* C interpreter */
-#define INCLUDE_SHELL_INTERP_CMD /* shell command interpreter */
-
-#undef SHELL_COMPATIBLE
-#define SHELL_COMPATIBLE TRUE
-
-#ifndef BSP_BUILD_BASIC_BTRM
-#define INCLUDE_RAWFS
-#define INCLUDE_XBD_RAMDRV
-#endif
-#ifndef _CONTROL_SLAVE_CORE_IMG
-#ifdef _BSP_BUILD_VXWORKS
-#define INCLUDE_SECURITY
-#endif
-#endif
-#ifdef INCLUDE_SECURITY
-#define LOGIN_USER_NAME "target"
-#endif
-
-#include "BrdCommon.h"
-//#include "configExtend.h"
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __INCconfigh */
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