diff options
| -rw-r--r-- | src/cpu/aarch64/vm/aarch64.ad | 4 | ||||
| -rw-r--r-- | src/cpu/aarch64/vm/macroAssembler_aarch64.hpp | 8 |
2 files changed, 9 insertions, 3 deletions
diff --git a/src/cpu/aarch64/vm/aarch64.ad b/src/cpu/aarch64/vm/aarch64.ad index 7051ebf43..12de3c2d9 100644 --- a/src/cpu/aarch64/vm/aarch64.ad +++ b/src/cpu/aarch64/vm/aarch64.ad @@ -7507,8 +7507,8 @@ instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr) %{ format %{ "negw $dst, $src\t# int" %} ins_encode %{ - __ negsw(as_Register($dst$$reg), - as_Register($src$$reg)); + __ negw(as_Register($dst$$reg), + as_Register($src$$reg)); %} ins_pipe(pipe_class_default); diff --git a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp index 0dc7eb094..3e240b57a 100644 --- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp +++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp @@ -179,11 +179,17 @@ class MacroAssembler: public Assembler { void cset(Register Rd, Assembler::Condition cond) { csinc(Rd, zr, zr, ~cond); } - void csetw(Register Rd, Assembler::Condition cond) { csincw(Rd, zr, zr, ~cond); } + void cneg(Register Rd, Register Rn, Assembler::Condition cond) { + csneg(Rd, Rn, Rn, ~cond); + } + void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { + csnegw(Rd, Rn, Rn, ~cond); + } + inline void movw(Register Rd, Register Rn) { if (Rd == sp || Rn == sp) { addw(Rd, Rn, 0U); |