diff options
Diffstat (limited to 'arch/arm/boot/dts/hi3620.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index b768d2b0dbd..5bd415d5b91 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -848,6 +848,34 @@ clock-output-names = "clk_dphy2"; hisilicon,hi3620-clkgate = <0x30 0x20000>; }; + ldiclk0: clkgate@65 { + compatible = "hisilicon,hi3620-clk-gate"; + #clock-cells = <0>; + clocks = <&refclk_ldi0>; + clock-output-names = "clk_ldi0"; + hisilicon,hi3620-clkgate = <0x30 0x200>; + }; + ldiclk1: clkgate@66 { + compatible = "hisilicon,hi3620-clk-gate"; + #clock-cells = <0>; + clocks = <&refclk_ldi1>; + clock-output-names = "clk_ldi1"; + hisilicon,hi3620-clkgate = <0x30 0x800>; + }; + edcclk0: clkgate@67 { + compatible = "hisilicon,hi3620-clk-gate"; + #clock-cells = <0>; + clocks = <&pclk>; + clock-output-names = "clk_edc0"; + hisilicon,hi3620-clkgate = <0x30 0x100>; + }; + edcclk1: clkgate@68 { + compatible = "hisilicon,hi3620-clk-gate"; + #clock-cells = <0>; + clocks = <&pclk>; + clock-output-names = "clk_edc1"; + hisilicon,hi3620-clkgate = <0x30 0x400>; + }; dtable: clkdiv@0 { #hisilicon,clkdiv-table-cells = <2>; }; @@ -1544,5 +1572,49 @@ clocks = <&kpcclk>; status = "disabled"; }; + edc0: edc@fa202000 { + compatible = "hisilicon,hi3620-fb"; + reg = <0xfa202000 0x1000>; + clocks = <&ldiclk0 &edcclk0 &dsiclk0 &lanebyteclk0>; + clock-names = "ldi", "edc", "dsi", "lane"; + interrupts = <0 38 0x4>, <0 39 0x4>, <0 40 0x4>; + interrupt-names = "edc", "ldi", "dsi"; + status = "disabled"; + + dsi2xclk0: clkdsi@0 { + compatible = "hisilicon,hi3620-phy"; + #clock-cells = <0>; + clocks = <&osc26m>; + clock-output-names = "clk_dsi2x0"; + }; + dsiclk0: clkdsi@1 { + compatible = "hisilicon,clk-fixed-factor"; + #clock-cells = <0>; + clocks = <&dsi2xclk0>; + clock-output-names = "clk_dsi0"; + /*mult, div*/ + hisilicon,fixed-factor = <1 2>; + }; + lanebyteclk0: clkdsi@2 { + compatible = "hisilicon,clk-fixed-factor"; + #clock-cells = <0>; + clocks = <&dsi2xclk0>; + clock-output-names = "clk_lanebyte0"; + /*mult, div*/ + hisilicon,fixed-factor = <1 8>; + }; + escclk0: clkdsi@3 { + compatible = "hisilicon,hi3620-phy-esc"; + #clock-cells = <0>; + clocks = <&lanebyteclk0>; + clock-output-names = "clk_dsi_phy_esc0"; + }; + }; + edc1: edc@fa206900 { + compatible = "hisilicon,hi3620-fb"; + clocks = <&ldiclk1 &edcclk1>; + clock-names = "ldi", "edc"; + status = "disabled"; + }; }; }; |