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/*
* Copyright 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IMX_IO_MUX_H
#define IMX_IO_MUX_H
#include <stdint.h>
/*
* i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017
* Section 30.5 IOMUXC Memory Map/Register Definition
*/
#define IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE0_GPIO5_IO10_OFFSET 0x0014
#define IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE1_GPIO5_IO11_OFFSET 0x0018
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0_GPIO5_IO00_OFFSET 0x001C
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1_GPIO5_IO01_OFFSET 0x0020
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER2_GPIO5_IO02_OFFSET 0x0024
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER3_GPIO5_IO03_OFFSET 0x0028
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER4_GPIO5_IO04_OFFSET 0x002C
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5_GPIO5_IO05_OFFSET 0x0030
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6_GPIO5_IO06_OFFSET 0x0034
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER7_GPIO5_IO07_OFFSET 0x0038
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER8_GPIO5_IO08_OFFSET 0x003C
#define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER9_GPIO5_IO09_OFFSET 0x0040
#define IOMUXC_SW_MUX_CTL_PAD_JTAG_MOD_SJC_MOD_OFFSET 0x0044
#define IOMUXC_SW_MUX_CTL_PAD_JTAG_TMS_SJC_TMS_OFFSET 0x0048
#define IOMUXC_SW_MUX_CTL_PAD_JTAG_TDO_SJC_TDO_OFFSET 0x004C
#define IOMUXC_SW_MUX_CTL_PAD_JTAG_TDI_SJC_TDI_OFFSET 0x0050
#define IOMUXC_SW_MUX_CTL_PAD_JTAG_TCK_SJC_TCK_OFFSET 0x0054
#define IOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B_SJC_TRSTB_OFFSET 0x0058
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_I2C2_SCL_OFFSET 0x005C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_I2C2_SDA_OFFSET 0x0060
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_I2C1_SCL_OFFSET 0x0064
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_I2C1_SDA_OFFSET 0x0068
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_ENET1_REF_CLK1_OFFSET 0x006C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_ENET2_REF_CLK2_OFFSET 0x0070
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_ENET1_MDIO_OFFSET 0x0074
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_ENET1_MDC_OFFSET 0x0078
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_PWM1_OUT_OFFSET 0x007C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_PWM2_OUT_OFFSET 0x0080
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_UART1_DCE_TX_OFFSET 0x0084
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_UART1_DCE_RX_OFFSET 0x0088
#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B_UART1_DCE_CTS_OFFSET 0x008C
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B_UART1_DCE_RTS_OFFSET 0x0090
#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_UART2_DCE_TX_OFFSET 0x0094
#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_UART2_DCE_RX_OFFSET 0x0098
#define IOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B_UART2_DCE_CTS_OFFSET 0x009C
#define IOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B_UART2_DCE_RTS_OFFSET 0x00A0
#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_UART3_DCE_TX_OFFSET 0x00A4
#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_UART3_DCE_RX_OFFSET 0x00A8
#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_UART3_DCE_CTS_OFFSET 0x00AC
#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_UART3_DCE_RTS_OFFSET 0x00B0
#define IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA_UART4_DCE_TX_OFFSET0 0x00B4
#define IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA_UART4_DCE_RX_OFFSET 0x00B8
#define IOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA_UART5_DCE_TX_OFFSET 0x00BC
#define IOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA_UART5_DCE_RX_OFFSET 0x00C0
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0_ENET1_RDATA00_OFFSET 0x00C4
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1_ENET1_RDATA01_OFFSET 0x00C8
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN_ENET1_RX_EN_OFFSET 0x00CC
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0_ENET1_TDATA00_OFFSET 0x00D0
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1_ENET1_TDATA01_OFFSET 0x00D4
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN_ENET1_TX_EN_OFFSET 0x00D8
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_ENET1_TX_CLK_OFFSET 0x00DC
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER_ENET1_RX_ER_OFFSET 0x00E0
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0_ENET2_RDATA00_OFFSET 0x00E4
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1_ENET2_RDATA01_OFFSET 0x00E8
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN_ENET2_RX_EN_OFFSET 0x00EC
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0_ENET2_TDATA00_OFFSET 0x00F0
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1_ENET2_TDATA01_OFFSET 0x00F4
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN_ENET2_TX_EN_OFFSET 0x00F8
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_ENET2_TX_CLK_OFFSET 0x00FC
#define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER_ENET2_RX_ER_OFFSET 0x0100
#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_LCDIF_CLK_OFFSET 0x0104
#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_LCDIF_ENABLE_OFFSET 0x0108
#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_LCDIF_HSYNC_OFFSET 0x010C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_LCDIF_VSYNC_OFFSET 0x0110
#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_LCDIF_RESET_OFFSET 0x0114
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_LCDIF_DATA00_OFFSET 0x0118
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_LCDIF_DATA01_OFFSET 0x011C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_LCDIF_DATA02_OFFSET 0x0120
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_LCDIF_DATA03_OFFSET 0x0124
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_LCDIF_DATA04_OFFSET 0x0128
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_LCDIF_DATA05_OFFSET 0x012C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_LCDIF_DATA06_OFFSET 0x0130
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_LCDIF_DATA07_OFFSET 0x0134
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_LCDIF_DATA08_OFFSET 0x0138
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_LCDIF_DATA09_OFFSET 0x013C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_LCDIF_DATA10_OFFSET 0x0140
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_LCDIF_DATA11_OFFSET 0x0144
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_LCDIF_DATA12_OFFSET 0x0148
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_LCDIF_DATA13_OFFSET 0x014C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_LCDIF_DATA14_OFFSET 0x0150
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_LCDIF_DATA15_OFFSET 0x0154
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_LCDIF_DATA16_OFFSET 0x0158
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_LCDIF_DATA17_OFFSET 0x015C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_LCDIF_DATA18_OFFSET 0x0160
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_LCDIF_DATA19_OFFSET 0x0164
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_LCDIF_DATA20_OFFSET 0x0168
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_LCDIF_DATA21_OFFSET 0x016C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_LCDIF_DATA22_OFFSET 0x0170
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_LCDIF_DATA23_OFFSET 0x0174
#define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_RAWNAND_RE_B_OFFSET 0x0178
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_RAWNAND_WE_B_OFFSET 0x017C
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RAWNAND_DATA00_OFFSET 0x0180
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RAWNAND_DATA01_OFFSET 0x0184
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RAWNAND_DATA02_OFFSET 0x0188
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RAWNAND_DATA03_OFFSET 0x018C
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RAWNAND_DATA04_OFFSET 0x0190
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RAWNAND_DATA05_OFFSET 0x0194
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RAWNAND_DATA06_OFFSET 0x0198
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RAWNAND_DATA07_OFFSET 0x019C
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RAWNAND_ALE_OFFSET 0x01A0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RAWNAND_WP_B_OFFSET 0x01A4
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_OFFSET 0x01A8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_ALT0_UART3_TX 0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_ALT1_USDHC1_DATA4 BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_ALT2_QSPI_A_DATA00 BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_ALT3_ECSPI3_SS0 BIT(1) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_ALT4_EIM_CS1_B BIT(2)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_ALT6_GPIO4_IO12 BIT(2) | BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_ALT8_UART3_TX BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_OFFSET 0x01AC
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_ALT0_RAWNAND_CE0_B 0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_ALT1_USDHC1_DATA5 BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_ALT2_QSPI_A_DATA01 BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_ALT3_ECSPI3_SCLK BIT(1) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_ALT4_EIM_DTACK_B BIT(2)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_ALT6_GPIO4_IO13 BIT(2) | BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_ALT8_UART3_RX BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_RAWNAND_CE1_B_OFFSET 0x01B0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE1_B_ALT0_RAWNAND_CE1_B 0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE1_B_ALT1_USDHC1_DATA6 BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE1_B_ALT2_QSPI_A_DATA02 BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE1_B_ALT3_ECSPI3_MOSCI BIT(1) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE1_B_ALT4_EIM_ADDR18 BIT(2)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE1_B_ALT6_GPIO4_IO14 BIT(2) | BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE1_B_ALT8_UART3_CTS_B BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_OFFSET 0x01B4
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_ALT0_RAWNAND_CLE 0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_ALT1_USDHC1_DATA7 BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_ALT2_QSPI_A_DATA03 BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_ALT3_ECSPI3_MISO BIT(1) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_ALT4_EIM_ADDR16 BIT(2)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_ALT6_GPIO4_IO15 BIT(2) | BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_ALT8_UART3_RTS_B BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DQS_RAWNAND_DQS_OFFSET 0x01B8
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_USDHC1_CMD_OFFSET 0x01BC
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_USDHC1_CLK_OFFSET 0x01C0
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_USDHC1_DATA0_OFFSET 0x01C4
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_USDHC1_DATA1_OFFSET 0x01C8
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_USDHC1_DATA2_OFFSET 0x01CC
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_USDHC1_DATA3_OFFSET 0x01D0
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_OFFSET 0x01D4
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT0_CSI_MCLK 0
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT1_USDHC2_CD_B BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT2_RAWNAND_CE2_B BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT3_I2C1_SDA BIT(1) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT4_EIM_CS0_B BIT(2)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT5_GPIO4_IO17 BIT(2) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT6_SNVS_HP_VIO_5_CTL BIT(2) | BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_ALT8_UART6_TX BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_OFFSET 0x01D8
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT0_CSI_PIXCLK 0
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT1_USDHC2_WP BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT2_RAWNAND_CE3_B BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT3_I2C1_SCL BIT(1) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT4_EIM_OE BIT(2)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT5_GPIO4_IO18 BIT(2) | BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT6_SNVS_HP_VIO_5 BIT(2) | BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_ALT8_UART6_RX BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_CSI_VSYNC_OFFSET 0x01DC
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_CSI_DATA02_OFFSET 0x01E4
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_CSI_DATA03_OFFSET 0x01E8
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_CSI_DATA04_OFFSET 0x01EC
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_CSI_DATA05_OFFSET 0x01F0
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_CSI_DATA06_OFFSET 0x01F4
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_CSI_DATA07_OFFSET 0x01F8
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_CSI_DATA08_OFFSET 0x01FC
#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_CSI_DATA09_OFFSET 0x0200
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_OFFSET 0x0204
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_OFFSET 0x0208
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_OFFSET 0x020C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_OFFSET 0x0210
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_OFFSET 0x0214
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_OFFSET 0x0218
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_OFFSET 0x021C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_OFFSET 0x0220
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_OFFSET 0x0224
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_OFFSET 0x0228
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_OFFSET 0x022C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_OFFSET 0x0230
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_OFFSET 0x0234
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_OFFSET 0x0238
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_OFFSET 0x023C
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_OFFSET 0x0240
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_OFFSET 0x0244
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_OFFSET 0x0248
#define IOMUXC_SW_PAD_CTL_PAD_RAS_B_OFFSET 0x024C
#define IOMUXC_SW_PAD_CTL_PAD_CAS_B_OFFSET 0x0250
#define IOMUXC_SW_PAD_CTL_PAD_CS0_B_OFFSET 0x0254
#define IOMUXC_SW_PAD_CTL_PAD_CS1_B_OFFSET 0x0258
#define IOMUXC_SW_PAD_CTL_PAD_SDWE_B_OFFSET 0x025C
#define IOMUXC_SW_PAD_CTL_PAD_ODT0_OFFSET 0x0260
#define IOMUXC_SW_PAD_CTL_PAD_ODT1_OFFSET 0x0264
#define IOMUXC_SW_PAD_CTL_PAD_SDBA0_OFFSET 0x0268
#define IOMUXC_SW_PAD_CTL_PAD_SDBA1_OFFSET 0x026C
#define IOMUXC_SW_PAD_CTL_PAD_SDBA2_OFFSET 0x0270
#define IOMUXC_SW_PAD_CTL_PAD_SDCKE0_OFFSET 0x0274
#define IOMUXC_SW_PAD_CTL_PAD_SDCKE1_OFFSET 0x0278
#define IOMUXC_SW_PAD_CTL_PAD_SDCLK0_P_OFFSET 0x027C
#define IOMUXC_SW_PAD_CTL_PAD_SDQS0_P_OFFSET 0x0280
#define IOMUXC_SW_PAD_CTL_PAD_SDQS1_P_OFFSET 0x0284
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_OFFSET 0x0288
/*
* The above offsets are all replicated from this base for each pin
* So we can calculate the IOMUXC_SW_PAD_CTRL_REGISTER_OFFSET given the
* IOMUXC_SW_MUX_CTL_PAD_REGISTER_OFFSET
*/
#define IOMUXC_SW_PAD_CTRL_BASE_OFFSET 0x028C
#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0_GPIO5_IO10_OFFSET (IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE0_GPIO5_IO10_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1_GPIO5_IO11_OFFSET (IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE1_GPIO5_IO11_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0_GPIO5_IO00_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0_GPIO5_IO00_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1_GPIO5_IO01_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1_GPIO5_IO01_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER2_GPIO5_IO02_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER2_GPIO5_IO02_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER3_GPIO5_IO03_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER3_GPIO5_IO03_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER4_GPIO5_IO04_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER4_GPIO5_IO04_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5_GPIO5_IO05_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5_GPIO5_IO05_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6_GPIO5_IO06_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6_GPIO5_IO06_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER7_GPIO5_IO07_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER7_GPIO5_IO07_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER8_GPIO5_IO08_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER8_GPIO5_IO08_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER9_GPIO5_IO09_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER9_GPIO5_IO09_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SJC_MOD_OFFSET (IOMUXC_SW_MUX_CTL_PAD_JTAG_MOD_SJC_MOD_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SJC_TMS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_JTAG_TMS_SJC_TMS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SJC_TDO_OFFSET (IOMUXC_SW_MUX_CTL_PAD_JTAG_TDO_SJC_TDO_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SJC_TDI_OFFSET (IOMUXC_SW_MUX_CTL_PAD_JTAG_TDI_SJC_TDI_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SJC_TCK_OFFSET (IOMUXC_SW_MUX_CTL_PAD_JTAG_TCK_SJC_TCK_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SJC_TRSTB_OFFSET (IOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B_SJC_TRSTB_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_I2C2_SCL_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_I2C2_SCL_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_I2C2_SDA_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_I2C2_SDA_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_I2C1_SCL_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_I2C1_SCL_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_I2C1_SDA_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_I2C1_SDA_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_ENET1_REF_CLK1_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_ENET1_REF_CLK1_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_ENET2_REF_CLK2_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_ENET2_REF_CLK2_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_ENET1_MDIO_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_ENET1_MDIO_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_ENET1_MDC_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_ENET1_MDC_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PWM1_OUT_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_PWM1_OUT_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PWM2_OUT_OFFSET (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_PWM2_OUT_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_UART1_DCE_TX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_UART1_DCE_TX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_UART1_DCE_RX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_UART1_DCE_RX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B_UART1_DCE_CTS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B_UART1_DCE_CTS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B_UART1_DCE_RTS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B_UART1_DCE_RTS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_UART2_DCE_TX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_UART2_DCE_TX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_UART2_DCE_RX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_UART2_DCE_RX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B_UART2_DCE_CTS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B_UART2_DCE_CTS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B_UART2_DCE_RTS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B_UART2_DCE_RTS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_UART3_DCE_TX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_UART3_DCE_TX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_UART3_DCE_RX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_UART3_DCE_RX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_UART3_DCE_CTS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_UART3_DCE_CTS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_UART3_DCE_RTS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_UART3_DCE_RTS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA_UART4_DCE_TX_OFFSET0 (IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA_UART4_DCE_TX_OFFSET0+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA_UART4_DCE_RX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA_UART4_DCE_RX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA_UART5_DCE_TX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA_UART5_DCE_TX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA_UART5_DCE_RX_OFFSET (IOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA_UART5_DCE_RX_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0_ENET1_RDATA00_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0_ENET1_RDATA00_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1_ENET1_RDATA01_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1_ENET1_RDATA01_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN_ENET1_RX_EN_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN_ENET1_RX_EN_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0_ENET1_TDATA00_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0_ENET1_TDATA00_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1_ENET1_TDATA01_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1_ENET1_TDATA01_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN_ENET1_TX_EN_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN_ENET1_TX_EN_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_ENET1_TX_CLK_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_ENET1_TX_CLK_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER_ENET1_RX_ER_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER_ENET1_RX_ER_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0_ENET2_RDATA00_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0_ENET2_RDATA00_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1_ENET2_RDATA01_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1_ENET2_RDATA01_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN_ENET2_RX_EN_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN_ENET2_RX_EN_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0_ENET2_TDATA00_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0_ENET2_TDATA00_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1_ENET2_TDATA01_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1_ENET2_TDATA01_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN_ENET2_TX_EN_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN_ENET2_TX_EN_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_ENET2_TX_CLK_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_ENET2_TX_CLK_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER_ENET2_RX_ER_OFFSET (IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER_ENET2_RX_ER_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_LCDIF_CLK_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_LCDIF_CLK_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_LCDIF_ENABLE_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_LCDIF_ENABLE_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_LCDIF_HSYNC_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_LCDIF_HSYNC_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_LCDIF_VSYNC_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_LCDIF_VSYNC_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_LCDIF_RESET_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_LCDIF_RESET_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_LCDIF_DATA00_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_LCDIF_DATA00_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_LCDIF_DATA01_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_LCDIF_DATA01_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_LCDIF_DATA02_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_LCDIF_DATA02_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_LCDIF_DATA03_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_LCDIF_DATA03_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_LCDIF_DATA04_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_LCDIF_DATA04_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_LCDIF_DATA05_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_LCDIF_DATA05_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_LCDIF_DATA06_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_LCDIF_DATA06_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_LCDIF_DATA07_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_LCDIF_DATA07_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_LCDIF_DATA08_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_LCDIF_DATA08_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_LCDIF_DATA09_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_LCDIF_DATA09_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_LCDIF_DATA10_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_LCDIF_DATA10_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_LCDIF_DATA11_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_LCDIF_DATA11_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_LCDIF_DATA12_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_LCDIF_DATA12_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_LCDIF_DATA13_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_LCDIF_DATA13_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_LCDIF_DATA14_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_LCDIF_DATA14 _OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_LCDIF_DATA15_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_LCDIF_DATA15_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_LCDIF_DATA16_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_LCDIF_DATA16_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_LCDIF_DATA17_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_LCDIF_DATA17_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_LCDIF_DATA18_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_LCDIF_DATA18_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_LCDIF_DATA19_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_LCDIF_DATA19_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_LCDIF_DATA20_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_LCDIF_DATA20_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_LCDIF_DATA21_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_LCDIF_DATA21_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_LCDIF_DATA22_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_LCDIF_DATA22_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_LCDIF_DATA23_OFFSET (IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_LCDIF_DATA23_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_RAWNAND_RE_B_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_RAWNAND_RE_B_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_RAWNAND_WE_B_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_RAWNAND_WE_B_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_RAWNAND_DATA00_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_RAWNAND_DATA00_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_RAWNAND_DATA01_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_RAWNAND_DATA01_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_RAWNAND_DATA02_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_RAWNAND_DATA02_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_RAWNAND_DATA03_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_RAWNAND_DATA03_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_RAWNAND_DATA04_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_RAWNAND_DATA04_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_RAWNAND_DATA05_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_RAWNAND_DATA05_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_RAWNAND_DATA06_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_RAWNAND_DATA06_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_RAWNAND_DATA07_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_RAWNAND_DATA07_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_RAWNAND_ALE_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_RAWNAND_ALE_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_RAWNAND_WP_B_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_RAWNAND_WP_B_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_RAWNAND_READY_B_OFFSET+ IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_RAWNAND_CE0_B_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_RAWNAND_CE1_B_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_RAWNAND_CE1_B_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_RAWNAND_CLE_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_RAWNAND_CLE_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DQS_RAWNAND_DQS_OFFSET (IOMUXC_SW_MUX_CTL_PAD_NAND_DQS_RAWNAND_DQS_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_USDHC1_CMD_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_USDHC1_CMD_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_USDHC1_CLK_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_USDHC1_CLK_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_USDHC1_DATA0_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_USDHC1_DATA0_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_USDHC1_DATA1_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_USDHC1_DATA1_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_USDHC1_DATA2_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_USDHC1_DATA2_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_USDHC1_DATA3_OFFSET (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_USDHC1_DATA3_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_CSI_MCLK_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_CSI_MCLK_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_CSI_PIXCLK_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_CSI_VSYNC_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_CSI_VSYNC_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_CSI_DATA02_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_CSI_DATA02_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_CSI_DATA03_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_CSI_DATA03_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_CSI_DATA04_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_CSI_DATA04_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_CSI_DATA05_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_CSI_DATA05_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_CSI_DATA06_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_CSI_DATA06_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_CSI_DATA07_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_CSI_DATA07_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_CSI_DATA08_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_CSI_DATA08_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_CSI_DATA09_OFFSET (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_CSI_DATA09_OFFSET + IOMUXC_SW_PAD_CTRL_BASE_OFFSET)
#define IOMUXC_SW_PAD_CTL_PAD_GRP_ADDDS_OFFSET 0x0490
#define IOMUXC_SW_PAD_CTL_PAD_GRP_DDRMODE_CTL_OFFSET 0x0494
#define IOMUXC_SW_PAD_CTL_PAD_GRP_B0DS_OFFSET 0x0498
#define IOMUXC_SW_PAD_CTL_PAD_GRP_CTLDS_OFFSET 0x04A0
#define IOMUXC_SW_PAD_CTL_PAD_CTL_GRP_B1DS_OFFSET 0x04A4
#define IOMUXC_SW_PAD_CTL_PAD_GRP_DDRPKE_OFFSET 0x04AC
#define IOMUXC_SW_PAD_CTL_PAD_GRP_DDRMODE_OFFSET 0x04B0
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT BIT(17)
#define IOMUXC_SW_PAD_CTL_PAD_GRP_DDR_TYPE_OFFSET 0x04B4
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_2_LPDDR2_MODE BIT(19)
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_3_DDR3_MODE BIT(19) | BIT(18)
/* These bits are constant for each pad control register */
#define IOMUXC_SW_PAD_CTL_PAD_HYS BIT(16)
#define IOMUXC_SW_PAD_CTL_PAD_PUS_3_22K_OHM_PULL_UP BIT(16) | BIT(15)
#define IOMUXC_SW_PAD_CTL_PADPUS_2_100K_OHM_PULL_UP BIT(15)
#define IOMUXC_SW_PAD_CTL_PAD_PUS_1_47K_OHM_PULL_UP BIT(14)
#define IOMUXC_SW_PAD_CTL_PAD_PUS_0_100K_OHM_PULL_DOWN 0
#define IOMUXC_SW_PAD_CTL_PAD_PUE_1_PULL BIT(13)
#define IOMUXC_SW_PAD_CTL_PAD_PUE_0_KEEPER 0
#define IOMUXC_SW_PAD_CTL_PAD_PKE_1_PULL_KEEPER_ENABLED BIT(12)
#define IOMUXC_SW_PAD_CTL_PAD_PKE_0_PULL_KEEPER_DISABLED 0
#define IOMUXC_SW_PAD_CTL_PAD_ODE_1_OPEN_DRAIN_ENABLED BIT(11)
#define IOMUXC_SW_PAD_CTL_PAD_ODE_0_OPEN_DRAIN_DISABLED 0
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_3_MAX_200MHZ BIT(7) | BIT(6)
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_2_MEDIUM_100MHZ BIT(7)
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_1_MEDIUM_100MHZ BIT(6)
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_0_LOW_50MHZ 0
#define IOMUXC_SW_PAD_CTL_PAD_DSE_7_R0_7 BIT(5) | BIT(4) | BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_6_R0_6 BIT(5) | BIT(4)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_5_R0_5 BIT(5) | BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_4_R0_4 BIT(5)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_3_R0_3 BIT(4) | BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_2_R0_2 BIT(4)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_1_R0_260_OHM___3_3V BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_1_R0_150_OHM___1_8V BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_1_R0_240_OHM___DDR BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_0_OUTPUT_DRIVER_DISABLED 0
#define IOMUXC_SW_PAD_CTL_PAD_SRE_1_FAST_SLEW_RATE BIT(0)
#define IOMUXC_SW_PAD_CTL_PAD_SRE_0_SLOW_SLEW_RATE 0
/*
* The above offsets are again possible to use to identify the relevant DAISY
* or direction register for a given PAD
*/
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x064C
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_CSI_MCLK_ALT8 0x00
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_ENET2_RX_DATA0_ALT1 0x01
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_ENET2_RX_DATA1_ALT1 0x02
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_CSI_PIXCLK_ALT8 0x03
#define IOMUXC_USDHC1_CD_B_SELECT_INPUT_OFFSET 0x668
#define IOMUXC_USDHC1_CD_B_SELECT_INPUT_GPIO1_IO03_ALT4 0
#define IOMUXC_USDHC1_CD_B_SELECT_INPUT_UART1_RTS_B_ALT2 BIT(0)
#define IOMUXC_USDHC1_CD_B_SELECT_INPUT_CSI_DATA05_ALT8 BIT(1)
#define IOMUXC_USDHC1_WP_SELECT_INPUT_OFFSET 0x66C
#define IOMUXC_USDHC1_WP_SELECT_INPUT_GPIO1_IO02_ALT4 0
#define IOMUXC_USDHC1_WP_SELECT_INPUT_UART1_CTS_B_ALT2 BIT(0)
#define IOMUXC_USDHC1_WP_SELECT_INPUT_CSI_DATA04_ALT8 BIT(1)
/* Pad mux/feature set routines */
void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function);
void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features);
void imx_io_muxc_set_pad_select_input(uint32_t pad_select_offset, uint32_t pad_select_input);
#endif /* IMX_IO_MUX_H */
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