diff options
| author | Andy Green <andy.green@linaro.org> | 2015-06-17 18:21:28 +0800 |
|---|---|---|
| committer | Guodong Xu <guodong.xu@linaro.org> | 2015-09-08 20:35:11 +0800 |
| commit | 40115b11e1f6a7d9754810b56b33feae973292e2 (patch) | |
| tree | f441a7c42ddaf105e43e9b63d38f949ffdec8fe5 | |
| parent | 8c097df62533c9cb2aa165e960bcd466366b422c (diff) | |
clk 1.2GHz actually 1.1904MHz
Signed-off-by: Andy Green <andy.green@linaro.org>
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi6220.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 10424eb02024..1e8f6b049bf6 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -35,9 +35,9 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = { { HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 245760000, }, { HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 1000000000,}, { HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 1066000000,}, - { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 1200000000,}, - { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 1200000000,}, - { HI6220_DDR_SRC, "ddr_sel_src", NULL, CLK_IS_ROOT, 1200000000,}, + { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 1190400000,}, + { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 1190400000,}, + { HI6220_DDR_SRC, "ddr_sel_src", NULL, CLK_IS_ROOT, 1190400000,}, { HI6220_PLL_MEDIA, "media_pll", NULL, CLK_IS_ROOT, 1440000000,}, { HI6220_PLL_DDR, "ddrpll0", NULL, CLK_IS_ROOT, 1600000000,}, }; |