diff options
| author | Leo Yan <leo.yan@linaro.org> | 2015-05-22 11:32:25 +0800 |
|---|---|---|
| committer | Leo Yan <leo.yan@linaro.org> | 2015-05-22 11:32:25 +0800 |
| commit | a4257cbcd14da5e571708adf9df9aa20e0b180c9 (patch) | |
| tree | fffc2d8270b4f052e861366eed3588b826482065 /arch | |
| parent | 46667d12db3f571fd7d01fa581e747165d98e648 (diff) | |
dts: hikey: configure pinctrl for uart3/4
The old dts have no configuration for uart3/4, so add related support
for these two uart ports.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/hi6220-hikey.dts | 12 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/hikey-pinctrl.dtsi | 59 |
2 files changed, 71 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hi6220-hikey.dts b/arch/arm64/boot/dts/hi6220-hikey.dts index 812aef7744b4..bc6a6957db19 100644 --- a/arch/arm64/boot/dts/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hi6220-hikey.dts @@ -58,6 +58,18 @@ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; status = "ok"; }; + + uart3: uart@f7113000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "ok"; + }; + + uart4: uart@f7114000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "ok"; + }; }; dwmmc_0: dwmmc0@f723d000 { diff --git a/arch/arm64/boot/dts/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hikey-pinctrl.dtsi index 4242b1a97018..68332362b6cf 100644 --- a/arch/arm64/boot/dts/hikey-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hikey-pinctrl.dtsi @@ -176,6 +176,31 @@ >; }; + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ + 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ + 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ + 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ + >; + }; + + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ + 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ + 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ + 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ + >; + }; + + uart5_pmx_func: uart5_pmx_func { + pinctrl-single,pins = < + 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ + 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ + >; + }; + i2c0_pmx_func: i2c0_pmx_func { pinctrl-single,pins = < 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ @@ -537,6 +562,40 @@ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; }; + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ + 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ + 0x198 0x0 /* UART3_RXD (IOCFG102) */ + 0x19c 0x0 /* UART3_TXD (IOCFG103) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ + 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ + 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ + 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ + 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ + >; + pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; + pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; + pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; + }; + i2c0_cfg_func: i2c0_cfg_func { pinctrl-single,pins = < 0xec 0x0 /* I2C0_SCL (IOCFG059) */ |