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authorJorge A. Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>2015-07-31 12:04:22 -0400
committerJorge A. Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>2015-07-31 12:04:22 -0400
commit5b0ad61e4517482b425402558b03089f6edd8d0a (patch)
tree83490a1f85c9fda4105f26a4c74a540fcca769e3 /drivers
parent9212a5290edb67d5d0f0b235980f3ead171d1703 (diff)
Revert "Working syspll get from registers v3"
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/hisilicon/clk-hi6220.c43
-rw-r--r--drivers/gpu/drm/Kconfig11
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c79
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c10
-rw-r--r--drivers/gpu/drm/drm_probe_helper.c21
-rw-r--r--drivers/gpu/drm/hisilicon/Kconfig1
-rw-r--r--drivers/gpu/drm/hisilicon/hisi_drm_ade.c126
-rw-r--r--drivers/gpu/drm/hisilicon/hisi_drm_dsi.c685
-rw-r--r--drivers/gpu/drm/hisilicon/hisi_ldi_reg.h94
-rw-r--r--drivers/gpu/drm/i2c/Kconfig48
-rw-r--r--drivers/gpu/drm/i2c/Makefile2
-rw-r--r--drivers/gpu/drm/i2c/adv7511.c1561
-rw-r--r--drivers/gpu/drm/i2c/adv7511.h350
-rw-r--r--drivers/gpu/drm/i2c/adv7533.c734
-rw-r--r--drivers/gpu/drm/i2c/adv7533.h223
-rw-r--r--drivers/tty/sysrq.c14
16 files changed, 1421 insertions, 2581 deletions
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index c1e243273fcc..4ea7e975f2b2 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -10,15 +10,15 @@
* published by the Free Software Foundation.
*/
-#include <linux/clk.h>
+#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/io.h>
-#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
+#include <linux/clk.h>
#include <dt-bindings/clock/hi6220-clock.h>
@@ -35,9 +35,9 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
{ HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 245760000, },
{ HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 1000000000,},
{ HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 1066000000,},
- { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 1190494208,},
- { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 1190494208,},
- { HI6220_DDR_SRC, "ddr_sel_src", NULL, CLK_IS_ROOT, 1190494208,},
+ { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 1200000000,},
+ { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 1200000000,},
+ { HI6220_DDR_SRC, "ddr_sel_src", NULL, CLK_IS_ROOT, 1200000000,},
{ HI6220_PLL_MEDIA, "media_pll", NULL, CLK_IS_ROOT, 1440000000,},
{ HI6220_PLL_DDR, "ddrpll0", NULL, CLK_IS_ROOT, 1600000000,},
};
@@ -73,47 +73,14 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
{ HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
};
-#define SOC_PERI_SCTRL_BASE_ADDR 0xF7030000 /* peri ctrl base addr */
-#define SC_PERIPH_CTRL14 0x02C
-#define SC_PERIPH_STAT1 0x094
-
static struct hisi_clock_data *clk_data_ao;
static void __init hi6220_clk_ao_init(struct device_node *np)
{
- void __iomem *peri_base;
- unsigned int syspll_freq;
- int i;
-
clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS);
if (!clk_data_ao)
return;
- /* SYSPLL is set by bootloader. Read it */
- peri_base = ioremap(SOC_PERI_SCTRL_BASE_ADDR, 0x1000);
- /* 0x2101 means to calculate clk_sys_pll */
- writel(0x2101, peri_base + SC_PERIPH_CTRL14);
- /* read back the calculated value */
- syspll_freq = readl(peri_base + SC_PERIPH_STAT1);
- pr_info("SYSPLL: syspll_freq is read: 0x%x, %d\n", syspll_freq, \
- syspll_freq);
- if (syspll_freq == 0x00020000 || syspll_freq == 0)
- syspll_freq = 1200000000;
- pr_info("SYSPLL: set syspll medpll ddrsrc: %d\n", syspll_freq);
-
- for (i = 0; i < ARRAY_SIZE(hi6220_fixed_rate_clks); i++) {
- switch (hi6220_fixed_rate_clks[i].id) {
- case HI6220_PLL_SYS:
- case HI6220_PLL_SYS_MEDIA:
- case HI6220_DDR_SRC:
- hi6220_fixed_rate_clks[i].fixed_rate = syspll_freq;
- pr_info("SYSPLL: modified fix_rate[%d], id=%d, f=%d\n", \
- i, hi6220_fixed_rate_clks[i].id, syspll_freq);
- default:
- break;
- }
- }
-
hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks,
ARRAY_SIZE(hi6220_fixed_rate_clks),
clk_data_ao);
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index e61d99b7409b..3d7a045536a2 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -80,17 +80,6 @@ source "drivers/gpu/drm/i2c/Kconfig"
source "drivers/gpu/drm/bridge/Kconfig"
-config DRM_SYSRQ_MODE_HACK
- bool "Allow SysRq-g to cycle through modes (1 crtc only)"
- depends on DRM
- help
- Select this option if your mode / timing generation is not so
- reliable that you can always show the preferred mode on any
- monitor and there are no arrangements on the platform to change
- it by hand. You can use AltGr-Sysrq-g to cycle between the
- available modes when this is enabled. It only understands one
- CRTC.
-
config DRM_TDFX
tristate "3dfx Banshee/Voodoo3+"
depends on DRM && PCI
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 164dfb34799e..6c65a0a28fbd 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -221,82 +221,6 @@ drm_crtc_prepare_encoders(struct drm_device *dev)
}
}
-#ifdef CONFIG_DRM_SYSRQ_MODE_HACK
-static struct drm_mode_set modehack_set;
-static void modehack_handler(struct work_struct *work)
-{
- struct drm_connector *connector = NULL, *connector1;
- struct drm_display_mode *mode1, *mode_first = NULL, *mode2 = NULL;
- bool next = false;
- char *envp[2];
-
- if (!modehack_set.crtc)
- return;
-
- drm_modeset_lock_all(modehack_set.crtc->dev);
-
- /* find our connector */
- list_for_each_entry(connector1,
- &modehack_set.crtc->dev->mode_config.connector_list,
- head) {
- if (!connector)
- connector = connector1;
- }
- if (!connector) {
- pr_err("no connector\n");
- goto bail;
- }
-
- /* identify our current mode and the "next" */
- list_for_each_entry(mode1, &connector->modes, head) {
- if (!mode_first)
- mode_first = mode1;
- if (next) {
- next = false;
- mode2 = mode1;
- }
- next = drm_mode_equal(&modehack_set.crtc->mode, mode1);
- }
-
- /* if next never appeared, loop back to first one */
- if (!mode2)
- mode2 = mode_first;
-
- pr_err("Trying %dx%d@%d, %dkHz\n", mode2->hdisplay, mode2->vdisplay,
- ((mode2->clock * 1000) / (mode2->htotal * mode2->vtotal)),
- mode2->clock);
-
- modehack_set.mode = mode2;
- modehack_set.connectors = &connector;
- modehack_set.num_connectors = 1;
-
- drm_helper_connector_dpms(connector, DRM_MODE_DPMS_STANDBY);
- drm_crtc_helper_set_config(&modehack_set);
- drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-
- envp[0] = "SOURCE=hotkey";
- envp[1] = NULL;
- kobject_uevent_env(&connector->kdev->kobj, KOBJ_CHANGE, envp);
-
-bail:
- drm_modeset_unlock_all(modehack_set.crtc->dev);
-}
-
-static DECLARE_WORK(modehack_work, modehack_handler);
-
-/*
- * Alt-Gr SYSRQ g magically calls this
- */
-void sysrq_handle_modehack(int key)
-{
- if (!modehack_set.crtc)
- return;
-
- schedule_work(&modehack_work);
-}
-EXPORT_SYMBOL_GPL(sysrq_handle_modehack);
-#endif
-
/**
* drm_crtc_helper_set_mode - internal helper to set a mode
* @crtc: CRTC to program
@@ -344,9 +268,6 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
return false;
}
- modehack_set.fb = crtc->primary->fb;
- modehack_set.crtc = crtc;
-
saved_mode = crtc->mode;
saved_x = crtc->x;
saved_y = crtc->y;
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 767adfcb8a37..0c0c39bac23d 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1262,16 +1262,6 @@ struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_connector *f
}
create_mode:
- /*
- * Synthetic mode timing is very unlikely to work on HDMI. Instead
- * if there is a fallback mode, give up on trying to guess the forced
- * mode timing and just let the forced mode deal with it.
- */
- if (fb_helper_conn->connector->funcs->fallback_mode) {
- pr_err("%s: preferring fallback mode\n", __func__);
- return NULL;
- }
-
mode = drm_mode_create_from_cmdline_mode(fb_helper_conn->connector->dev,
cmdline_mode);
list_add(&mode->head, &fb_helper_conn->connector->modes);
diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
index f240a689e92f..6857e9ad6339 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -155,15 +155,11 @@ static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect
count = (*connector_funcs->get_modes)(connector);
}
- if (count == 0 && connector->status == connector_status_connected &&
- !connector->funcs->fallback_mode)
+ if (count == 0 && connector->status == connector_status_connected)
count = drm_add_modes_noedid(connector, 1024, 768);
-
- if (count || !connector->funcs->fallback_mode) {
- count += drm_helper_probe_add_cmdline_mode(connector);
- if (count == 0)
- goto prune;
- }
+ count += drm_helper_probe_add_cmdline_mode(connector);
+ if (count == 0)
+ goto prune;
drm_mode_connector_list_update(connector, merge_type_bits);
@@ -187,13 +183,8 @@ static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect
prune:
drm_mode_prune_invalid(dev, &connector->modes, verbose_prune);
- if (list_empty(&connector->modes)) {
- if (!connector->funcs->fallback_mode)
- return 0;
- if (connector->funcs->fallback_mode(connector))
- return 0;
- count = 1;
- }
+ if (list_empty(&connector->modes))
+ return 0;
list_for_each_entry(mode, &connector->modes, head)
mode->vrefresh = drm_mode_vrefresh(mode);
diff --git a/drivers/gpu/drm/hisilicon/Kconfig b/drivers/gpu/drm/hisilicon/Kconfig
index 35362ef89f46..d4d42c9bffd7 100644
--- a/drivers/gpu/drm/hisilicon/Kconfig
+++ b/drivers/gpu/drm/hisilicon/Kconfig
@@ -5,7 +5,6 @@ config DRM_HISI
select DRM_GEM_CMA_HELPER
select DRM_PANEL
select DRM_MIPI_DSI
- select DRM_SYSRQ_MODE_HACK
help
Choose this option if you have a hisilicon terminal chipset.
If M is selected the module will be called hisi-drm.
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
index 22e5b66ef7bf..98b0b128471a 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_ade.c
@@ -25,7 +25,6 @@
#include "hisi_ldi_reg.h"
#include "hisi_drm_ade.h"
-#define FORCE_PIXEL_CLOCK_SAME_OR_HIGHER 0
#define SC_MEDIA_RSTDIS (0x530)
#define SC_MEDIA_RSTEN (0x52C)
@@ -109,7 +108,6 @@ struct hisi_drm_ade_crtc {
struct clk *ade_core_clk;
struct clk *media_noc_clk;
struct clk *ade_pix_clk;
- bool power_on;
};
@@ -177,7 +175,6 @@ static int ade_power_up(struct hisi_drm_ade_crtc *crtc_ade)
DRM_ERROR("fail to clk_prepare_enable ade_core_clk\n");
return ret;
}
- crtc_ade->power_on = true;
return 0;
}
@@ -188,7 +185,6 @@ static int ade_power_down(struct hisi_drm_ade_crtc *crtc_ade)
clk_disable_unprepare(crtc_ade->ade_core_clk);
writel(0x20, media_base + SC_MEDIA_RSTEN);
clk_disable_unprepare(crtc_ade->media_noc_clk);
- crtc_ade->power_on = false;
return 0;
}
@@ -196,12 +192,10 @@ static int hisi_drm_crtc_ade_enable(struct hisi_drm_ade_crtc *crtc_ade)
{
int ret;
- if (!crtc_ade->power_on) {
- ret = ade_power_up(crtc_ade);
- if (ret) {
+ ret = ade_power_up(crtc_ade);
+ if (ret) {
DRM_ERROR("failed to initialize ade clk\n");
return ret;
- }
}
ade_init(crtc_ade);
@@ -230,54 +224,54 @@ static int hisi_drm_crtc_ade_disable(struct hisi_drm_ade_crtc *crtc_ade)
static void ldi_init(struct hisi_drm_ade_crtc *crtc_ade)
{
- struct drm_display_mode *mode = crtc_ade->dmode;
- void __iomem *ade_base = crtc_ade->ade_base;
- u32 hfp, hbp, hsw, vfp, vbp, vsw;
+ int ret;
+ u32 hfront_porch, hback_porch, hsync_len;
+ u32 vfront_porch, vback_porch, vsync_len;
u32 plr_flags;
u32 ldi_mask;
+ struct drm_display_mode *mode = crtc_ade->dmode;
+ u8 __iomem *ade_base = crtc_ade->ade_base;
+ /*
+ * Timing setting
+ */
plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC)
? HISI_LDI_FLAG_NVSYNC : 0;
plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC)
? HISI_LDI_FLAG_NHSYNC : 0;
- hfp = mode->hsync_start - mode->hdisplay;
- hbp = mode->htotal - mode->hsync_end;
- hsw = mode->hsync_end - mode->hsync_start;
- vfp = mode->vsync_start - mode->vdisplay;
- vbp = mode->vtotal - mode->vsync_end;
- vsw = mode->vsync_end - mode->vsync_start;
- if (vsw > 15) {
- pr_err("%s: vsw exceeded 15\n", __func__);
- vsw = 15;
- }
-
- writel((hbp << 20) | (hfp << 0), ade_base + LDI_HRZ_CTRL0_REG);
- /* p3-73 6220V100 pdf:
- * "The configured value is the actual width - 1"
- */
- writel(hsw - 1, ade_base + LDI_HRZ_CTRL1_REG);
- writel((vbp << 20) | (vfp << 0), ade_base + LDI_VRT_CTRL0_REG);
- /* p3-74 6220V100 pdf:
- * "The configured value is the actual width - 1"
- */
- writel(vsw - 1, ade_base + LDI_VRT_CTRL1_REG);
-
- /* p3-75 6220V100 pdf:
- * "The configured value is the actual width - 1"
- */
- writel(((mode->vdisplay - 1) << 20) | ((mode->hdisplay - 1) << 0),
- ade_base + LDI_DSP_SIZE_REG);
+ hfront_porch = mode->hsync_start - mode->hdisplay;
+ hback_porch = mode->htotal - mode->hsync_end;
+ hsync_len = mode->hsync_end - mode->hsync_start;
+ vfront_porch = mode->vsync_start - mode->vdisplay;
+ vback_porch = mode->vtotal - mode->vsync_end;
+ vsync_len = mode->vsync_end - mode->vsync_start;
+ if (vsync_len > 15)
+ vsync_len = 15;
+
+ set_LDI_HRZ_CTRL0(ade_base, hfront_porch, hback_porch);
+ set_LDI_HRZ_CTRL1_hsw(ade_base, hsync_len);
+ set_LDI_VRT_CTRL0(ade_base, vfront_porch, vback_porch);
+ set_LDI_VRT_CTRL1_vsw(ade_base, vsync_len);
writel(plr_flags, ade_base + LDI_PLR_CTRL_REG);
+ set_LDI_DSP_SIZE_size(ade_base, mode->hdisplay, mode->vdisplay);
+ ret = clk_set_rate(crtc_ade->ade_pix_clk, mode->clock * 1000);
+ if (ret) {
+ DRM_ERROR("set ade_pixel_clk_rate fail\n");
+ return;
+ }
/*
* other parameters setting
*/
- writel(BIT(0), ade_base + LDI_WORK_MODE_REG);
+ set_LDI_WORK_MODE_work_mode(ade_base, LDI_WORK);
+ set_LDI_WORK_MODE_colorbar_en(ade_base, ADE_DISABLE);
ldi_mask = LDI_ISR_FRAME_END_INT | LDI_ISR_UNDER_FLOW_INT;
writel(ldi_mask, ade_base + LDI_INT_EN_REG);
- writel((0x3c << 6) | (ADE_OUT_RGB_888 << 3) | BIT(2) | BIT(0),
- ade_base + LDI_CTRL_REG);
+ set_LDI_CTRL_bgr(ade_base, ADE_RGB);
+ set_LDI_CTRL_bpp(ade_base, ADE_OUT_RGB_888);
+ set_LDI_CTRL_disp_mode(ade_base, LDI_DISP_MODE_NOT_3D_FBF);
+ set_LDI_CTRL_corlorbar_width(ade_base, 0x3C);
writel(0xFFFFFFFF, ade_base + LDI_INT_CLR_REG);
set_reg(ade_base + LDI_DE_SPACE_LOW_REG, 0x1, 1, 1);
/* dsi pixel on */
@@ -310,38 +304,9 @@ static void hisi_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
static bool hisi_drm_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
+ struct drm_display_mode *adjusted_mode)
{
- struct hisi_drm_ade_crtc *crtc_ade = to_hisi_crtc(crtc);
- u32 clock_kHz = mode->clock;
- int ret;
-
DRM_DEBUG_DRIVER("mode_fixup enter successfully.\n");
-
- if (!crtc_ade->power_on)
- if (ade_power_up(crtc_ade))
- DRM_ERROR("%s: failed to power up ade\n", __func__);
-
- do {
- ret = clk_set_rate(crtc_ade->ade_pix_clk, clock_kHz * 1000);
- if (ret) {
- DRM_ERROR("set ade_pixel_clk_rate fail\n");
- return false;
- }
- adj_mode->clock = clk_get_rate(crtc_ade->ade_pix_clk) / 1000;
-#if FORCE_PIXEL_CLOCK_SAME_OR_HIGHER
- if (adj_mode->clock >= clock_kHz)
-#endif
- /* This avoids a bad 720p DSI clock with 1.2GHz DPI PLL */
- if (adj_mode->clock != 72000)
- break;
-
- clock_kHz += 10;
- } while (1);
-
- pr_info("%s: pixel clock: req %dkHz -> actual: %dkHz\n",
- __func__, mode->clock, adj_mode->clock);
-
DRM_DEBUG_DRIVER("mode_fixup exit successfully.\n");
return true;
}
@@ -386,7 +351,6 @@ static int hisi_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
u32 display_addr;
u32 offset;
u32 fb_hight;
- int bytes_pp = (fb->bits_per_pixel + 1) / 8;
ade_base = crtc_ade->ade_base;
stride = fb->pitches[0];
@@ -395,11 +359,9 @@ static int hisi_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
fb_hight = hisi_fb->is_fbdev_fb ? fb->height / HISI_NUM_FRAMEBUFFERS
: fb->height;
- DRM_DEBUG_DRIVER("enter: fb stride=%d, paddr=0x%x, display_addr=0x%x, "
- "fb=%dx%d, scanout=%dx%d\n",
- stride, (u32)obj->paddr, display_addr,
- fb->width, fb_hight, crtc->mode.hdisplay,
- crtc->mode.vdisplay);
+ DRM_DEBUG_DRIVER("enter stride=%d,paddr=0x%x,display_addr=0x%x,%dx%d\n",
+ stride, (u32)obj->paddr, display_addr,
+ fb->width, fb_hight);
/* TOP setting */
writel(0, ade_base + ADE_WDMA2_SRC_CFG_REG);
@@ -435,20 +397,19 @@ static int hisi_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
#endif /* CONFIG_ANDROID */
writel(display_addr, ade_base + RD_CH_DISP_ADDR_REG);
- writel((crtc->mode.vdisplay << 16) | crtc->mode.hdisplay * bytes_pp,
- ade_base + RD_CH_DISP_SIZE_REG);
+ writel((fb_hight << 16) | stride, ade_base + RD_CH_DISP_SIZE_REG);
writel(stride, ade_base + RD_CH_DISP_STRIDE_REG);
- writel(crtc->mode.vdisplay * stride, ade_base + RD_CH_DISP_SPACE_REG);
+ writel(fb_hight * stride, ade_base + RD_CH_DISP_SPACE_REG);
writel(1, ade_base + RD_CH_DISP_EN_REG);
/* ctran5 setting */
writel(1, ade_base + ADE_CTRAN5_DIS_REG);
- writel(crtc->mode.hdisplay * crtc->mode.vdisplay - 1,
+ writel(fb->width * fb_hight - 1,
ade_base + ADE_CTRAN5_IMAGE_SIZE_REG);
/* ctran6 setting */
writel(1, ade_base + ADE_CTRAN6_DIS_REG);
- writel(crtc->mode.hdisplay * crtc->mode.vdisplay - 1,
+ writel(fb->width * fb_hight - 1,
ade_base + ADE_CTRAN6_IMAGE_SIZE_REG);
/* enable ade and ldi */
@@ -505,7 +466,6 @@ static int hisi_drm_crtc_create(struct hisi_drm_ade_crtc *crtc_ade)
int ret;
crtc_ade->enable = false;
- crtc_ade->power_on = false;
ret = drm_crtc_init(crtc_ade->drm_dev, crtc, &crtc_funcs);
if (ret < 0)
return ret;
diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
index a44bc39dfd13..6741cd09eefe 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
@@ -41,10 +41,11 @@
#define DSI_BURST_MODE DSI_NON_BURST_SYNC_PULSES
#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
-#define DEFAULT_MIPI_CLK_PERIOD_PS (1000000000 / (DEFAULT_MIPI_CLK_RATE / 1000))
+#define USE_DEFAULT_720P_MODE 1
u8 *reg_base_mipi_dsi;
+
struct mipi_dsi_phy_register {
u32 clk_t_lpx;
u32 clk_t_hs_prepare;
@@ -76,7 +77,7 @@ struct mipi_dsi_phy_register {
u32 phy_hs2lp_time;
u32 clk_to_data_delay;
u32 data_to_clk_delay;
- u32 lane_byte_clk_kHz;
+ u32 lane_byte_clk;
u32 clk_division;
u32 burst_mode;
};
@@ -88,14 +89,13 @@ struct hisi_dsi {
struct drm_i2c_encoder_driver *drm_i2c_driver;
struct clk *dsi_cfg_clk;
struct videomode vm;
- int nominal_pixel_clock_kHz;
u8 __iomem *reg_base;
u8 color_mode;
u32 lanes;
u32 format;
- struct mipi_dsi_phy_register phyreg;
+ struct mipi_dsi_phy_register phy_register;
u32 date_enable_pol;
u32 vc;
u32 mode_flags;
@@ -115,8 +115,8 @@ enum {
};
struct dsi_phy_seq_info {
- u32 min_range_kHz;
- u32 max_range_kHz;
+ u32 min_range;
+ u32 max_range;
u32 rg_pll_vco_750M;
u32 rg_hstx_ckg_sel;
};
@@ -129,44 +129,16 @@ enum {
};
struct dsi_phy_seq_info dphy_seq_info[] = {
- { 46000, 62000, 1, 7 },
- { 62000, 93000, 0, 7 },
- { 93000, 125000, 1, 6 },
- { 125000, 187000, 0, 6 },
- { 187000, 250000, 1, 5 },
- { 250000, 375000, 0, 5 },
- { 375000, 500000, 1, 4 },
- { 500000, 750000, 0, 4 },
- { 750000, 1000000, 1, 0 },
- { 1000000, 1500000, 0, 0 }
-};
-
-/*
- * Canned 720p60 mode for use if no whitelisted modes
- * available (due to no EDID or EDID contains no whitelisted
- * mode)
- *
- * Detailed mode: Clock 74.250 MHz, 735 mm x 420 mm
- * 1280 1390 1430 1650 hborder 0
- * 720 725 730 750 vborder 0
- * +hsync +vsync
- */
-
-static struct drm_display_mode mode_720p_canned = {
- .name = "720p60",
- .type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER,
- .clock = 74250,
- .hdisplay = 1280,
- .hsync_start = 1390,
- .hsync_end = 1430,
- .htotal = 1650,
- .vdisplay = 720,
- .vsync_start = 725,
- .vsync_end = 730,
- .vtotal = 750,
- .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
- .width_mm = 735,
- .height_mm = 420,
+ {46, 62, 1, 7},
+ {62, 93, 0, 7},
+ {93, 125, 1, 6},
+ {125, 187, 0, 6},
+ {187, 250, 1, 5},
+ {250, 375, 0, 5},
+ {375, 500, 1, 4},
+ {500, 750, 0, 4},
+ {750, 1000, 1, 0},
+ {1000, 1500, 0, 0}
};
static inline void set_reg(u8 *addr, u32 val, u32 bw, u32 bs)
@@ -184,168 +156,168 @@ static inline struct drm_encoder_slave_funcs *
return to_encoder_slave(enc)->slave_funcs;
}
-void set_dsi_phy_rate_equal_or_faster(u32 *phy_freq_kHz,
- struct mipi_dsi_phy_register *phyreg)
+void get_dsi_phy_register(u32 *phy_freq,
+ struct mipi_dsi_phy_register *phy_register)
{
u32 ui = 0;
- u32 cfg_clk_ps = DEFAULT_MIPI_CLK_PERIOD_PS;
+ u32 t_cfg_clk = 0;
+ u32 seq_info_count = 0;
u32 i = 0;
- u32 q_pll = 1;
+ u32 q_pll = 0;
u32 m_pll = 0;
u32 n_pll = 0;
- u32 r_pll = 1;
+ u32 r_pll = 0;
u32 m_n = 0;
u32 m_n_int = 0;
- u64 f_kHz;
- u64 temp;
-
- DRM_DEBUG_DRIVER("enter (phy_freq_kHz = %u)\n", *phy_freq_kHz);
- BUG_ON(phyreg == NULL);
- do {
- f_kHz = *phy_freq_kHz;
-
- /* Find the PLL clock range from the table */
-
- for (i = 0; i < ARRAY_SIZE(dphy_seq_info); i++)
- if (f_kHz > dphy_seq_info[i].min_range_kHz &&
- f_kHz <= dphy_seq_info[i].max_range_kHz)
- break;
-
- if (i == ARRAY_SIZE(dphy_seq_info)) {
- pr_err("%s: %lldkHz out of range\n", __func__, f_kHz);
- return;
+ DRM_DEBUG_DRIVER("enter.\n");
+ BUG_ON(phy_freq == NULL);
+ BUG_ON(phy_register == NULL);
+
+ t_cfg_clk = 1000 / (DEFAULT_MIPI_CLK_RATE / 1000000);
+
+ /* PLL parameters calculation */
+ seq_info_count = sizeof(dphy_seq_info) / sizeof(struct dsi_phy_seq_info);
+ for (i = 0; i < seq_info_count; i++) {
+ if (*phy_freq > dphy_seq_info[i].min_range
+ && *phy_freq <= dphy_seq_info[i].max_range) {
+ phy_register->rg_pll_vco_750M = dphy_seq_info[i].rg_pll_vco_750M;
+ phy_register->rg_hstx_ckg_sel = dphy_seq_info[i].rg_hstx_ckg_sel;
+ break;
}
+ }
- phyreg->rg_pll_vco_750M = dphy_seq_info[i].rg_pll_vco_750M;
- phyreg->rg_hstx_ckg_sel = dphy_seq_info[i].rg_hstx_ckg_sel;
-
- if (phyreg->rg_hstx_ckg_sel <= 7 &&
- phyreg->rg_hstx_ckg_sel >= 4)
- q_pll = 0x10 >> (7 - phyreg->rg_hstx_ckg_sel);
-
- temp = f_kHz * (u64)q_pll * (u64)cfg_clk_ps;
- m_n_int = temp / (u64)1000000000;
- m_n = (temp % (u64)1000000000) / (u64)100000000;
-
- pr_debug("%s: m_n_int = %d, m_n = %d\n",
- __func__, m_n_int, m_n);
-
- if (m_n_int % 2 == 0) {
- if (m_n * 6 >= 50) {
- n_pll = 2;
- m_pll = (m_n_int + 1) * n_pll;
- } else if (m_n * 6 >= 30) {
- n_pll = 3;
- m_pll = m_n_int * n_pll + 2;
- } else {
- n_pll = 1;
- m_pll = m_n_int * n_pll;
- }
- } else {
- if (m_n * 6 >= 50) {
- n_pll = 1;
- m_pll = (m_n_int + 1) * n_pll;
- } else if (m_n * 6 >= 30) {
- n_pll = 1;
- m_pll = (m_n_int + 1) * n_pll;
- } else if (m_n * 6 >= 10) {
- n_pll = 3;
- m_pll = m_n_int * n_pll + 1;
- } else {
- n_pll = 2;
- m_pll = m_n_int * n_pll;
- }
- }
+ switch (phy_register->rg_hstx_ckg_sel) {
+ case 7:
+ q_pll = 16;
+ break;
+ case 6:
+ q_pll = 8;
+ break;
+ case 5:
+ q_pll = 4;
+ break;
+ case 4:
+ q_pll = 2;
+ break;
+ default:
+ q_pll = 1;
+ break;
+ }
- if (n_pll == 1) {
- phyreg->rg_pll_fbd_p = 0;
- phyreg->rg_pll_pre_div1p = 1;
+ m_n_int = (*phy_freq) * q_pll * t_cfg_clk / 1000;
+ m_n = (*phy_freq) * q_pll * t_cfg_clk % 1000 * 10 / 1000;
+ if (m_n_int % 2 == 0) {
+ if (m_n * 6 >= 50) {
+ n_pll = 2;
+ m_pll = (m_n_int + 1) * n_pll;
+ } else if (m_n * 6 >= 30) {
+ n_pll = 3;
+ m_pll = m_n_int * n_pll + 2;
} else {
- phyreg->rg_pll_fbd_p = n_pll;
- phyreg->rg_pll_pre_div1p = 0;
+ n_pll = 1;
+ m_pll = m_n_int * n_pll;
}
-
- if (phyreg->rg_pll_fbd_2p <= 7 && phyreg->rg_pll_fbd_2p >= 4)
- r_pll = 0x10 >> (7 - phyreg->rg_pll_fbd_2p);
-
- if (m_pll == 2) {
- phyreg->rg_pll_pre_p = 0;
- phyreg->rg_pll_fbd_s = 0;
- phyreg->rg_pll_fbd_div1f = 0;
- phyreg->rg_pll_fbd_div5f = 1;
- } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
- phyreg->rg_pll_pre_p = m_pll / (2 * r_pll);
- phyreg->rg_pll_fbd_s = 0;
- phyreg->rg_pll_fbd_div1f = 1;
- phyreg->rg_pll_fbd_div5f = 0;
- } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
- if (((m_pll / (2 * r_pll)) % 2) == 0) {
- phyreg->rg_pll_pre_p =
- (m_pll / (2 * r_pll)) / 2 - 1;
- phyreg->rg_pll_fbd_s =
- (m_pll / (2 * r_pll)) % 2 + 2;
- } else {
- phyreg->rg_pll_pre_p =
- (m_pll / (2 * r_pll)) / 2;
- phyreg->rg_pll_fbd_s =
- (m_pll / (2 * r_pll)) % 2;
- }
- phyreg->rg_pll_fbd_div1f = 0;
- phyreg->rg_pll_fbd_div5f = 0;
+ } else {
+ if (m_n * 6 >= 50) {
+ n_pll = 1;
+ m_pll = (m_n_int + 1) * n_pll;
+ } else if (m_n * 6 >= 30) {
+ n_pll = 1;
+ m_pll = (m_n_int + 1) * n_pll;
+ } else if (m_n * 6 >= 10) {
+ n_pll = 3;
+ m_pll = m_n_int * n_pll + 1;
} else {
- phyreg->rg_pll_pre_p = 0;
- phyreg->rg_pll_fbd_s = 0;
- phyreg->rg_pll_fbd_div1f = 0;
- phyreg->rg_pll_fbd_div5f = 1;
+ n_pll = 2;
+ m_pll = m_n_int * n_pll;
}
+ }
+
+ if (n_pll == 1) {
+ phy_register->rg_pll_fbd_p = 0;
+ phy_register->rg_pll_pre_div1p = 1;
+ } else {
+ phy_register->rg_pll_fbd_p = n_pll;
+ phy_register->rg_pll_pre_div1p = 0;
+ }
- f_kHz = (u64)1000000000 * (u64)m_pll /
- ((u64)cfg_clk_ps * (u64)n_pll * (u64)q_pll);
+ switch (phy_register->rg_pll_fbd_2p) {
+ case 7:
+ r_pll = 16;
+ break;
+ case 6:
+ r_pll = 8;
+ break;
+ case 5:
+ r_pll = 4;
+ break;
+ case 4:
+ r_pll = 2;
+ break;
+ default:
+ r_pll = 1;
+ break;
+ }
- if (f_kHz >= *phy_freq_kHz)
- break;
+ if (m_pll == 2) {
+ phy_register->rg_pll_pre_p = 0;
+ phy_register->rg_pll_fbd_s = 0;
+ phy_register->rg_pll_fbd_div1f = 0;
+ phy_register->rg_pll_fbd_div5f = 1;
+ } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
+ phy_register->rg_pll_pre_p = m_pll / (2 * r_pll);
+ phy_register->rg_pll_fbd_s = 0;
+ phy_register->rg_pll_fbd_div1f = 1;
+ phy_register->rg_pll_fbd_div5f = 0;
+ } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
+ if (((m_pll / (2 * r_pll)) % 2) == 0) {
+ phy_register->rg_pll_pre_p = (m_pll / (2 * r_pll)) / 2 - 1;
+ phy_register->rg_pll_fbd_s = (m_pll / (2 * r_pll)) % 2 + 2;
+ } else {
+ phy_register->rg_pll_pre_p = (m_pll / (2 * r_pll)) / 2;
+ phy_register->rg_pll_fbd_s = (m_pll / (2 * r_pll)) % 2;
+ }
+ phy_register->rg_pll_fbd_div1f = 0;
+ phy_register->rg_pll_fbd_div5f = 0;
+ } else {
+ phy_register->rg_pll_pre_p = 0;
+ phy_register->rg_pll_fbd_s = 0;
+ phy_register->rg_pll_fbd_div1f = 0;
+ phy_register->rg_pll_fbd_div5f = 1;
+ }
- (*phy_freq_kHz) += 10;
-
- } while (1);
-
- pr_info("%s: %dkHz -> %lldkHz\n", __func__, *phy_freq_kHz, f_kHz);
-
- *phy_freq_kHz = f_kHz;
- ui = 1000000 / f_kHz;
-
- phyreg->clk_t_lpx = ROUND(50, 8 * ui);
- phyreg->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
-
- phyreg->clk_t_hs_zero = ROUND(262, 8 * ui);
- phyreg->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
- phyreg->clk_t_wakeup = ROUND(1000000, (cfg_clk_ps / 1000) - 1);
- if (phyreg->clk_t_wakeup > 0xff)
- phyreg->clk_t_wakeup = 0xff;
- phyreg->data_t_wakeup = phyreg->clk_t_wakeup;
- phyreg->data_t_lpx = phyreg->clk_t_lpx;
- phyreg->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
- phyreg->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
- phyreg->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
- phyreg->data_t_ta_go = 3;
- phyreg->data_t_ta_get = 4;
-
- phyreg->rg_pll_enbwt = 1;
- phyreg->phy_clklp2hs_time = ROUND(407, 8 * ui) + 12;
- phyreg->phy_clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
- phyreg->phy_lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
- phyreg->phy_hs2lp_time = phyreg->phy_clkhs2lp_time;
- phyreg->clk_to_data_delay = 1 + phyreg->phy_clklp2hs_time;
- phyreg->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
- phyreg->phy_clkhs2lp_time;
-
- phyreg->lane_byte_clk_kHz = f_kHz / 8;
- phyreg->clk_division = phyreg->lane_byte_clk_kHz / MAX_TX_ESC_CLK;
- if (phyreg->lane_byte_clk_kHz % MAX_TX_ESC_CLK)
- phyreg->clk_division++;
-
- phyreg->burst_mode = DSI_BURST_MODE;
+ *phy_freq = 1000 * m_pll / (t_cfg_clk * n_pll * q_pll);
+ ui = 1000 / (*phy_freq);
+
+ phy_register->clk_t_lpx = ROUND(50, 8 * ui);
+ phy_register->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
+
+ phy_register->clk_t_hs_zero = ROUND(262, 8 * ui);
+ phy_register->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
+ phy_register->clk_t_wakeup = ROUND(1000000, t_cfg_clk - 1) > 0xFF ? 0xFF : ROUND(1000000, t_cfg_clk - 1);
+ phy_register->data_t_wakeup = phy_register->clk_t_wakeup;
+ phy_register->data_t_lpx = phy_register->clk_t_lpx;
+ phy_register->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
+ phy_register->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
+ phy_register->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
+ phy_register->data_t_ta_go = 3;
+ phy_register->data_t_ta_get = 4;
+
+ phy_register->rg_pll_enbwt = 1;
+ phy_register->phy_clklp2hs_time = ROUND(407, 8 * ui) + 12;
+ phy_register->phy_clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
+ phy_register->phy_lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
+ phy_register->phy_hs2lp_time = phy_register->phy_clkhs2lp_time;
+ phy_register->clk_to_data_delay = 1 + phy_register->phy_clklp2hs_time;
+ phy_register->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) + phy_register->phy_clkhs2lp_time;
+
+ phy_register->lane_byte_clk = *phy_freq / 8;
+ phy_register->clk_division = ((phy_register->lane_byte_clk % MAX_TX_ESC_CLK) > 0) ?
+ (phy_register->lane_byte_clk / MAX_TX_ESC_CLK + 1) :
+ (phy_register->lane_byte_clk / MAX_TX_ESC_CLK);
+
+ phy_register->burst_mode = DSI_BURST_MODE;
DRM_DEBUG_DRIVER("exit success.\n");
}
@@ -355,21 +327,18 @@ int mipi_init(struct hisi_dsi *dsi)
u32 hline_time = 0;
u32 hsa_time = 0;
u32 hbp_time = 0;
- u32 pixel_clk_kHz;
+ u32 pixel_clk = 0;
u32 i = 0;
bool is_ready = false;
u32 delay_count = 0;
- struct mipi_dsi_phy_register *phyreg = &dsi->phyreg;
- int refresh_nom, refresh_real, htot, vtot, blc_hactive;
- int tmp, tmp1;
-
- pr_info("%s: lanes %d\n", __func__, dsi->lanes);
+ struct mipi_dsi_phy_register *phy_register = &dsi->phy_register;
+ DRM_DEBUG_DRIVER("enter.\n");
/* reset Core */
set_MIPIDSI_PWR_UP_shutdownz(0);
- set_MIPIDSI_PHY_IF_CFG_n_lanes(dsi->lanes - 1);
- set_MIPIDSI_CLKMGR_CFG_tx_esc_clk_division(phyreg->clk_division);
+ set_MIPIDSI_PHY_IF_CFG_n_lanes(dsi->lanes-1);
+ set_MIPIDSI_CLKMGR_CFG_tx_esc_clk_division(phy_register->clk_division);
set_MIPIDSI_PHY_RSTZ(0x00000000);
set_MIPIDSI_PHY_TST_CTRL0(0x00000000);
@@ -380,7 +349,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10010);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->clk_t_lpx);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->clk_t_lpx);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -388,7 +357,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10011);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->clk_t_hs_prepare);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->clk_t_hs_prepare);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -396,7 +365,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10012);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->clk_t_hs_zero);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->clk_t_hs_zero);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -404,7 +373,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10013);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->clk_t_hs_trial);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->clk_t_hs_trial);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -412,7 +381,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10014);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->clk_t_wakeup);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->clk_t_wakeup);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -422,7 +391,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10020 + (i << 4));
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->data_t_lpx);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->data_t_lpx);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -430,7 +399,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10021 + (i << 4));
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->data_t_hs_prepare);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->data_t_hs_prepare);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -438,7 +407,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10022 + (i << 4));
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->data_t_hs_zero);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->data_t_hs_zero);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -446,7 +415,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10023 + (i << 4));
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->data_t_hs_trial);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->data_t_hs_trial);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -454,7 +423,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10024 + (i << 4));
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->data_t_ta_go);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->data_t_ta_go);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -462,7 +431,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10025 + (i << 4));
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->data_t_ta_get);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->data_t_ta_get);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -470,7 +439,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10026 + (i << 4));
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->data_t_wakeup);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->data_t_wakeup);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
}
@@ -479,7 +448,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10060);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->rg_hstx_ckg_sel);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->rg_hstx_ckg_sel);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -487,9 +456,9 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10063);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1((phyreg->rg_pll_fbd_div5f << 5) +
- (phyreg->rg_pll_fbd_div1f << 4) + (phyreg->rg_pll_fbd_2p << 1) +
- phyreg->rg_pll_enbwt);
+ set_MIPIDSI_PHY_TST_CTRL1((phy_register->rg_pll_fbd_div5f << 5) +
+ (phy_register->rg_pll_fbd_div1f << 4) + (phy_register->rg_pll_fbd_2p << 1) +
+ phy_register->rg_pll_enbwt);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -497,7 +466,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10064);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1(phyreg->rg_pll_fbd_p);
+ set_MIPIDSI_PHY_TST_CTRL1(phy_register->rg_pll_fbd_p);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -505,7 +474,7 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10065);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1((1 << 4) + phyreg->rg_pll_fbd_s);
+ set_MIPIDSI_PHY_TST_CTRL1((1 << 4) + phy_register->rg_pll_fbd_s);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -513,8 +482,8 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10066);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1((phyreg->rg_pll_pre_div1p << 7) +
- phyreg->rg_pll_pre_p);
+ set_MIPIDSI_PHY_TST_CTRL1((phy_register->rg_pll_pre_div1p << 7) +
+ phy_register->rg_pll_pre_p);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -522,8 +491,8 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_PHY_TST_CTRL1(0x10067);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
- set_MIPIDSI_PHY_TST_CTRL1((5 << 5) + (phyreg->rg_pll_vco_750M << 4) +
- (phyreg->rg_pll_lpf_rs << 2) + phyreg->rg_pll_lpf_cs);
+ set_MIPIDSI_PHY_TST_CTRL1((5 << 5) + (phy_register->rg_pll_vco_750M << 4) +
+ (phy_register->rg_pll_lpf_rs << 2) + phy_register->rg_pll_lpf_cs);
set_MIPIDSI_PHY_TST_CTRL0(0x2);
set_MIPIDSI_PHY_TST_CTRL0(0x0);
@@ -564,62 +533,54 @@ int mipi_init(struct hisi_dsi *dsi)
if (!is_ready)
DRM_INFO("phystopstateclklane is not ready.\n");
+ /* --------------configuring the DPI packet transmission----------------
+ *
+ * 1. Global configuration
+ * Configure Register PHY_IF_CFG with the correct number of lanes
+ * to be used by the controller.
+ *
+ * 2. Configure the DPI Interface:
+ * This defines how the DPI interface interacts with the controller.
+ *
+ * 3. Configure the TX_ESC clock frequency to a frequency lower than 20 MHz
+ * that is the maximum allowed frequency for D-PHY ESCAPE mode.
+ *
+ */
set_MIPIDSI_DPI_VCID(dsi->vc);
set_MIPIDSI_DPI_COLOR_CODING_dpi_color_coding(dsi->color_mode);
- set_MIPIDSI_DPI_CFG_POL_hsync_active_low(
- dsi->vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 0 : 1);
+ set_MIPIDSI_DPI_CFG_POL_hsync_active_low(dsi->vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 0 : 1);
set_MIPIDSI_DPI_CFG_POL_dataen_active_low(dsi->date_enable_pol);
- set_MIPIDSI_DPI_CFG_POL_vsync_active_low(
- dsi->vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 0 : 1);
+ set_MIPIDSI_DPI_CFG_POL_vsync_active_low(dsi->vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 0 : 1);
set_MIPIDSI_DPI_CFG_POL_shutd_active_low(0);
set_MIPIDSI_DPI_CFG_POL_colorm_active_low(0);
if (dsi->format == MIPI_DSI_FMT_RGB666)
set_MIPIDSI_DPI_COLOR_CODING_loosely18_en(1);
/*
- * The DSI IP accepts vertical timing using lines as normal,
- * but horizontal timing is a mixture of pixel-clocks for the
- * active region and byte-lane clocks for the blanking-related
- * timings. hfp is specified as the total hline_time in byte-
- * lane clocks minus hsa, hbp and active.
- */
-
- htot = dsi->vm.hactive + dsi->vm.hsync_len +
- dsi->vm.hfront_porch + dsi->vm.hback_porch;
- vtot = dsi->vm.vactive + dsi->vm.vsync_len +
- dsi->vm.vfront_porch + dsi->vm.vback_porch;
-
- pixel_clk_kHz = dsi->vm.pixelclock;
-
- hsa_time = (dsi->vm.hsync_len * phyreg->lane_byte_clk_kHz) /
- pixel_clk_kHz;
- hbp_time = (dsi->vm.hback_porch * phyreg->lane_byte_clk_kHz) /
- pixel_clk_kHz;
- hline_time = (((u64)htot * (u64)phyreg->lane_byte_clk_kHz)) /
- pixel_clk_kHz;
- blc_hactive = (((u64)dsi->vm.hactive *
- (u64)phyreg->lane_byte_clk_kHz)) / pixel_clk_kHz;
-
-/* returns pixel clocks in dsi byte lane times, multiplied by 1000 */
-#define R(x) ((u32)((((u64)(x) * (u64)1000 * (u64)dsi->vm.pixelclock) / \
- phyreg->lane_byte_clk_kHz)))
-
- if ((R(hline_time) / 1000) > htot)
- hline_time--;
-
- if ((R(hline_time) / 1000) < htot)
- hline_time++;
-
- /* all specified in byte-lane clocks */
+ * 4. Define the DPI Horizontal timing configuration:
+ *
+ * Hsa_time = HSA*(PCLK period/Clk Lane Byte Period);
+ * Hbp_time = HBP*(PCLK period/Clk Lane Byte Period);
+ * Hline_time = (HSA+HBP+HACT+HFP)*(PCLK period/Clk Lane Byte Period);
+ */
+
+ pixel_clk = dsi->vm.pixelclock;
+ hsa_time = dsi->vm.hsync_len * phy_register->lane_byte_clk / pixel_clk;
+ hbp_time = dsi->vm.hback_porch * phy_register->lane_byte_clk / pixel_clk;
+ hline_time = (dsi->vm.hsync_len + dsi->vm.hback_porch +
+ dsi->vm.hactive + dsi->vm.hfront_porch) *
+ phy_register->lane_byte_clk / pixel_clk;
set_MIPIDSI_VID_HSA_TIME(hsa_time);
set_MIPIDSI_VID_HBP_TIME(hbp_time);
set_MIPIDSI_VID_HLINE_TIME(hline_time);
- DRM_INFO("%s: pixel_clk_kHz=%d, lane_byte_clk_kHz=%d, hsa=%d, "
- "hbp=%d, hline=%d", __func__, pixel_clk_kHz,
- phyreg->lane_byte_clk_kHz, hsa_time, hbp_time, hline_time);
-
+ DRM_INFO("%s,pixcel_clk=%d,lane_byte_clk=%d,hsa=%d,hbp=%d,hline=%d", __func__,
+ pixel_clk, phy_register->lane_byte_clk, hsa_time, hbp_time, hline_time);
+ /*
+ * 5. Define the Vertical line configuration:
+ *
+ */
if (dsi->vm.vsync_len > 15)
dsi->vm.vsync_len = 15;
@@ -627,97 +588,54 @@ int mipi_init(struct hisi_dsi *dsi)
set_MIPIDSI_VID_VBP_LINES(dsi->vm.vback_porch);
set_MIPIDSI_VID_VFP_LINES(dsi->vm.vfront_porch);
set_MIPIDSI_VID_VACTIVE_LINES(dsi->vm.vactive);
- set_MIPIDSI_VID_PKT_SIZE(dsi->vm.hactive); /* in DPI pixel clocks */
-
- refresh_nom = ((u64)dsi->nominal_pixel_clock_kHz * 1000000) /
- (htot * vtot);
-
- tmp = 1000000000 / dsi->vm.pixelclock;
- tmp1 = 1000000000 / phyreg->lane_byte_clk_kHz;
-
- pr_info("%s: Pixel clock: %ldkHz (%d.%03dns), "
- "DSI bytelane clock: %dkHz (%d.%03dns)\n",
- __func__, dsi->vm.pixelclock, tmp / 1000, tmp % 1000,
- phyreg->lane_byte_clk_kHz, tmp1 / 1000, tmp1 % 1000);
-
- pr_info("%s: CLK HACT VACT REFRSH HTOT VTOT HFP HSA HBP VFP VBP VSA\n",
- __func__);
-
-/* returns pixel clocks in dsi byte lane times, multiplied by 1000 */
-#define R(x) ((u32)((((u64)(x) * (u64)1000 * (u64)dsi->vm.pixelclock) / \
- phyreg->lane_byte_clk_kHz)))
-
- refresh_real = ((u64)dsi->vm.pixelclock * (u64)1000000000) /
- ((u64)R(hline_time) * (u64)vtot);
-
- pr_info("%s: nom: %6u %4u %4u %2u.%03u %4u %4u %3u %3u %3u %3u %3u %3u\n",
- __func__, dsi->nominal_pixel_clock_kHz,
- dsi->vm.hactive, dsi->vm.vactive,
- refresh_nom / 1000, refresh_nom % 1000, htot, vtot,
- dsi->vm.hfront_porch, dsi->vm.hsync_len,
- dsi->vm.hback_porch, dsi->vm.vfront_porch,
- dsi->vm.vsync_len, dsi->vm.vback_porch);
-
- pr_info("%s: tru: %6u %4u %4u %2u.%03u %4u.%03u %4u %3u.%03u %3u.%03u %3u.%03u %3u %3u %3u\n",
- __func__, (u32)dsi->vm.pixelclock,
- dsi->vm.hactive, dsi->vm.vactive,
- refresh_real / 1000, refresh_real % 1000,
- R(hline_time) / 1000, R(hline_time) % 1000, vtot,
- R(hline_time - hbp_time - hsa_time - blc_hactive) / 1000,
- R(hline_time - hbp_time - hsa_time - blc_hactive) % 1000,
- R(hsa_time) / 1000, R(hsa_time) % 1000,
- R(hbp_time) / 1000, R(hbp_time) % 1000,
- dsi->vm.vfront_porch,
- dsi->vm.vsync_len, dsi->vm.vback_porch);
+ set_MIPIDSI_VID_PKT_SIZE(dsi->vm.hactive);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
- /*
- * we disable this since it affects downstream
- * DSI -> HDMI converter output
- */
- set_MIPIDSI_VID_MODE_CFG_lp_vsa_en(0);
- set_MIPIDSI_VID_MODE_CFG_lp_vbp_en(0);
- set_MIPIDSI_VID_MODE_CFG_lp_vfp_en(0);
- set_MIPIDSI_VID_MODE_CFG_lp_vact_en(0);
- set_MIPIDSI_VID_MODE_CFG_lp_hbp_en(0);
- set_MIPIDSI_VID_MODE_CFG_lp_hfp_en(0);
-
- /*VSA/VBP/VFP max transfer byte in LP mode*/
+ set_MIPIDSI_VID_MODE_CFG_lp_vsa_en(1);
+ set_MIPIDSI_VID_MODE_CFG_lp_vbp_en(1);
+ set_MIPIDSI_VID_MODE_CFG_lp_vfp_en(1);
+ set_MIPIDSI_VID_MODE_CFG_lp_vact_en(1);
+ set_MIPIDSI_VID_MODE_CFG_lp_hbp_en(1);
+ set_MIPIDSI_VID_MODE_CFG_lp_hfp_en(1);
+ /*VSA/VBP/VFP max transfer byte in LP mode*/
set_MIPIDSI_DPI_CFG_LP_TIM(0);
- /* enable LP command transfer */
- set_MIPIDSI_VID_MODE_CFG_lp_cmd_en(0);
- /* config max read time */
- set_MIPIDSI_PHY_TMR_CFG_max_rd_time(0xFF);
+ /*enable LP command transfer*/
+ set_MIPIDSI_VID_MODE_CFG_lp_cmd_en(1);
+ /*config max read time*/
+ set_MIPIDSI_PHY_TMR_CFG_max_rd_time(0xFFFF);
}
/* Configure core's phy parameters */
set_MIPIDSI_BTA_TO_CNT_bta_to_cnt(4095);
- set_MIPIDSI_PHY_TMR_CFG_phy_lp2hs_time(phyreg->phy_lp2hs_time);
- set_MIPIDSI_PHY_TMR_CFG_phy_hs2lp_time(phyreg->phy_hs2lp_time);
- set_MIPIDSI_PHY_TMR_LPCLK_CFG_phy_clklp2hs_time(
- phyreg->phy_clklp2hs_time);
- set_MIPIDSI_PHY_TMR_LPCLK_CFG_phy_clkhs2lp_time(
- phyreg->phy_clkhs2lp_time);
- set_MIPIDSI_PHY_TMR_clk_to_data_delay(phyreg->clk_to_data_delay);
- set_MIPIDSI_PHY_TMR_data_to_clk_delay(phyreg->data_to_clk_delay);
-
+ set_MIPIDSI_PHY_TMR_CFG_phy_lp2hs_time(phy_register->phy_lp2hs_time);
+ set_MIPIDSI_PHY_TMR_CFG_phy_hs2lp_time(phy_register->phy_hs2lp_time);
+ set_MIPIDSI_PHY_TMR_LPCLK_CFG_phy_clklp2hs_time(phy_register->phy_clklp2hs_time);
+ set_MIPIDSI_PHY_TMR_LPCLK_CFG_phy_clkhs2lp_time(phy_register->phy_clkhs2lp_time);
+ set_MIPIDSI_PHY_TMR_clk_to_data_delay(phy_register->clk_to_data_delay);
+ set_MIPIDSI_PHY_TMR_data_to_clk_delay(phy_register->data_to_clk_delay);
+ /*
+ * 3. Select the Video Transmission Mode:
+ * This defines how the processor requires the video line to be
+ * transported through the DSI link.
+ */
set_MIPIDSI_VID_MODE_CFG_frame_bta_ack_en(0);
- set_MIPIDSI_VID_MODE_CFG_vid_mode_type(phyreg->burst_mode);
+ set_MIPIDSI_VID_MODE_CFG_vid_mode_type(phy_register->burst_mode);
set_MIPIDSI_LPCLK_CTRL_auto_clklane_ctrl(0);
/* for dsi read */
- set_MIPIDSI_PCKHDL_CFG_bta_en(0);
- /* Enable EOTP TX; Enable EDPI */
+ set_MIPIDSI_PCKHDL_CFG_bta_en(1);
+ /* Enable EOTP TX; Enable EDPI, ALLOWED_CMD_SIZE = 720*/
if (dsi->mode_flags == MIPI_DSI_MODE_VIDEO)
set_MIPIDSI_EDPI_CMD_SIZE(dsi->vm.hactive);
/*------------DSI and D-PHY Initialization-----------------*/
-
+ /* switch to video mode */
set_MIPIDSI_MODE_CFG(MIPIDSI_VIDEO_MODE);
+ /* enable generate High Speed clock */
set_MIPIDSI_LPCLK_CTRL_phy_txrequestclkhs(1);
+ /* Waking up Core */
set_MIPIDSI_PWR_UP_shutdownz(1);
-
DRM_INFO("%s , exit success!\n", __func__);
-
+ DRM_DEBUG_DRIVER("exit success.\n");
return 0;
}
@@ -744,12 +662,14 @@ static void hisi_dsi_enable(struct hisi_dsi *dsi)
static void hisi_dsi_disable(struct hisi_dsi *dsi)
{
DRM_DEBUG_DRIVER("enter.\n");
-
+ /*reset Core*/
set_MIPIDSI_PWR_UP_shutdownz(0);
+ /* disable generate High Speed clock */
set_MIPIDSI_LPCLK_CTRL_phy_txrequestclkhs(0);
+ /* shutdown d_phy */
set_MIPIDSI_PHY_RSTZ(0);
+ /* mipi dphy clock disable */
clk_disable_unprepare(dsi->dsi_cfg_clk);
-
DRM_DEBUG_DRIVER("exit success.\n");
}
@@ -816,12 +736,11 @@ static void hisi_drm_encoder_mode_set(struct drm_encoder *encoder,
struct hisi_dsi *dsi = encoder_to_dsi(encoder);
struct videomode *vm = &dsi->vm;
struct drm_encoder_slave_funcs *sfuncs = get_slave_funcs(encoder);
- u32 dphy_freq_kHz;
+ u32 dphy_freq_need;
+ u32 dphy_freq_true;
DRM_DEBUG_DRIVER("enter.\n");
- vm->pixelclock = adjusted_mode->clock;
- dsi->nominal_pixel_clock_kHz = mode->clock;
-
+ vm->pixelclock = mode->clock/1000;
vm->hactive = mode->hdisplay;
vm->vactive = mode->vdisplay;
vm->vfront_porch = mode->vsync_start - mode->vdisplay;
@@ -831,14 +750,12 @@ static void hisi_drm_encoder_mode_set(struct drm_encoder *encoder,
vm->hback_porch = mode->htotal - mode->hsync_end;
vm->hsync_len = mode->hsync_end - mode->hsync_start;
- dsi->lanes = 3 + !!(vm->pixelclock >= 115000);
-
- dphy_freq_kHz = vm->pixelclock * 24 / dsi->lanes;
- /* this avoids a less-compatible DSI rate with 1.2GHz px PLL */
- if (dphy_freq_kHz == 600000)
- dphy_freq_kHz = 640000;
-
- set_dsi_phy_rate_equal_or_faster(&dphy_freq_kHz, &dsi->phyreg);
+ /* laneBitRate >= pixelClk*24/lanes */
+ if (vm->vactive == 720 && vm->pixelclock == 75)
+ dphy_freq_true = dphy_freq_need = 640; /* for 720p 640M is more stable */
+ else
+ dphy_freq_true = dphy_freq_need = vm->pixelclock*24/dsi->lanes;
+ get_dsi_phy_register(&dphy_freq_true, &dsi->phy_register);
vm->flags = 0;
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -852,8 +769,8 @@ static void hisi_drm_encoder_mode_set(struct drm_encoder *encoder,
if (sfuncs->mode_set)
sfuncs->mode_set(encoder, mode, adjusted_mode);
- DRM_DEBUG_DRIVER("exit success: pixelclk=%dkHz, dphy_freq_kHz=%dkHz\n",
- (u32)vm->pixelclock, dphy_freq_kHz);
+ DRM_DEBUG_DRIVER("exit success: pixelclk=%d,dphy_freq_need=%d, dphy_freq_true=%d\n",
+ (u32)vm->pixelclock, dphy_freq_need, dphy_freq_true);
}
static void hisi_drm_encoder_prepare(struct drm_encoder *encoder)
@@ -906,26 +823,45 @@ static void hisi_dsi_connector_destroy(struct drm_connector *connector)
drm_connector_cleanup(connector);
}
-static int hisi_dsi_fallback_mode(struct drm_connector *connector)
-{
- struct drm_display_mode *mode = kmalloc(sizeof(*mode), GFP_KERNEL);
-
- pr_info("%s: adding canned fallback 720p mode\n", __func__);
- memcpy(mode, &mode_720p_canned, sizeof(*mode));
-
- list_add_tail(&mode->head, &connector->modes);
-
- return 0;
-}
-
static struct drm_connector_funcs hisi_dsi_connector_funcs = {
.dpms = drm_helper_connector_dpms,
.fill_modes = drm_helper_probe_single_connector_modes,
.detect = hisi_dsi_detect,
- .destroy = hisi_dsi_connector_destroy,
- .fallback_mode = hisi_dsi_fallback_mode,
+ .destroy = hisi_dsi_connector_destroy
};
+#if USE_DEFAULT_720P_MODE
+static int hisi_get_default_modes(struct drm_connector *connector)
+{
+ struct drm_display_mode *mode;
+
+ DRM_DEBUG_DRIVER("enter.\n");
+ mode = drm_mode_create(connector->dev);
+ if (!mode) {
+ DRM_ERROR("failed to create a new display mode\n");
+ return 0;
+ }
+
+ mode->vrefresh = 60;
+ mode->clock = 75000;
+ mode->hdisplay = 1280;
+ mode->hsync_start = 1500;
+ mode->hsync_end = 1540;
+ mode->htotal = 1650;
+ mode->vdisplay = 720;
+ mode->vsync_start = 740;
+ mode->vsync_end = 745;
+ mode->vtotal = 750;
+ mode->type = 0x40;
+ mode->flags = 0xa;
+ drm_mode_set_name(mode);
+ drm_mode_probed_add(connector, mode);
+
+ DRM_DEBUG_DRIVER("exit successfully.\n");
+ return 1;
+}
+#endif
+
static int hisi_dsi_get_modes(struct drm_connector *connector)
{
struct hisi_dsi *dsi __maybe_unused = connector_to_dsi(connector);
@@ -935,8 +871,12 @@ static int hisi_dsi_get_modes(struct drm_connector *connector)
int count = 0;
DRM_DEBUG_DRIVER("enter.\n");
+#if USE_DEFAULT_720P_MODE
+ count = hisi_get_default_modes(connector);
+#else
if (sfuncs->get_modes)
count = sfuncs->get_modes(encoder, connector);
+#endif
DRM_DEBUG_DRIVER("exit success. count=%d\n", count);
return count;
}
@@ -960,11 +900,13 @@ static int hisi_drm_connector_mode_valid(struct drm_connector *connector,
struct drm_encoder_slave_funcs *sfuncs = get_slave_funcs(encoder);
int ret = MODE_OK;
- if (sfuncs->mode_valid) {
+ /* For 3 lanes bandwith is limited */
+ if (mode->vdisplay > 1000)
+ return MODE_BAD_VVALUE;
+
+ DRM_DEBUG_DRIVER("enter.\n");
+ if (sfuncs->mode_valid)
ret = sfuncs->mode_valid(encoder, mode);
- if (ret != MODE_OK)
- return ret;
- }
DRM_DEBUG_DRIVER("exit success. ret=%d\n", ret);
return ret;
@@ -1072,15 +1014,10 @@ static int hisi_dsi_probe(struct platform_device *pdev)
return -EPROBE_DEFER;
}
- if (!dsi->client->dev.driver) {
- DRM_INFO("%s: NULL client driver\n", __func__);
- return -EPROBE_DEFER;
- }
-
dsi->drm_i2c_driver = to_drm_i2c_encoder_driver(
to_i2c_driver(dsi->client->dev.driver));
- if (IS_ERR(dsi->drm_i2c_driver)) {
- pr_err("failed initialize encoder driver %ld\n", PTR_ERR(dsi->drm_i2c_driver));
+ if (!dsi->drm_i2c_driver) {
+ DRM_INFO("failed initialize encoder driver\n");
return -EPROBE_DEFER;
}
diff --git a/drivers/gpu/drm/hisilicon/hisi_ldi_reg.h b/drivers/gpu/drm/hisilicon/hisi_ldi_reg.h
index f89ced7cedc8..e59f2dec717b 100644
--- a/drivers/gpu/drm/hisilicon/hisi_ldi_reg.h
+++ b/drivers/gpu/drm/hisilicon/hisi_ldi_reg.h
@@ -40,6 +40,48 @@
#define HISI_LDI_FLAG_NDE BIT(3)
/********** LDI Register Union Struct ***********/
+union U_LDI_HRZ_CTRL0 {
+struct {
+ unsigned int hfp :12;
+ unsigned int Reserved_564 :8;
+ unsigned int hbp :12;
+ } bits;
+ unsigned int u32;
+};
+
+union U_LDI_HRZ_CTRL1 {
+struct {
+ unsigned int hsw :12;
+ unsigned int Reserved_566 :20;
+ } bits;
+ unsigned int u32;
+};
+
+union U_LDI_VRT_CTRL0 {
+struct {
+ unsigned int vfp :12;
+ unsigned int Reserved_567 :8;
+ unsigned int vbp :12;
+ } bits;
+ unsigned int u32;
+};
+
+union U_LDI_VRT_CTRL1 {
+struct {
+ unsigned int vsw :12;
+ unsigned int Reserved_568 :20;
+ } bits;
+ unsigned int u32;
+};
+
+union U_LDI_DSP_SIZE {
+struct {
+ unsigned int hsize :12;
+ unsigned int Reserved_570 :8;
+ unsigned int vsize :12;
+ } bits;
+ unsigned int u32;
+};
union U_LDI_CTRL {
struct {
@@ -80,6 +122,58 @@ static inline void set_reg(u8 *addr, u32 val, u32 bw, u32 bs)
writel(tmp | ((val & mask) << bs), addr);
}
+static inline void set_LDI_HRZ_CTRL0(u8 *ade_base, u32 hfp, u32 hbp)
+{
+ volatile union U_LDI_HRZ_CTRL0 ldi_hrz_ctrl0;
+ u8 *addr = ade_base + LDI_HRZ_CTRL0_REG;
+
+ ldi_hrz_ctrl0.u32 = readl(addr);
+ ldi_hrz_ctrl0.bits.hfp = hfp;
+ ldi_hrz_ctrl0.bits.hbp = hbp;
+ writel(ldi_hrz_ctrl0.u32, addr);
+}
+
+static inline void set_LDI_HRZ_CTRL1_hsw(u8 *ade_base, u32 nVal)
+{
+ volatile union U_LDI_HRZ_CTRL1 ldi_hrz_ctrl1;
+ u8 *addr = ade_base + LDI_HRZ_CTRL1_REG;
+
+ ldi_hrz_ctrl1.u32 = readl(addr);
+ ldi_hrz_ctrl1.bits.hsw = (nVal > 0) ? nVal - 1 : 0;
+ writel(ldi_hrz_ctrl1.u32, addr);
+}
+
+static inline void set_LDI_VRT_CTRL0(u8 *ade_base, u32 vfp, u32 vbp)
+{
+ volatile union U_LDI_VRT_CTRL0 ldi_vrt_ctrl0;
+ u8 *addr = ade_base + LDI_VRT_CTRL0_REG;
+
+ ldi_vrt_ctrl0.u32 = readl(addr);
+ ldi_vrt_ctrl0.bits.vfp = vfp;
+ ldi_vrt_ctrl0.bits.vbp = vbp;
+ writel(ldi_vrt_ctrl0.u32, addr);
+}
+
+static inline void set_LDI_VRT_CTRL1_vsw(u8 *ade_base, u32 nVal)
+{
+ volatile union U_LDI_VRT_CTRL1 ldi_vrt_ctrl1;
+ u8 *addr = ade_base + LDI_VRT_CTRL1_REG;
+
+ ldi_vrt_ctrl1.u32 = readl(addr);
+ ldi_vrt_ctrl1.bits.vsw = (nVal > 0) ? nVal - 1 : 0;
+ writel(ldi_vrt_ctrl1.u32, addr);
+}
+
+static inline void set_LDI_DSP_SIZE_size(u8 *ade_base, u32 hVal, u32 vVal)
+{
+ volatile union U_LDI_DSP_SIZE ldi_dsp_size;
+ u8 *addr = ade_base + LDI_DSP_SIZE_REG;
+
+ ldi_dsp_size.bits.hsize = (hVal > 0) ? hVal-1 : 0;
+ ldi_dsp_size.bits.vsize = (vVal > 0) ? vVal-1 : 0;
+ writel(ldi_dsp_size.u32, addr);
+}
+
static inline void set_LDI_CTRL_ldi_en(u8 *ade_base, u32 nVal)
{
volatile union U_LDI_CTRL ldi_ctrl;
diff --git a/drivers/gpu/drm/i2c/Kconfig b/drivers/gpu/drm/i2c/Kconfig
index b44c15ab4f33..899796d21f4b 100644
--- a/drivers/gpu/drm/i2c/Kconfig
+++ b/drivers/gpu/drm/i2c/Kconfig
@@ -1,51 +1,11 @@
menu "I2C encoder or helper chips"
depends on DRM && DRM_KMS_HELPER && I2C
-config DRM_I2C_ADV7511
- tristate "AV7511 encoder"
- select REGMAP_I2C
- help
- Support for the Analog Device ADV7511(W) and ADV7513 HDMI encoders.
-
-config DRM_I2C_ADV7511_SLAVE_ENCODER
- tristate "Use ADV7511 as an I2C slave encoder"
- default y
- depends on DRM_I2C_ADV7511
- help
- Configure ADV7511 as an I2C slave encoder. Selecting 'n' will
- configure the driver as a drm bridge driver
-
-config DRM_I2C_ADV7511_SLAVE_ENCODER
- tristate "Use ADV7511 as an I2C slave encoder"
- default y
- depends on DRM_I2C_ADV7511
- help
- Configure ADV7511 as an I2C slave encoder. Selecting 'n' will
- configure the driver as a drm bridge driver
-
-config DRM_I2C_ADV7511_SLAVE_ENCODER
- tristate "Use ADV7511 as an I2C slave encoder"
- default y
- depends on DRM_I2C_ADV7511
- help
- Configure ADV7511 as an I2C slave encoder. Selecting 'n' will
- configure the driver as a drm bridge driver
-
-config DRM_I2C_ADV7511_SLAVE_ENCODER
- tristate "Use ADV7511 as an I2C slave encoder"
- default y
- depends on DRM_I2C_ADV7511
- help
- Configure ADV7511 as an I2C slave encoder. Selecting 'n' will
- configure the driver as a drm bridge driver
-
-config DRM_I2C_ADV7511_SLAVE_ENCODER
- tristate "Use ADV7511 as an I2C slave encoder"
- default y
- depends on DRM_I2C_ADV7511
+config DRM_I2C_ADV7533
+ tristate "ADV7533 encoder"
+ select REGMAP_I2C
help
- Configure ADV7511 as an I2C slave encoder. Selecting 'n' will
- configure the driver as a drm bridge driver
+ Support for the Analog Device ADV7533 HDMI encoders.
config DRM_I2C_CH7006
tristate "Chrontel ch7006 TV encoder"
diff --git a/drivers/gpu/drm/i2c/Makefile b/drivers/gpu/drm/i2c/Makefile
index 2c72eb584ab7..f6002059f8b9 100644
--- a/drivers/gpu/drm/i2c/Makefile
+++ b/drivers/gpu/drm/i2c/Makefile
@@ -1,6 +1,6 @@
ccflags-y := -Iinclude/drm
-obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
+obj-$(CONFIG_DRM_I2C_ADV7533) += adv7533.o
ch7006-y := ch7006_drv.o ch7006_mode.o
obj-$(CONFIG_DRM_I2C_CH7006) += ch7006.o
diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/i2c/adv7511.c
deleted file mode 100644
index 916964f85081..000000000000
--- a/drivers/gpu/drm/i2c/adv7511.c
+++ /dev/null
@@ -1,1561 +0,0 @@
-/*
- * Analog Devices ADV7511 HDMI transmitter driver
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/device.h>
-#include <linux/gpio/consumer.h>
-#include <linux/i2c.h>
-#include <linux/module.h>
-#include <linux/regmap.h>
-#include <linux/slab.h>
-
-#include <drm/drmP.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_encoder_slave.h>
-//#include <drm/drm_atomic.h>
-//#include <drm/drm_atomic_helper.h>
-#include <drm/drm_mipi_dsi.h>
-#include <linux/of_irq.h>
-
-#include "adv7511.h"
-
-/* uncomment to enable Internal Timing Generator + DE */
-//#define ITG
-
-/* uncomment to force plug detect always */
-#define FORCE_HPD
-
-/* ADI recommended values for proper operation. */
-static const struct reg_default adv7511_fixed_registers[] = {
- { 0x98, 0x03 },
- { 0x9a, 0xe0 },
- { 0x9c, 0x30 },
- { 0x9d, 0x61 },
- { 0xa2, 0xa4 },
- { 0xa3, 0xa4 },
- { 0xe0, 0xd0 },
- { 0xf9, 0x00 },
- { 0x55, 0x02 },
-};
-
-/* ADI recommended values for proper operation. */
-static const struct reg_default adv7533_fixed_registers[] = {
- { 0x16, 0x20 },
- { 0x9a, 0xe0 },
- { 0xba, 0x70 },
- { 0xde, 0x82 },
- { 0xe4, 0x40 },
- { 0xe5, 0x80 },
-};
-
-static const struct reg_default adv7533_cec_fixed_registers[] = {
- { 0x15, 0xd0 },
- { 0x17, 0xd0 },
- { 0x24, 0x20 },
- { 0x57, 0x11 },
- { 0x05, 0xc8 },
-};
-
-/* -----------------------------------------------------------------------------
- * Register access
- */
-
-static const uint8_t adv7511_register_defaults[] = {
- 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00 */
- 0x00, 0x00, 0x01, 0x0e, 0xbc, 0x18, 0x01, 0x13,
- 0x25, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 10 */
- 0x46, 0x62, 0x04, 0xa8, 0x00, 0x00, 0x1c, 0x84,
- 0x1c, 0xbf, 0x04, 0xa8, 0x1e, 0x70, 0x02, 0x1e, /* 20 */
- 0x00, 0x00, 0x04, 0xa8, 0x08, 0x12, 0x1b, 0xac,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 */
- 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0xb0,
- 0x00, 0x50, 0x90, 0x7e, 0x79, 0x70, 0x00, 0x00, /* 40 */
- 0x00, 0xa8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x02, 0x0d, 0x00, 0x00, 0x00, 0x00, /* 50 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 60 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 70 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 80 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, /* 90 */
- 0x0b, 0x02, 0x00, 0x18, 0x5a, 0x60, 0x00, 0x00,
- 0x00, 0x00, 0x80, 0x80, 0x08, 0x04, 0x00, 0x00, /* a0 */
- 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x40, 0x14,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* b0 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c0 */
- 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x01, 0x04,
- 0x30, 0xff, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, /* d0 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01,
- 0x80, 0x75, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, /* e0 */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x11, 0x00, /* f0 */
- 0x00, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
-static bool adv7511_register_volatile(struct device *dev, unsigned int reg)
-{
- switch (reg) {
- case ADV7511_REG_CHIP_REVISION:
- case ADV7511_REG_SPDIF_FREQ:
- case ADV7511_REG_CTS_AUTOMATIC1:
- case ADV7511_REG_CTS_AUTOMATIC2:
- case ADV7511_REG_VIC_DETECTED:
- case ADV7511_REG_VIC_SEND:
- case ADV7511_REG_AUX_VIC_DETECTED:
- case ADV7511_REG_STATUS:
- case ADV7511_REG_GC(1):
- case ADV7511_REG_INT(0):
- case ADV7511_REG_INT(1):
- case ADV7511_REG_PLL_STATUS:
- case ADV7511_REG_AN(0):
- case ADV7511_REG_AN(1):
- case ADV7511_REG_AN(2):
- case ADV7511_REG_AN(3):
- case ADV7511_REG_AN(4):
- case ADV7511_REG_AN(5):
- case ADV7511_REG_AN(6):
- case ADV7511_REG_AN(7):
- case ADV7511_REG_HDCP_STATUS:
- case ADV7511_REG_BCAPS:
- case ADV7511_REG_BKSV(0):
- case ADV7511_REG_BKSV(1):
- case ADV7511_REG_BKSV(2):
- case ADV7511_REG_BKSV(3):
- case ADV7511_REG_BKSV(4):
- case ADV7511_REG_DDC_STATUS:
- case ADV7511_REG_BSTATUS(0):
- case ADV7511_REG_BSTATUS(1):
- case ADV7511_REG_CHIP_ID_HIGH:
- case ADV7511_REG_CHIP_ID_LOW:
- return true;
- }
-
- return false;
-}
-
-static const struct regmap_config adv7511_regmap_config = {
- .reg_bits = 8,
- .val_bits = 8,
-
- .max_register = 0xff,
- .cache_type = REGCACHE_RBTREE,
- .reg_defaults_raw = adv7511_register_defaults,
- .num_reg_defaults_raw = ARRAY_SIZE(adv7511_register_defaults),
-
- .volatile_reg = adv7511_register_volatile,
-};
-
-static const struct regmap_config adv7533_cec_regmap_config = {
- .reg_bits = 8,
- .val_bits = 8,
-
- .max_register = 0xff,
- .cache_type = REGCACHE_RBTREE,
-};
-
-
-/* -----------------------------------------------------------------------------
- * Hardware configuration
- */
-
-static void adv7511_set_colormap(struct adv7511 *adv7511, bool enable,
- const uint16_t *coeff,
- unsigned int scaling_factor)
-{
- unsigned int i;
-
- regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(1),
- ADV7511_CSC_UPDATE_MODE, ADV7511_CSC_UPDATE_MODE);
-
- if (enable) {
- for (i = 0; i < 12; ++i) {
- regmap_update_bits(adv7511->regmap,
- ADV7511_REG_CSC_UPPER(i),
- 0x1f, coeff[i] >> 8);
- regmap_write(adv7511->regmap,
- ADV7511_REG_CSC_LOWER(i),
- coeff[i] & 0xff);
- }
- }
-
- if (enable)
- regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(0),
- 0xe0, 0x80 | (scaling_factor << 5));
- else
- regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(0),
- 0x80, 0x00);
-
- regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(1),
- ADV7511_CSC_UPDATE_MODE, 0);
-}
-
-int adv7511_packet_enable(struct adv7511 *adv7511, unsigned int packet)
-{
- if (packet & 0xff)
- regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE0,
- packet, 0xff);
-
- if (packet & 0xff00) {
- packet >>= 8;
- regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE1,
- packet, 0xff);
- }
-
- return 0;
-}
-
-int adv7511_packet_disable(struct adv7511 *adv7511, unsigned int packet)
-{
- if (packet & 0xff)
- regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE0,
- packet, 0x00);
-
- if (packet & 0xff00) {
- packet >>= 8;
- regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE1,
- packet, 0x00);
- }
-
- return 0;
-}
-
-/* Coefficients for adv7511 color space conversion */
-static const uint16_t adv7511_csc_ycbcr_to_rgb[] = {
- 0x0734, 0x04ad, 0x0000, 0x1c1b,
- 0x1ddc, 0x04ad, 0x1f24, 0x0135,
- 0x0000, 0x04ad, 0x087c, 0x1b77,
-};
-
-static void adv7511_set_config_csc(struct adv7511 *adv7511,
- struct drm_connector *connector,
- bool rgb)
-{
- struct adv7511_video_config config;
- bool output_format_422, output_format_ycbcr;
- unsigned int mode;
- uint8_t infoframe[17];
-
- if (adv7511->edid)
- config.hdmi_mode = drm_detect_hdmi_monitor(adv7511->edid);
- else
- config.hdmi_mode = false;
-
- hdmi_avi_infoframe_init(&config.avi_infoframe);
-
- config.avi_infoframe.scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
-
- if (rgb) {
- config.csc_enable = false;
- config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB;
- } else {
- config.csc_scaling_factor = ADV7511_CSC_SCALING_4;
- config.csc_coefficents = adv7511_csc_ycbcr_to_rgb;
-
- if ((connector->display_info.color_formats &
- DRM_COLOR_FORMAT_YCRCB422) &&
- config.hdmi_mode) {
- config.csc_enable = false;
- config.avi_infoframe.colorspace =
- HDMI_COLORSPACE_YUV422;
- } else {
- config.csc_enable = true;
- config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB;
- }
- }
-
- if (config.hdmi_mode) {
- mode = ADV7511_HDMI_CFG_MODE_HDMI;
-
- switch (config.avi_infoframe.colorspace) {
- case HDMI_COLORSPACE_YUV444:
- output_format_422 = false;
- output_format_ycbcr = true;
- break;
- case HDMI_COLORSPACE_YUV422:
- output_format_422 = true;
- output_format_ycbcr = true;
- break;
- default:
- output_format_422 = false;
- output_format_ycbcr = false;
- break;
- }
- } else {
- mode = ADV7511_HDMI_CFG_MODE_DVI;
- output_format_422 = false;
- output_format_ycbcr = false;
- }
-
- adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME);
-
- adv7511_set_colormap(adv7511, config.csc_enable,
- config.csc_coefficents,
- config.csc_scaling_factor);
-
- regmap_update_bits(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG1, 0x81,
- (output_format_422 << 7) | output_format_ycbcr);
-
- regmap_update_bits(adv7511->regmap, ADV7511_REG_HDCP_HDMI_CFG,
- ADV7511_HDMI_CFG_MODE_MASK, mode);
-
- hdmi_avi_infoframe_pack(&config.avi_infoframe, infoframe,
- sizeof(infoframe));
-
- /* The AVI infoframe id is not configurable */
- regmap_bulk_write(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME_VERSION,
- infoframe + 1, sizeof(infoframe) - 1);
-
- adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME);
-}
-
-static void adv7511_set_link_config(struct adv7511 *adv7511,
- const struct adv7511_link_config *config)
-{
- /*
- * The input style values documented in the datasheet don't match the
- * hardware register field values :-(
- */
- static const unsigned int input_styles[4] = { 0, 2, 1, 3 };
-
- unsigned int clock_delay;
- unsigned int color_depth;
- unsigned int input_id;
-
- adv7511->rgb = config->input_colorspace == HDMI_COLORSPACE_RGB;
-
- /*
- * TODO: some of the below configurations might be needed for ADV7533
- * too, check in ADV7533 spec.
- */
- if (adv7511->type == ADV7533) {
- adv7511->num_dsi_lanes = config->num_dsi_lanes;
- return;
- }
-
- clock_delay = (config->clock_delay + 1200) / 400;
- color_depth = config->input_color_depth == 8 ? 3
- : (config->input_color_depth == 10 ? 1 : 2);
-
- /* TODO Support input ID 6 */
- if (config->input_colorspace != HDMI_COLORSPACE_YUV422)
- input_id = config->input_clock == ADV7511_INPUT_CLOCK_DDR
- ? 5 : 0;
- else if (config->input_clock == ADV7511_INPUT_CLOCK_DDR)
- input_id = config->embedded_sync ? 8 : 7;
- else if (config->input_clock == ADV7511_INPUT_CLOCK_2X)
- input_id = config->embedded_sync ? 4 : 3;
- else
- input_id = config->embedded_sync ? 2 : 1;
-
- regmap_update_bits(adv7511->regmap, ADV7511_REG_I2C_FREQ_ID_CFG, 0xf,
- input_id);
- regmap_update_bits(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG1, 0x7e,
- (color_depth << 4) |
- (input_styles[config->input_style] << 2));
- regmap_write(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG2,
- config->input_justification << 3);
- regmap_write(adv7511->regmap, ADV7511_REG_TIMING_GEN_SEQ,
- config->sync_pulse << 2);
-
- regmap_write(adv7511->regmap, 0xba, clock_delay << 5);
-
- adv7511->embedded_sync = config->embedded_sync;
- adv7511->hsync_polarity = config->hsync_polarity;
- adv7511->vsync_polarity = config->vsync_polarity;
-}
-
-static void adv7511_dsi_config_tgen(struct adv7511 *adv7511)
-{
- struct drm_display_mode *mode = adv7511->curr_mode;
- unsigned int hsw, hfp, hbp, vsw, vfp, vbp, hd, vd;
-
- hsw = mode->hsync_end - mode->hsync_start;
- hfp = mode->hsync_start - mode->hdisplay;
- hbp = mode->htotal - mode->hsync_end;
- vsw = mode->vsync_end - mode->vsync_start;
- vfp = mode->vsync_start - mode->vdisplay;
- vbp = mode->vtotal - mode->vsync_end;
- hd = hsw + hbp - 1;
- vd = vsw + vbp;
-
- /* set pixel clock divider mode to auto */
- regmap_write(adv7511->regmap_cec, 0x16, 0x00);
-
- pr_info("%s: ITG HTOT=%d, HSA=%d, HFP=%d, HBP=%d\n",
- __func__, mode->htotal, hsw, hfp, hbp);
- pr_info("%s: ITG VTOT=%d, VSA=%d, VFP=%d, VBP=%d\n",
- __func__, mode->vtotal, vsw, vfp, vbp);
-
- /* horizontal porch params */
- regmap_write(adv7511->regmap_cec, 0x28, mode->htotal >> 4);
- regmap_write(adv7511->regmap_cec, 0x29, (mode->htotal << 4) & 0xff);
- regmap_write(adv7511->regmap_cec, 0x2a, hsw >> 4);
- regmap_write(adv7511->regmap_cec, 0x2b, (hsw << 4) & 0xff);
- regmap_write(adv7511->regmap_cec, 0x2c, hfp >> 4);
- regmap_write(adv7511->regmap_cec, 0x2d, (hfp << 4) & 0xff);
- regmap_write(adv7511->regmap_cec, 0x2e, hbp >> 4);
- regmap_write(adv7511->regmap_cec, 0x2f, (hbp << 4) & 0xff);
-
- /* vertical porch params */
- regmap_write(adv7511->regmap_cec, 0x30, mode->vtotal >> 4);
- regmap_write(adv7511->regmap_cec, 0x31, (mode->vtotal << 4) & 0xff);
- regmap_write(adv7511->regmap_cec, 0x32, vsw >> 4);
- regmap_write(adv7511->regmap_cec, 0x33, (vsw << 4) & 0xff);
- regmap_write(adv7511->regmap_cec, 0x34, vfp >> 4);
- regmap_write(adv7511->regmap_cec, 0x35, (vfp << 4) & 0xff);
- regmap_write(adv7511->regmap_cec, 0x36, vbp >> 4);
- regmap_write(adv7511->regmap_cec, 0x37, (vbp << 4) & 0xff);
-
- /* DE generator */
-
- pr_info("%s: DE HSDLY=%d, VSDLY=%d, HACT=%d, VACT=%d\n",
- __func__, hd, vd, mode->hdisplay, mode->vdisplay);
-
-
- /* DE generation HSYNC delay */
- regmap_write(adv7511->regmap, 0x35, hd >> 2);
- regmap_write(adv7511->regmap, 0x36, (hd << 6) | (vd >> 3));
- /* DE generation VSYNC delay */
- regmap_write(adv7511->regmap, 0x37, (vd << 5) |
- (mode->hdisplay >> 7));
- regmap_write(adv7511->regmap, 0x38, (mode->hdisplay << 1));
- regmap_write(adv7511->regmap, 0x39, (mode->vdisplay >> 4));
- regmap_write(adv7511->regmap, 0x3a, (mode->vdisplay << 4));
-
-
- regmap_write(adv7511->regmap, 0xd0, BIT(1));
-
- pr_info("%s: DE HSPLA=%d, VSPLA=%d\n",
- __func__, hfp, vfp);
-
-
- /* hsync placement relative to DE end */
- regmap_write(adv7511->regmap, 0xd7, (hfp >> 2));
- regmap_write(adv7511->regmap, 0xd8, (hfp << 6) |
- (hsw >> 4));
- regmap_write(adv7511->regmap, 0xd9, (hsw << 4) |
- /* vsync placement relative to DE end */
- (vfp >> 6));
- regmap_write(adv7511->regmap, 0xda, (vfp << 2) |
- (vsw >> 8));
- regmap_write(adv7511->regmap, 0xdb, vsw);
-
-#ifdef ITG
- regmap_update_bits(adv7511->regmap, 0x17, BIT(0), BIT(0));
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER, BIT(1), BIT(1));
-#endif
-}
-
-static void adv7511_dsi_receiver_dpms(struct adv7511 *adv7511)
-{
- if (adv7511->type != ADV7533)
- return;
-
- if (adv7511->powered) {
- adv7511_dsi_config_tgen(adv7511);
-
-#ifdef ITG
- /* reset internal timing generator */
- regmap_write(adv7511->regmap_cec, 0x27, 0xcb);
- regmap_write(adv7511->regmap_cec, 0x27, 0x8b);
- regmap_write(adv7511->regmap_cec, 0x27, 0xcb);
-#else
- /* disable internal timing generator */
- regmap_write(adv7511->regmap_cec, 0x27, 0x0b);
-#endif
-
- /* enable hdmi */
- regmap_write(adv7511->regmap_cec, 0x03, 0x89);
-
- /* explicitly disable test mode */
- regmap_write(adv7511->regmap_cec, 0x55, 0x00);
- /* deassert DSI reset */
- regmap_update_bits(adv7511->regmap, 0x26, BIT(5), 0);
- /* Black OFF */
- regmap_write(adv7511->regmap, 0xd5, 0);
- } else {
- /* Black ON */
- regmap_write(adv7511->regmap, 0xd5, 1);
- regmap_write(adv7511->regmap_cec, 0x03, 0x0b);
- regmap_write(adv7511->regmap_cec, 0x27, 0x0b);
- /* assert DSI reset */
- regmap_update_bits(adv7511->regmap, 0x26, BIT(5), BIT(5));
- }
-}
-
-static void adv7511_power_on(struct adv7511 *adv7511)
-{
- adv7511->current_edid_segment = -1;
-
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
- ADV7511_POWER_POWER_DOWN, 0);
-
- /*
- * Per spec it is allowed to pulse the HDP signal to indicate that the
- * EDID information has changed. Some monitors do this when they wakeup
- * from standby or are enabled. When the HDP goes low the adv7511 is
- * reset and the outputs are disabled which might cause the monitor to
- * go to standby again. To avoid this we ignore the HDP pin for the
- * first few seconds after enabling the output.
- */
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
- ADV7511_REG_POWER2_HDP_SRC_MASK, 0x40);
-
- /*
- * Most of the registers are reset during power down or when HPD is low.
- */
- regcache_sync(adv7511->regmap);
-
- adv7511->powered = true;
-
- adv7511_dsi_receiver_dpms(adv7511);
-}
-
-static void adv7511_power_off(struct adv7511 *adv7511)
-{
- /* TODO: setup additional power down modes */
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
- ADV7511_POWER_POWER_DOWN,
- ADV7511_POWER_POWER_DOWN);
- regcache_mark_dirty(adv7511->regmap);
-
- adv7511->powered = false;
-
- adv7511_dsi_receiver_dpms(adv7511);
-}
-
-/* -----------------------------------------------------------------------------
- * Interrupt and hotplug detection
- */
-#ifndef FORCE_HPD
-static bool adv7511_hpd(struct adv7511 *adv7511)
-{
- unsigned int irq0;
- int ret;
-
- ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(0), &irq0);
- if (ret < 0)
- return false;
-
- if (irq0 & ADV7511_INT0_HDP) {
- regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
- ADV7511_INT0_HDP);
- return true;
- }
-
- return false;
-}
-#endif
-
-static int adv7511_irq_process(struct adv7511 *adv7511)
-{
- unsigned int irq0, irq1;
- int ret;
-
- ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(0), &irq0);
- if (ret < 0)
- return ret;
-
- ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(1), &irq1);
- if (ret < 0)
- return ret;
-
- regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0);
- regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1);
-
- if (adv7511->encoder && (irq0 & ADV7511_INT0_HDP))
- drm_helper_hpd_irq_event(adv7511->encoder->dev);
-
- if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) {
- adv7511->edid_read = true;
-
- if (adv7511->irq)
- wake_up_all(&adv7511->wq);
- }
-
- return 0;
-}
-
-static irqreturn_t adv7511_irq_handler(int irq, void *devid)
-{
- struct adv7511 *adv7511 = devid;
- int ret;
-
- ret = adv7511_irq_process(adv7511);
- return ret < 0 ? IRQ_NONE : IRQ_HANDLED;
-}
-
-/* -----------------------------------------------------------------------------
- * EDID retrieval
- */
-
-static int adv7511_get_edid_block(void *data, u8 *buf, unsigned int block,
- size_t len)
-{
- struct adv7511 *adv7511 = data;
- struct i2c_msg xfer[2];
- uint8_t offset;
- unsigned int i;
- int ret;
- int timeout = 100;
-
- if (len > 128)
- return -EINVAL;
-
- if (adv7511->current_edid_segment != block / 2) {
- unsigned int status;
-
- adv7511->edid_read = false;
-
- while (--timeout) {
- ret = regmap_read(adv7511->regmap,
- ADV7511_REG_DDC_STATUS, &status);
- if (ret < 0) {
- pr_err("a\n");
- return ret;
- }
- if (status == 2)
- break;
-
- msleep(10);
- }
-
- if (!timeout)
- return -ETIMEDOUT;
-
- /* Break this apart, hopefully more I2C controllers will
- * support 64 byte transfers than 256 byte transfers
- */
-
- xfer[0].addr = adv7511->i2c_edid->addr;
- xfer[0].flags = 0;
- xfer[0].len = 1;
- xfer[0].buf = &offset;
- xfer[1].addr = adv7511->i2c_edid->addr;
- xfer[1].flags = I2C_M_RD;
- xfer[1].len = 64;
- xfer[1].buf = adv7511->edid_buf;
-
- offset = 0;
-
- for (i = 0; i < 4; ++i) {
- ret = i2c_transfer(adv7511->i2c_edid->adapter, xfer,
- ARRAY_SIZE(xfer));
- if (ret < 0)
- return ret;
-
- else if (ret != 2)
- return -EIO;
-
- xfer[1].buf += 64;
- offset += 64;
- }
-
- adv7511->current_edid_segment = block / 2;
- }
-
- if (block % 2 == 0)
- memcpy(buf, adv7511->edid_buf, len);
- else
- memcpy(buf, adv7511->edid_buf + 128, len);
-
- return 0;
-}
-
-/* -----------------------------------------------------------------------------
- * ADV75xx helpers
- */
-static int adv7511_get_modes(struct adv7511 *adv7511,
- struct drm_connector *connector)
-{
- struct edid *edid;
- unsigned int count;
-
- /* Reading the EDID only works if the device is powered */
- if (!adv7511->powered) {
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
- ADV7511_REG_POWER2_HDP_SRC_MASK, 0x40);
- regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
- ADV7511_INT0_EDID_READY);
- regmap_write(adv7511->regmap, ADV7511_REG_INT(1),
- ADV7511_INT1_DDC_ERROR);
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
- ADV7511_POWER_POWER_DOWN, 0);
- adv7511->current_edid_segment = -1;
- }
-
- edid = drm_do_get_edid(connector, adv7511_get_edid_block, adv7511);
-
- if (!adv7511->powered)
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
- ADV7511_POWER_POWER_DOWN,
- ADV7511_POWER_POWER_DOWN);
-
- kfree(adv7511->edid);
- adv7511->edid = edid;
- if (!edid)
- return 0;
-
- drm_mode_connector_update_edid_property(connector, edid);
- count = drm_add_edid_modes(connector, edid);
-
- adv7511_set_config_csc(adv7511, connector, adv7511->rgb);
-
- return count;
-}
-
-static enum drm_connector_status
-adv7511_detect(struct adv7511 *adv7511,
- struct drm_connector *connector)
-{
- enum drm_connector_status status;
- unsigned int val;
- bool hpd = true;
- int ret;
-
- ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val);
- if (ret < 0)
- return connector_status_disconnected;
-
-#ifndef FORCE_HPD
- if (val & ADV7511_STATUS_HPD)
-#endif
- status = connector_status_connected;
-#ifndef FORCE_HPD
- else
- status = connector_status_disconnected;
- hpd = adv7511_hpd(adv7511);
-#endif
-
- /* The chip resets itself when the cable is disconnected, so in case
- * there is a pending HPD interrupt and the cable is connected there was
- * at least one transition from disconnected to connected and the chip
- * has to be reinitialized. */
- if (status == connector_status_connected && hpd && adv7511->powered) {
- regcache_mark_dirty(adv7511->regmap);
- adv7511_power_on(adv7511);
- adv7511_get_modes(adv7511, connector);
- if (adv7511->status == connector_status_connected)
- status = connector_status_disconnected;
-#ifndef FORCE_HPD
- } else {
- /* Renable HDP sensing */
- regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
- ADV7511_REG_POWER2_HDP_SRC_MASK, 0);
-#endif
- }
-
- adv7511->status = status;
- return status;
-}
-
-static void adv7511_mode_set(struct adv7511 *adv7511,
- struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- static u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */
- unsigned int low_refresh_rate;
- unsigned int hsync_polarity = 0;
- unsigned int vsync_polarity = 0;
- int lanes = 3;
-
- regmap_write(adv7511->regmap, 0xd5, 1);
-
- if (adv7511->embedded_sync) {
- unsigned int hsync_offset, hsync_len;
- unsigned int vsync_offset, vsync_len;
-
- hsync_offset = adj_mode->crtc_hsync_start -
- adj_mode->crtc_hdisplay;
- vsync_offset = adj_mode->crtc_vsync_start -
- adj_mode->crtc_vdisplay;
- hsync_len = adj_mode->crtc_hsync_end -
- adj_mode->crtc_hsync_start;
- vsync_len = adj_mode->crtc_vsync_end -
- adj_mode->crtc_vsync_start;
-
- /* The hardware vsync generator has a off-by-one bug */
- vsync_offset += 1;
-
- regmap_write(adv7511->regmap, ADV7511_REG_HSYNC_PLACEMENT_MSB,
- ((hsync_offset >> 10) & 0x7) << 5);
- regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(0),
- (hsync_offset >> 2) & 0xff);
- regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(1),
- ((hsync_offset & 0x3) << 6) |
- ((hsync_len >> 4) & 0x3f));
- regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(2),
- ((hsync_len & 0xf) << 4) |
- ((vsync_offset >> 6) & 0xf));
- regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(3),
- ((vsync_offset & 0x3f) << 2) |
- ((vsync_len >> 8) & 0x3));
- regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(4),
- vsync_len & 0xff);
-
- hsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PHSYNC);
- vsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PVSYNC);
- } else {
- enum adv7511_sync_polarity mode_hsync_polarity;
- enum adv7511_sync_polarity mode_vsync_polarity;
-
- /**
- * If the input signal is always low or always high we want to
- * invert or let it passthrough depending on the polarity of the
- * current mode.
- **/
- if (adj_mode->flags & DRM_MODE_FLAG_NHSYNC)
- mode_hsync_polarity = ADV7511_SYNC_POLARITY_LOW;
- else
- mode_hsync_polarity = ADV7511_SYNC_POLARITY_HIGH;
-
- if (adj_mode->flags & DRM_MODE_FLAG_NVSYNC)
- mode_vsync_polarity = ADV7511_SYNC_POLARITY_LOW;
- else
- mode_vsync_polarity = ADV7511_SYNC_POLARITY_HIGH;
-
- if (adv7511->hsync_polarity != mode_hsync_polarity &&
- adv7511->hsync_polarity !=
- ADV7511_SYNC_POLARITY_PASSTHROUGH)
- hsync_polarity = 1;
-
- if (adv7511->vsync_polarity != mode_vsync_polarity &&
- adv7511->vsync_polarity !=
- ADV7511_SYNC_POLARITY_PASSTHROUGH)
- vsync_polarity = 1;
- }
-
- if (!adv7511->num_dsi_lanes) {
- /* if not fixed in dts, we decide it dynamically */
- if (adj_mode->clock > 115000)
- lanes = 4;
- regmap_write(adv7511->regmap_cec, 0x1C, lanes << 4);
- regmap_write(adv7511->regmap_cec, 0x16,
- clock_div_by_lanes[lanes - 2] << 3);
- }
-
- if (mode->vrefresh <= 24000)
- low_refresh_rate = ADV7511_LOW_REFRESH_RATE_24HZ;
- else if (mode->vrefresh <= 25000)
- low_refresh_rate = ADV7511_LOW_REFRESH_RATE_25HZ;
- else if (mode->vrefresh <= 30000)
- low_refresh_rate = ADV7511_LOW_REFRESH_RATE_30HZ;
- else
- low_refresh_rate = ADV7511_LOW_REFRESH_RATE_NONE;
-
- regmap_update_bits(adv7511->regmap, 0xfb,
- 0x6, low_refresh_rate << 1);
- regmap_update_bits(adv7511->regmap, 0x17,
- 0x60, (vsync_polarity << 6) | (hsync_polarity << 5));
-
- adv7511->curr_mode = adj_mode;
- /*
- * TODO Test first order 4:2:2 to 4:4:4 up conversion method, which is
- * supposed to give better results.
- */
-
- adv7511->f_tmds = mode->clock;
-
- regmap_update_bits(adv7511->regmap, 0xaf, BIT(1), BIT(1) * (
- (mode->hdisplay == 1920 && mode->vdisplay == 1080) ||
- (mode->hdisplay == 1280 && mode->vdisplay == 720) ||
- (mode->hdisplay == 1280 && mode->vdisplay == 576) ||
- (mode->hdisplay == 720 && mode->vdisplay == 576) ||
- (mode->hdisplay == 720 && mode->vdisplay == 480)
- ));
-}
-
-#ifdef CONFIG_DRM_I2C_ADV7511_SLAVE_ENCODER
-/* -----------------------------------------------------------------------------
- * Encoder i2c slave functions
- */
-
-static struct adv7511 *encoder_to_adv7511(struct drm_encoder *encoder)
-{
- return to_encoder_slave(encoder)->slave_priv;
-}
-
-static int adv7511_encoder_get_modes(struct drm_encoder *encoder,
- struct drm_connector *connector)
-{
- struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
-
- return adv7511_get_modes(adv7511, connector);
-}
-
-static void adv7511_encoder_dpms(struct drm_encoder *encoder, int mode)
-{
- struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
-
- if (mode == DRM_MODE_DPMS_ON)
- adv7511_power_on(adv7511);
- else
- adv7511_power_off(adv7511);
-}
-
-static enum drm_connector_status
-adv7511_encoder_detect(struct drm_encoder *encoder,
- struct drm_connector *connector)
-{
- struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
-
- return adv7511_detect(adv7511, connector);
-}
-
-static int adv7511_encoder_mode_valid(struct drm_encoder *encoder,
- struct drm_display_mode *mode)
-{
- if (mode->clock > 165000)
- return MODE_CLOCK_HIGH;
-
- return MODE_OK;
-}
-
-static void adv7511_encoder_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- struct adv7511 *adv7511 = encoder_to_adv7511(encoder);
-
- adv7511_mode_set(adv7511, mode, adj_mode);
-}
-
-static struct drm_encoder_slave_funcs adv7511_encoder_funcs = {
- .dpms = adv7511_encoder_dpms,
- .mode_valid = adv7511_encoder_mode_valid,
- .mode_set = adv7511_encoder_mode_set,
- .detect = adv7511_encoder_detect,
- .get_modes = adv7511_encoder_get_modes,
-};
-#else
-/* -----------------------------------------------------------------------------
- * Bridge and connector functions
- */
-
-static struct adv7511 *connector_to_adv7511(struct drm_connector *connector)
-{
- return container_of(connector, struct adv7511, connector);
-}
-
-/* connector helper functions */
-static int adv7511_connector_get_modes(struct drm_connector *connector)
-{
- struct adv7511 *adv7511 = connector_to_adv7511(connector);
-
- return adv7511_get_modes(adv7511, connector);
-}
-
-static struct drm_encoder *adv7511_connector_best_encoder(struct drm_connector *connector)
-{
- struct adv7511 *adv7511 = connector_to_adv7511(connector);
-
- return adv7511->bridge.encoder;
-}
-
-static struct drm_connector_helper_funcs adv7511_connector_helper_funcs = {
- .get_modes = adv7511_connector_get_modes,
- .best_encoder = adv7511_connector_best_encoder,
-};
-
-static enum drm_connector_status
-adv7511_connector_detect(struct drm_connector *connector, bool force)
-{
- struct adv7511 *adv7511 = connector_to_adv7511(connector);
-
- return adv7511_detect(adv7511, connector);
-}
-
-static struct drm_connector_funcs adv7511_connector_funcs = {
- .dpms = drm_helper_connector_dpms,
- .fill_modes = drm_helper_probe_single_connector_modes,
- .detect = adv7511_connector_detect,
- .destroy = drm_connector_cleanup,
- .reset = drm_atomic_helper_connector_reset,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-/* bridge funcs */
-static struct adv7511 *bridge_to_adv7511(struct drm_bridge *bridge)
-{
- return container_of(bridge, struct adv7511, bridge);
-}
-
-static void adv7511_bridge_pre_enable(struct drm_bridge *bridge)
-{
- struct adv7511 *adv7511 = bridge_to_adv7511(bridge);
-
- adv7511_power_on(adv7511);
-}
-
-static void adv7511_bridge_post_disable(struct drm_bridge *bridge)
-{
- struct adv7511 *adv7511 = bridge_to_adv7511(bridge);
-
- adv7511_power_off(adv7511);
-}
-
-static void adv7511_bridge_enable(struct drm_bridge *bridge)
-{
-}
-
-static void adv7511_bridge_disable(struct drm_bridge *bridge)
-{
-}
-
-static void adv7511_bridge_mode_set(struct drm_bridge *bridge,
- struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- struct adv7511 *adv7511 = bridge_to_adv7511(bridge);
-
- adv7511_mode_set(adv7511, mode, adj_mode);
-}
-
-static int adv7511_bridge_attach(struct drm_bridge *bridge)
-{
- struct adv7511 *adv7511 = bridge_to_adv7511(bridge);
- int ret;
-
- adv7511->encoder = bridge->encoder;
-
- if (!bridge->encoder) {
- DRM_ERROR("Parent encoder object not found");
- return -ENODEV;
- }
-
- adv7511->connector.polled = DRM_CONNECTOR_POLL_HPD;
- ret = drm_connector_init(bridge->dev, &adv7511->connector,
- &adv7511_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
- if (ret) {
- DRM_ERROR("Failed to initialize connector with drm\n");
- return ret;
- }
- drm_connector_helper_add(&adv7511->connector,
- &adv7511_connector_helper_funcs);
- drm_connector_register(&adv7511->connector);
- drm_mode_connector_attach_encoder(&adv7511->connector, adv7511->encoder);
-
- drm_helper_hpd_irq_event(adv7511->connector.dev);
-
- return ret;
-}
-
-static struct drm_bridge_funcs adv7511_bridge_funcs = {
- .pre_enable = adv7511_bridge_pre_enable,
- .enable = adv7511_bridge_enable,
- .disable = adv7511_bridge_disable,
- .post_disable = adv7511_bridge_post_disable,
- .attach = adv7511_bridge_attach,
- .mode_set = adv7511_bridge_mode_set,
-};
-#endif
-
-/* -----------------------------------------------------------------------------
- * Probe & remove
- */
-
-static int adv7511_parse_dt(struct adv7511 *adv7511, struct device_node *np,
- struct adv7511_link_config *config)
-{
- const char *str;
- int ret;
-
- of_property_read_u32(np, "adi,input-depth", &config->input_color_depth);
- if (config->input_color_depth != 8 && config->input_color_depth != 10 &&
- config->input_color_depth != 12)
- return -EINVAL;
-
- ret = of_property_read_string(np, "adi,input-colorspace", &str);
- if (ret < 0)
- return ret;
-
- if (!strcmp(str, "rgb"))
- config->input_colorspace = HDMI_COLORSPACE_RGB;
- else if (!strcmp(str, "yuv422"))
- config->input_colorspace = HDMI_COLORSPACE_YUV422;
- else if (!strcmp(str, "yuv444"))
- config->input_colorspace = HDMI_COLORSPACE_YUV444;
- else
- return -EINVAL;
-
- if (adv7511->type == ADV7533) {
- /*
- * Optional... leaving it out uses a heuristic to determine
- * dynamically
- */
- if (!of_property_read_u32(np, "adi,dsi-lanes",
- &config->num_dsi_lanes))
- if (config->num_dsi_lanes < 1 ||
- config->num_dsi_lanes > 4)
- return -EINVAL;
-
- return 0;
- }
-
- ret = of_property_read_string(np, "adi,input-clock", &str);
- if (ret < 0)
- return ret;
-
- if (!strcmp(str, "1x"))
- config->input_clock = ADV7511_INPUT_CLOCK_1X;
- else if (!strcmp(str, "2x"))
- config->input_clock = ADV7511_INPUT_CLOCK_2X;
- else if (!strcmp(str, "ddr"))
- config->input_clock = ADV7511_INPUT_CLOCK_DDR;
- else
- return -EINVAL;
-
- if (config->input_colorspace == HDMI_COLORSPACE_YUV422 ||
- config->input_clock != ADV7511_INPUT_CLOCK_1X) {
- ret = of_property_read_u32(np, "adi,input-style",
- &config->input_style);
- if (ret)
- return ret;
-
- if (config->input_style < 1 || config->input_style > 3)
- return -EINVAL;
-
- ret = of_property_read_string(np, "adi,input-justification",
- &str);
- if (ret < 0)
- return ret;
-
- if (!strcmp(str, "left"))
- config->input_justification =
- ADV7511_INPUT_JUSTIFICATION_LEFT;
- else if (!strcmp(str, "evenly"))
- config->input_justification =
- ADV7511_INPUT_JUSTIFICATION_EVENLY;
- else if (!strcmp(str, "right"))
- config->input_justification =
- ADV7511_INPUT_JUSTIFICATION_RIGHT;
- else
- return -EINVAL;
-
- } else {
- config->input_style = 1;
- config->input_justification = ADV7511_INPUT_JUSTIFICATION_LEFT;
- }
-
- of_property_read_u32(np, "adi,clock-delay", &config->clock_delay);
- if (config->clock_delay < -1200 || config->clock_delay > 1600)
- return -EINVAL;
-
- config->embedded_sync = of_property_read_bool(np, "adi,embedded-sync");
-
- /* Hardcode the sync pulse configurations for now. */
- config->sync_pulse = ADV7511_INPUT_SYNC_PULSE_NONE;
- config->vsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH;
- config->hsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH;
-
- return 0;
-}
-
-static const int edid_i2c_addr = 0x7e;
-static const int packet_i2c_addr = 0x70;
-static const int cec_i2c_addr = 0x78;
-static const int main_i2c_addr = 0x72;
-
-static const struct of_device_id adv7511_of_ids[] = {
- { .compatible = "adi,adv7511", .data = (void *)ADV7511 },
- { .compatible = "adi,adv7511w", .data = (void *)ADV7511 },
- { .compatible = "adi,adv7513", .data= (void *)ADV7511 },
- { .compatible = "adi,adv7533", .data = (void *)ADV7533 },
- { }
-};
-MODULE_DEVICE_TABLE(of, adv7511_of_ids);
-
-#ifdef CONFIG_DRM_I2C_ADV7511_SLAVE_ENCODER
-static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
-{
- struct adv7511_link_config link_config;
- struct adv7511 *adv7511;
- struct device *dev = &i2c->dev;
- unsigned int val;
- int ret;
-
- if (!dev->of_node)
- return -EINVAL;
-
- adv7511 = devm_kzalloc(dev, sizeof(*adv7511), GFP_KERNEL);
- if (!adv7511)
- return -ENOMEM;
-
- adv7511->powered = false;
- adv7511->status = connector_status_disconnected;
-
- if (dev->of_node) {
- const struct of_device_id *of_id;
- of_id = of_match_node(adv7511_of_ids, dev->of_node);
- adv7511->type = (unsigned long)of_id->data;
- } else {
- adv7511->type = id->driver_data;
- }
-
- memset(&link_config, 0, sizeof(link_config));
-
- ret = adv7511_parse_dt(adv7511, dev->of_node, &link_config);
- if (ret)
- return ret;
-
- /*
- * The power down GPIO is optional. If present, toggle it from active to
- * inactive to wake up the encoder.
- */
- adv7511->gpio_pd = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_HIGH);
- if (IS_ERR(adv7511->gpio_pd))
- return PTR_ERR(adv7511->gpio_pd);
-
- if (adv7511->gpio_pd) {
- mdelay(5);
- gpiod_set_value_cansleep(adv7511->gpio_pd, 0);
- }
-
- adv7511->regmap = devm_regmap_init_i2c(i2c, &adv7511_regmap_config);
- if (IS_ERR(adv7511->regmap))
- return PTR_ERR(adv7511->regmap);
-
- ret = regmap_read(adv7511->regmap, ADV7511_REG_CHIP_REVISION, &val);
- if (ret)
- return ret;
- dev_dbg(dev, "Rev. %d\n", val);
-
- if (adv7511->type == ADV7511) {
- ret = regmap_register_patch(adv7511->regmap, adv7511_fixed_registers,
- ARRAY_SIZE(adv7511_fixed_registers));
- if (ret)
- return ret;
- } else {
- ret = regmap_register_patch(adv7511->regmap, adv7533_fixed_registers,
- ARRAY_SIZE(adv7533_fixed_registers));
- if (ret)
- return ret;
- }
-
- regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, edid_i2c_addr);
- regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR,
- packet_i2c_addr);
- regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR, cec_i2c_addr);
- adv7511_packet_disable(adv7511, 0xffff);
-
- adv7511->i2c_main = i2c;
- adv7511->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1);
- if (!adv7511->i2c_edid)
- return -ENOMEM;
-
- adv7511->i2c_cec = i2c_new_dummy(i2c->adapter, cec_i2c_addr >> 1);
- if (!adv7511->i2c_cec) {
- ret = -ENOMEM;
- goto err_i2c_unregister_edid;
- }
-
- adv7511->regmap_cec = devm_regmap_init_i2c(adv7511->i2c_cec,
- &adv7533_cec_regmap_config);
- if (IS_ERR(adv7511->regmap_cec)) {
- ret = PTR_ERR(adv7511->regmap_cec);
- goto err_i2c_unregister_cec;
- }
-
- if (adv7511->type == ADV7533) {
- ret = regmap_register_patch(adv7511->regmap_cec, adv7533_cec_fixed_registers,
- ARRAY_SIZE(adv7533_cec_fixed_registers));
- if (ret)
- return ret;
- }
-
- if (i2c->irq) {
- init_waitqueue_head(&adv7511->wq);
-
- ret = devm_request_threaded_irq(dev, i2c->irq, NULL,
- adv7511_irq_handler,
- IRQF_ONESHOT, dev_name(dev),
- adv7511);
- if (ret)
- goto err_i2c_unregister_cec;
-
- adv7511->irq = i2c->irq;
- }
-
- /* CEC is unused for now */
- regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
- ADV7511_CEC_CTRL_POWER_DOWN);
-
- adv7511_power_off(adv7511);
-
- i2c_set_clientdata(i2c, adv7511);
-
-// adv7511_audio_init(dev);
-
- adv7511_set_link_config(adv7511, &link_config);
-
- return 0;
-
-err_i2c_unregister_cec:
- i2c_unregister_device(adv7511->i2c_cec);
-err_i2c_unregister_edid:
- i2c_unregister_device(adv7511->i2c_edid);
-
- return ret;
-}
-
-static int adv7511_remove(struct i2c_client *i2c)
-{
- struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
-
-// adv7511_audio_exit(&i2c->dev);
- i2c_unregister_device(adv7511->i2c_cec);
- i2c_unregister_device(adv7511->i2c_edid);
-
- kfree(adv7511->edid);
-
- return 0;
-}
-
-static const struct i2c_device_id adv7511_i2c_ids[] = {
- { "adv7511", ADV7511 },
- { "adv7511w", ADV7511 },
- { "adv7513", ADV7511 },
- { "adv7533", ADV7533 },
- { }
-};
-MODULE_DEVICE_TABLE(i2c, adv7511_i2c_ids);
-
-static int adv7511_encoder_init(struct i2c_client *i2c, struct drm_device *dev,
- struct drm_encoder_slave *encoder)
-{
-
- struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
-
- encoder->slave_priv = adv7511;
- encoder->slave_funcs = &adv7511_encoder_funcs;
-
- adv7511->encoder = &encoder->base;
-
- return 0;
-}
-
-static struct drm_i2c_encoder_driver adv7511_driver = {
- .i2c_driver = {
- .driver = {
- .name = "adv7511",
- .of_match_table = adv7511_of_ids,
- },
- .id_table = adv7511_i2c_ids,
- .probe = adv7511_probe,
- .remove = adv7511_remove,
- },
-
- .encoder_init = adv7511_encoder_init,
-};
-
-static int __init adv7511_init(void)
-{
- return drm_i2c_encoder_register(THIS_MODULE, &adv7511_driver);
-}
-module_init(adv7511_init);
-
-static void __exit adv7511_exit(void)
-{
- drm_i2c_encoder_unregister(&adv7511_driver);
-}
-module_exit(adv7511_exit);
-#else
-
-static int adv7533_probe(struct mipi_dsi_device *dsi)
-{
- struct device *dev = &dsi->dev;
- struct adv7511 *adv;
- struct adv7511_link_config link_config;
- struct i2c_adapter *adapter;
- struct device_node *adapter_node;
- unsigned int val;
- int irq;
- int ret;
-
- adv = devm_kzalloc(dev, sizeof(struct adv7511), GFP_KERNEL);
- if (!adv)
- return -ENOMEM;
-
- mipi_dsi_set_drvdata(dsi, adv);
-
- dsi->lanes = 4;
- dsi->format = MIPI_DSI_FMT_RGB888;
- dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE
- | MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
-
- adv->type = ADV7533;
- adv->powered = false;
- adv->status = connector_status_disconnected;
-
- memset(&link_config, 0, sizeof(link_config));
-
- ret = adv7511_parse_dt(adv, dev->of_node, &link_config);
- if (ret)
- return ret;
-
- adv->gpio_pd = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_HIGH);
- if (IS_ERR(adv->gpio_pd))
- return PTR_ERR(adv->gpio_pd);
-
- if (adv->gpio_pd) {
- mdelay(5);
- gpiod_set_value_cansleep(adv->gpio_pd, 0);
- }
-
- adapter_node = of_parse_phandle(dev->of_node, "i2c-bus", 0);
- if (adapter_node) {
- adapter = of_find_i2c_adapter_by_node(adapter_node);
- if (adapter == NULL)
- return -ENODEV;
- } else {
- return -ENODEV;
- }
-
- adv->i2c_main = i2c_new_dummy(adapter, main_i2c_addr >> 1);
- if (!adv->i2c_main)
- return -ENOMEM;
-
- adv->regmap = devm_regmap_init_i2c(adv->i2c_main, &adv7511_regmap_config);
- if (IS_ERR(adv->regmap))
- return PTR_ERR(adv->regmap);
-
- ret = regmap_read(adv->regmap, ADV7511_REG_CHIP_REVISION, &val);
- if (ret)
- return ret;
-
- dev_dbg(dev, "Rev. %d\n", val);
-
- ret = regmap_register_patch(adv->regmap, adv7533_fixed_registers,
- ARRAY_SIZE(adv7533_fixed_registers));
- if (ret)
- return ret;
-
- regmap_write(adv->regmap, ADV7511_REG_EDID_I2C_ADDR, edid_i2c_addr);
- regmap_write(adv->regmap, ADV7511_REG_PACKET_I2C_ADDR,
- packet_i2c_addr);
- regmap_write(adv->regmap, ADV7511_REG_CEC_I2C_ADDR, cec_i2c_addr);
- adv7511_packet_disable(adv, 0xffff);
-
- adv->i2c_edid = i2c_new_dummy(adapter, edid_i2c_addr >> 1);
- if (!adv->i2c_edid) {
- ret = -ENOMEM;
- goto err_i2c_unregister_main;
- }
-
- adv->i2c_cec = i2c_new_dummy(adapter, cec_i2c_addr >> 1);
- if (!adv->i2c_cec) {
- ret = -ENOMEM;
- goto err_i2c_unregister_edid;
- }
-
- adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
- &adv7533_cec_regmap_config);
- if (IS_ERR(adv->regmap_cec)) {
- ret = PTR_ERR(adv->regmap_cec);
- goto err_i2c_unregister_cec;
- }
-
- ret = regmap_register_patch(adv->regmap_cec,
- adv7533_cec_fixed_registers,
- ARRAY_SIZE(adv7533_cec_fixed_registers));
- if (ret) {
- goto err_i2c_unregister_cec;
- }
-
- irq = irq_of_parse_and_map(dev->of_node, 0);
- if (irq) {
- init_waitqueue_head(&adv->wq);
-
- ret = devm_request_threaded_irq(dev, irq, NULL,
- adv7511_irq_handler,
- IRQF_ONESHOT, dev_name(dev),
- adv);
- if (ret)
- goto err_i2c_unregister_cec;
-
- adv->irq = irq;
- }
-
- /* CEC is unused for now */
- regmap_write(adv->regmap, ADV7511_REG_CEC_CTRL,
- ADV7511_CEC_CTRL_POWER_DOWN);
-
- adv7511_power_off(adv);
-
-// adv7511_audio_init(dev);
-
- adv7511_set_link_config(adv, &link_config);
-
- adv->bridge.funcs = &adv7511_bridge_funcs;
- adv->bridge.of_node = dev->of_node;
-
- ret = drm_bridge_add(&adv->bridge);
- if (ret) {
- DRM_ERROR("Failed to add adv7533 bridge\n");
- return ret;
- }
-
- ret = mipi_dsi_attach(dsi);
- if (ret < 0)
- goto err_bridge_remove;
-
- return 0;
-
-err_bridge_remove:
- drm_bridge_remove(&adv->bridge);
-err_i2c_unregister_cec:
- i2c_unregister_device(adv->i2c_cec);
-err_i2c_unregister_edid:
- i2c_unregister_device(adv->i2c_edid);
-err_i2c_unregister_main:
- i2c_unregister_device(adv->i2c_main);
-
- return ret;
-}
-
-static int adv7533_remove(struct mipi_dsi_device *dsi)
-{
- struct adv7511 *adv = mipi_dsi_get_drvdata(dsi);
-
-// adv7511_audio_exit(&dsi->dev);
-
- i2c_unregister_device(adv->i2c_main);
- i2c_unregister_device(adv->i2c_cec);
- i2c_unregister_device(adv->i2c_edid);
-
- mipi_dsi_detach(dsi);
- drm_bridge_remove(&adv->bridge);
- kfree(adv->edid);
-
- return 0;
-}
-
-static struct of_device_id adv7533_of_match[] = {
- { .compatible = "adi,adv7533" },
- { }
-};
-MODULE_DEVICE_TABLE(of, adv7533_of_match);
-
-static struct mipi_dsi_driver adv7533_driver = {
- .probe = adv7533_probe,
- .remove = adv7533_remove,
- .driver = {
- .name = "adv7533",
- .of_match_table = adv7533_of_match,
- },
-};
-module_mipi_dsi_driver(adv7533_driver);
-#endif
-
-MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("ADV7511 HDMI transmitter driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/i2c/adv7511.h b/drivers/gpu/drm/i2c/adv7511.h
deleted file mode 100644
index 26c9045f6b46..000000000000
--- a/drivers/gpu/drm/i2c/adv7511.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Analog Devices ADV7511 HDMI transmitter driver
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef __DRM_I2C_ADV7511_H__
-#define __DRM_I2C_ADV7511_H__
-
-#include <linux/hdmi.h>
-#include <drm/drm_crtc_helper.h>
-
-struct regmap;
-struct adv7511;
-
-int adv7511_packet_enable(struct adv7511 *adv7511, unsigned int packet);
-int adv7511_packet_disable(struct adv7511 *adv7511, unsigned int packet);
-
-int adv7511_audio_init(struct device *dev);
-void adv7511_audio_exit(struct device *dev);
-
-#define ADV7511_REG_CHIP_REVISION 0x00
-#define ADV7511_REG_N0 0x01
-#define ADV7511_REG_N1 0x02
-#define ADV7511_REG_N2 0x03
-#define ADV7511_REG_SPDIF_FREQ 0x04
-#define ADV7511_REG_CTS_AUTOMATIC1 0x05
-#define ADV7511_REG_CTS_AUTOMATIC2 0x06
-#define ADV7511_REG_CTS_MANUAL0 0x07
-#define ADV7511_REG_CTS_MANUAL1 0x08
-#define ADV7511_REG_CTS_MANUAL2 0x09
-#define ADV7511_REG_AUDIO_SOURCE 0x0a
-#define ADV7511_REG_AUDIO_CONFIG 0x0b
-#define ADV7511_REG_I2S_CONFIG 0x0c
-#define ADV7511_REG_I2S_WIDTH 0x0d
-#define ADV7511_REG_AUDIO_SUB_SRC0 0x0e
-#define ADV7511_REG_AUDIO_SUB_SRC1 0x0f
-#define ADV7511_REG_AUDIO_SUB_SRC2 0x10
-#define ADV7511_REG_AUDIO_SUB_SRC3 0x11
-#define ADV7511_REG_AUDIO_CFG1 0x12
-#define ADV7511_REG_AUDIO_CFG2 0x13
-#define ADV7511_REG_AUDIO_CFG3 0x14
-#define ADV7511_REG_I2C_FREQ_ID_CFG 0x15
-#define ADV7511_REG_VIDEO_INPUT_CFG1 0x16
-#define ADV7511_REG_CSC_UPPER(x) (0x18 + (x) * 2)
-#define ADV7511_REG_CSC_LOWER(x) (0x19 + (x) * 2)
-#define ADV7511_REG_SYNC_DECODER(x) (0x30 + (x))
-#define ADV7511_REG_DE_GENERATOR (0x35 + (x))
-#define ADV7511_REG_PIXEL_REPETITION 0x3b
-#define ADV7511_REG_VIC_MANUAL 0x3c
-#define ADV7511_REG_VIC_SEND 0x3d
-#define ADV7511_REG_VIC_DETECTED 0x3e
-#define ADV7511_REG_AUX_VIC_DETECTED 0x3f
-#define ADV7511_REG_PACKET_ENABLE0 0x40
-#define ADV7511_REG_POWER 0x41
-#define ADV7511_REG_STATUS 0x42
-#define ADV7511_REG_EDID_I2C_ADDR 0x43
-#define ADV7511_REG_PACKET_ENABLE1 0x44
-#define ADV7511_REG_PACKET_I2C_ADDR 0x45
-#define ADV7511_REG_DSD_ENABLE 0x46
-#define ADV7511_REG_VIDEO_INPUT_CFG2 0x48
-#define ADV7511_REG_INFOFRAME_UPDATE 0x4a
-#define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
-#define ADV7511_REG_AVI_INFOFRAME_VERSION 0x52
-#define ADV7511_REG_AVI_INFOFRAME_LENGTH 0x53
-#define ADV7511_REG_AVI_INFOFRAME_CHECKSUM 0x54
-#define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
-#define ADV7511_REG_AUDIO_INFOFRAME_VERSION 0x70
-#define ADV7511_REG_AUDIO_INFOFRAME_LENGTH 0x71
-#define ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM 0x72
-#define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
-#define ADV7511_REG_INT_ENABLE(x) (0x94 + (x))
-#define ADV7511_REG_INT(x) (0x96 + (x))
-#define ADV7511_REG_INPUT_CLK_DIV 0x9d
-#define ADV7511_REG_PLL_STATUS 0x9e
-#define ADV7511_REG_HDMI_POWER 0xa1
-#define ADV7511_REG_HDCP_HDMI_CFG 0xaf
-#define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
-#define ADV7511_REG_HDCP_STATUS 0xb8
-#define ADV7511_REG_BCAPS 0xbe
-#define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
-#define ADV7511_REG_EDID_SEGMENT 0xc4
-#define ADV7511_REG_DDC_STATUS 0xc8
-#define ADV7511_REG_EDID_READ_CTRL 0xc9
-#define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
-#define ADV7511_REG_TIMING_GEN_SEQ 0xd0
-#define ADV7511_REG_POWER2 0xd6
-#define ADV7511_REG_HSYNC_PLACEMENT_MSB 0xfa
-
-#define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
-#define ADV7511_REG_TMDS_CLOCK_INV 0xde
-#define ADV7511_REG_ARC_CTRL 0xdf
-#define ADV7511_REG_CEC_I2C_ADDR 0xe1
-#define ADV7511_REG_CEC_CTRL 0xe2
-#define ADV7511_REG_CHIP_ID_HIGH 0xf5
-#define ADV7511_REG_CHIP_ID_LOW 0xf6
-
-#define ADV7511_CSC_ENABLE BIT(7)
-#define ADV7511_CSC_UPDATE_MODE BIT(5)
-
-#define ADV7511_INT0_HDP BIT(7)
-#define ADV7511_INT0_VSYNC BIT(5)
-#define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
-#define ADV7511_INT0_EDID_READY BIT(2)
-#define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1)
-
-#define ADV7511_INT1_DDC_ERROR BIT(7)
-#define ADV7511_INT1_BKSV BIT(6)
-#define ADV7511_INT1_CEC_TX_READY BIT(5)
-#define ADV7511_INT1_CEC_TX_ARBIT_LOST BIT(4)
-#define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT BIT(3)
-#define ADV7511_INT1_CEC_RX_READY3 BIT(2)
-#define ADV7511_INT1_CEC_RX_READY2 BIT(1)
-#define ADV7511_INT1_CEC_RX_READY1 BIT(0)
-
-#define ADV7511_ARC_CTRL_POWER_DOWN BIT(0)
-
-#define ADV7511_CEC_CTRL_POWER_DOWN BIT(0)
-
-#define ADV7511_POWER_POWER_DOWN BIT(6)
-
-#define ADV7511_HDMI_CFG_MODE_MASK 0x2
-#define ADV7511_HDMI_CFG_MODE_DVI 0x0
-#define ADV7511_HDMI_CFG_MODE_HDMI 0x2
-
-#define ADV7511_AUDIO_SELECT_I2C 0x0
-#define ADV7511_AUDIO_SELECT_SPDIF 0x1
-#define ADV7511_AUDIO_SELECT_DSD 0x2
-#define ADV7511_AUDIO_SELECT_HBR 0x3
-#define ADV7511_AUDIO_SELECT_DST 0x4
-
-#define ADV7511_I2S_SAMPLE_LEN_16 0x2
-#define ADV7511_I2S_SAMPLE_LEN_20 0x3
-#define ADV7511_I2S_SAMPLE_LEN_18 0x4
-#define ADV7511_I2S_SAMPLE_LEN_22 0x5
-#define ADV7511_I2S_SAMPLE_LEN_19 0x8
-#define ADV7511_I2S_SAMPLE_LEN_23 0x9
-#define ADV7511_I2S_SAMPLE_LEN_24 0xb
-#define ADV7511_I2S_SAMPLE_LEN_17 0xc
-#define ADV7511_I2S_SAMPLE_LEN_21 0xd
-
-#define ADV7511_SAMPLE_FREQ_44100 0x0
-#define ADV7511_SAMPLE_FREQ_48000 0x2
-#define ADV7511_SAMPLE_FREQ_32000 0x3
-#define ADV7511_SAMPLE_FREQ_88200 0x8
-#define ADV7511_SAMPLE_FREQ_96000 0xa
-#define ADV7511_SAMPLE_FREQ_176400 0xc
-#define ADV7511_SAMPLE_FREQ_192000 0xe
-
-#define ADV7511_STATUS_POWER_DOWN_POLARITY BIT(7)
-#define ADV7511_STATUS_HPD BIT(6)
-#define ADV7511_STATUS_MONITOR_SENSE BIT(5)
-#define ADV7511_STATUS_I2S_32BIT_MODE BIT(3)
-
-#define ADV7511_PACKET_ENABLE_N_CTS BIT(8+6)
-#define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5)
-#define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)
-#define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3)
-#define ADV7511_PACKET_ENABLE_GC BIT(7)
-#define ADV7511_PACKET_ENABLE_SPD BIT(6)
-#define ADV7511_PACKET_ENABLE_MPEG BIT(5)
-#define ADV7511_PACKET_ENABLE_ACP BIT(4)
-#define ADV7511_PACKET_ENABLE_ISRC BIT(3)
-#define ADV7511_PACKET_ENABLE_GM BIT(2)
-#define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)
-#define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)
-
-#define ADV7511_REG_POWER2_HDP_SRC_MASK 0xc0
-#define ADV7511_REG_POWER2_HDP_SRC_BOTH 0x00
-#define ADV7511_REG_POWER2_HDP_SRC_HDP 0x40
-#define ADV7511_REG_POWER2_HDP_SRC_CEC 0x80
-#define ADV7511_REG_POWER2_HDP_SRC_NONE 0xc0
-#define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)
-#define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)
-
-#define ADV7511_LOW_REFRESH_RATE_NONE 0x0
-#define ADV7511_LOW_REFRESH_RATE_24HZ 0x1
-#define ADV7511_LOW_REFRESH_RATE_25HZ 0x2
-#define ADV7511_LOW_REFRESH_RATE_30HZ 0x3
-
-#define ADV7511_AUDIO_CFG3_LEN_MASK 0x0f
-#define ADV7511_I2C_FREQ_ID_CFG_RATE_MASK 0xf0
-
-#define ADV7511_AUDIO_SOURCE_I2S 0
-#define ADV7511_AUDIO_SOURCE_SPDIF 1
-
-#define ADV7511_I2S_FORMAT_I2S 0
-#define ADV7511_I2S_FORMAT_RIGHT_J 1
-#define ADV7511_I2S_FORMAT_LEFT_J 2
-
-#define ADV7511_PACKET(p, x) ((p) * 0x20 + (x))
-#define ADV7511_PACKET_SDP(x) ADV7511_PACKET(0, x)
-#define ADV7511_PACKET_MPEG(x) ADV7511_PACKET(1, x)
-#define ADV7511_PACKET_ACP(x) ADV7511_PACKET(2, x)
-#define ADV7511_PACKET_ISRC1(x) ADV7511_PACKET(3, x)
-#define ADV7511_PACKET_ISRC2(x) ADV7511_PACKET(4, x)
-#define ADV7511_PACKET_GM(x) ADV7511_PACKET(5, x)
-#define ADV7511_PACKET_SPARE(x) ADV7511_PACKET(6, x)
-
-enum adv7511_input_clock {
- ADV7511_INPUT_CLOCK_1X,
- ADV7511_INPUT_CLOCK_2X,
- ADV7511_INPUT_CLOCK_DDR,
-};
-
-enum adv7511_input_justification {
- ADV7511_INPUT_JUSTIFICATION_EVENLY = 0,
- ADV7511_INPUT_JUSTIFICATION_RIGHT = 1,
- ADV7511_INPUT_JUSTIFICATION_LEFT = 2,
-};
-
-enum adv7511_input_sync_pulse {
- ADV7511_INPUT_SYNC_PULSE_DE = 0,
- ADV7511_INPUT_SYNC_PULSE_HSYNC = 1,
- ADV7511_INPUT_SYNC_PULSE_VSYNC = 2,
- ADV7511_INPUT_SYNC_PULSE_NONE = 3,
-};
-
-/**
- * enum adv7511_sync_polarity - Polarity for the input sync signals
- * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
- * the currently configured mode.
- * @ADV7511_SYNC_POLARITY_LOW: Sync polarity is low
- * @ADV7511_SYNC_POLARITY_HIGH: Sync polarity is high
- *
- * If the polarity is set to either LOW or HIGH the driver will configure the
- * ADV7511 to internally invert the sync signal if required to match the sync
- * polarity setting for the currently selected output mode.
- *
- * If the polarity is set to PASSTHROUGH, the ADV7511 will route the signal
- * unchanged. This is used when the upstream graphics core already generates
- * the sync signals with the correct polarity.
- */
-enum adv7511_sync_polarity {
- ADV7511_SYNC_POLARITY_PASSTHROUGH,
- ADV7511_SYNC_POLARITY_LOW,
- ADV7511_SYNC_POLARITY_HIGH,
-};
-
-enum adv7511_type {
- ADV7511,
- ADV7533,
-};
-
-struct adv7511 {
- struct i2c_client *i2c_main;
- struct i2c_client *i2c_edid;
- struct i2c_client *i2c_cec;
-
- int irq;
-
- struct regmap *regmap;
- struct regmap *regmap_cec;
- enum drm_connector_status status;
- bool powered;
-
- struct drm_display_mode *curr_mode;
-
- unsigned int f_tmds;
- unsigned int f_audio;
- unsigned int audio_source;
-
- unsigned int current_edid_segment;
- uint8_t edid_buf[256];
- bool edid_read;
- struct drm_encoder *encoder;
-
- wait_queue_head_t wq;
-
-#ifndef CONFIG_DRM_I2C_ADV7511_SLAVE_ENCODER
- struct drm_connector connector;
- struct drm_bridge bridge;
-#endif
-
- bool embedded_sync;
- enum adv7511_sync_polarity vsync_polarity;
- enum adv7511_sync_polarity hsync_polarity;
- bool rgb;
- u8 num_dsi_lanes;
-
- struct edid *edid;
-
- struct gpio_desc *gpio_pd;
-
- enum adv7511_type type;
-};
-
-/**
- * struct adv7511_link_config - Describes adv7511 hardware configuration
- * @input_color_depth: Number of bits per color component (8, 10 or 12)
- * @input_colorspace: The input colorspace (RGB, YUV444, YUV422)
- * @input_clock: The input video clock style (1x, 2x, DDR)
- * @input_style: The input component arrangement variant
- * @input_justification: Video input format bit justification
- * @clock_delay: Clock delay for the input clock (in ps)
- * @embedded_sync: Video input uses BT.656-style embedded sync
- * @sync_pulse: Select the sync pulse
- * @vsync_polarity: vsync input signal configuration
- * @hsync_polarity: hsync input signal configuration
- * @num_dsi_lanes: number of dsi lanes in use(for ADV7533)
- */
-struct adv7511_link_config {
- unsigned int input_color_depth;
- enum hdmi_colorspace input_colorspace;
- enum adv7511_input_clock input_clock;
- unsigned int input_style;
- enum adv7511_input_justification input_justification;
-
- int clock_delay;
-
- bool embedded_sync;
- enum adv7511_input_sync_pulse sync_pulse;
- enum adv7511_sync_polarity vsync_polarity;
- enum adv7511_sync_polarity hsync_polarity;
-
- unsigned int num_dsi_lanes;
-};
-
-/**
- * enum adv7511_csc_scaling - Scaling factor for the ADV7511 CSC
- * @ADV7511_CSC_SCALING_1: CSC results are not scaled
- * @ADV7511_CSC_SCALING_2: CSC results are scaled by a factor of two
- * @ADV7511_CSC_SCALING_4: CSC results are scalled by a factor of four
- */
-enum adv7511_csc_scaling {
- ADV7511_CSC_SCALING_1 = 0,
- ADV7511_CSC_SCALING_2 = 1,
- ADV7511_CSC_SCALING_4 = 2,
-};
-
-/**
- * struct adv7511_video_config - Describes adv7511 hardware configuration
- * @csc_enable: Whether to enable color space conversion
- * @csc_scaling_factor: Color space conversion scaling factor
- * @csc_coefficents: Color space conversion coefficents
- * @hdmi_mode: Whether to use HDMI or DVI output mode
- * @avi_infoframe: HDMI infoframe
- */
-struct adv7511_video_config {
- bool csc_enable;
- enum adv7511_csc_scaling csc_scaling_factor;
- const uint16_t *csc_coefficents;
-
- bool hdmi_mode;
- struct hdmi_avi_infoframe avi_infoframe;
-};
-
-#endif /* __DRM_I2C_ADV7511_H__ */
diff --git a/drivers/gpu/drm/i2c/adv7533.c b/drivers/gpu/drm/i2c/adv7533.c
new file mode 100644
index 000000000000..47888ee38943
--- /dev/null
+++ b/drivers/gpu/drm/i2c/adv7533.c
@@ -0,0 +1,734 @@
+/*
+ * Analog Devices ADV7533 HDMI transmitter driver
+ *
+ * Copyright 2012 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#include <linux/device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_encoder_slave.h>
+
+#include "adv7533.h"
+
+struct adv7533 {
+ struct i2c_client *i2c_main;
+ struct i2c_client *i2c_edid;
+ struct i2c_client *i2c_dsi;
+
+ struct regmap *regmap_main;
+ struct regmap *regmap_dsi;
+ int dpms_mode;
+
+ unsigned int current_edid_segment;
+ uint8_t edid_buf[256];
+
+ wait_queue_head_t wq;
+ struct delayed_work hotplug_work;
+ struct drm_encoder *encoder;
+
+ struct edid *edid;
+ struct gpio_desc *gpio_pd;
+
+};
+
+/* ADI recommended values for proper operation. */
+static const struct reg_default adv7533_fixed_registers[] = {
+ { 0x16, 0x20 },
+ { 0x9a, 0xe0 },
+ { 0xba, 0x70 },
+ { 0xde, 0x82 },
+ { 0xe4, 0x40 },
+ { 0xe5, 0x80 },
+};
+
+static const struct reg_default adv7533_dsi_fixed_registers[] = {
+ { 0x15, 0x10 },
+ { 0x17, 0xd0 },
+ { 0x24, 0x20 },
+ { 0x57, 0x11 },
+};
+
+static const struct regmap_config adv7533_main_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = 0xff,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static const struct regmap_config adv7533_dsi_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = 0xff,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+
+static struct adv7533 *encoder_to_adv7533(struct drm_encoder *encoder)
+{
+ return to_encoder_slave(encoder)->slave_priv;
+}
+
+static const int edid_i2c_addr = 0x7e;
+static const int packet_i2c_addr = 0x70;
+static const int dsi_i2c_addr = 0x78;
+
+static const struct of_device_id adv7533_of_ids[] = {
+ { .compatible = "adi,adv7533"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, adv7533_of_ids);
+
+/* -----------------------------------------------------------------------------
+ * Hardware configuration
+ */
+
+static void adv7533_set_colormap(struct adv7533 *adv7533, bool enable,
+ const uint16_t *coeff,
+ unsigned int scaling_factor)
+{
+ unsigned int i;
+
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_CSC_UPPER(1),
+ ADV7533_CSC_UPDATE_MODE, ADV7533_CSC_UPDATE_MODE);
+
+ if (enable) {
+ for (i = 0; i < 12; ++i) {
+ regmap_update_bits(adv7533->regmap_main,
+ ADV7533_REG_CSC_UPPER(i),
+ 0x1f, coeff[i] >> 8);
+ regmap_write(adv7533->regmap_main,
+ ADV7533_REG_CSC_LOWER(i),
+ coeff[i] & 0xff);
+ }
+ }
+
+ if (enable)
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_CSC_UPPER(0),
+ 0xe0, 0x80 | (scaling_factor << 5));
+ else
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_CSC_UPPER(0),
+ 0x80, 0x00);
+
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_CSC_UPPER(1),
+ ADV7533_CSC_UPDATE_MODE, 0);
+}
+
+static int adv7533_packet_enable(struct adv7533 *adv7533, unsigned int packet)
+{
+ if (packet & 0xff)
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_PACKET_ENABLE0,
+ packet, 0xff);
+
+ if (packet & 0xff00) {
+ packet >>= 8;
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_PACKET_ENABLE1,
+ packet, 0xff);
+ }
+
+ return 0;
+}
+
+static int adv7533_packet_disable(struct adv7533 *adv7533, unsigned int packet)
+{
+ if (packet & 0xff)
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_PACKET_ENABLE0,
+ packet, 0x00);
+
+ if (packet & 0xff00) {
+ packet >>= 8;
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_PACKET_ENABLE1,
+ packet, 0x00);
+ }
+
+ return 0;
+}
+
+/* Coefficients for adv7533 color space conversion */
+static const uint16_t adv7533_csc_ycbcr_to_rgb[] = {
+ 0x0734, 0x04ad, 0x0000, 0x1c1b,
+ 0x1ddc, 0x04ad, 0x1f24, 0x0135,
+ 0x0000, 0x04ad, 0x087c, 0x1b77,
+};
+
+static void adv7533_set_config_csc(struct adv7533 *adv7533,
+ struct drm_connector *connector,
+ bool rgb)
+{
+ struct adv7533_video_config config;
+ bool output_format_422, output_format_ycbcr;
+ unsigned int mode;
+ uint8_t infoframe[17];
+
+ if (adv7533->edid)
+ config.hdmi_mode = drm_detect_hdmi_monitor(adv7533->edid);
+ else
+ config.hdmi_mode = false;
+
+ hdmi_avi_infoframe_init(&config.avi_infoframe);
+
+ config.avi_infoframe.scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
+
+ if (rgb) {
+ config.csc_enable = false;
+ config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB;
+ } else {
+ config.csc_scaling_factor = ADV7533_CSC_SCALING_4;
+ config.csc_coefficents = adv7533_csc_ycbcr_to_rgb;
+
+ if ((connector->display_info.color_formats &
+ DRM_COLOR_FORMAT_YCRCB422) &&
+ config.hdmi_mode) {
+ config.csc_enable = false;
+ config.avi_infoframe.colorspace =
+ HDMI_COLORSPACE_YUV422;
+ } else {
+ config.csc_enable = true;
+ config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB;
+ }
+ }
+
+ if (config.hdmi_mode) {
+ mode = ADV7533_HDMI_CFG_MODE_HDMI;
+
+ switch (config.avi_infoframe.colorspace) {
+ case HDMI_COLORSPACE_YUV444:
+ output_format_422 = false;
+ output_format_ycbcr = true;
+ break;
+ case HDMI_COLORSPACE_YUV422:
+ output_format_422 = true;
+ output_format_ycbcr = true;
+ break;
+ default:
+ output_format_422 = false;
+ output_format_ycbcr = false;
+ break;
+ }
+ } else {
+ mode = ADV7533_HDMI_CFG_MODE_DVI;
+ output_format_422 = false;
+ output_format_ycbcr = false;
+ }
+
+ DRM_INFO("HDMI: mode=%d,format_422=%d,format_ycbcr=%d\n",
+ mode, output_format_422, output_format_ycbcr);
+ adv7533_packet_disable(adv7533, ADV7533_PACKET_ENABLE_AVI_INFOFRAME);
+
+ adv7533_set_colormap(adv7533, config.csc_enable,
+ config.csc_coefficents,
+ config.csc_scaling_factor);
+
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_VIDEO_INPUT_CFG1,
+ 0x81, (output_format_422 << 7) | output_format_ycbcr);
+
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_HDCP_HDMI_CFG,
+ ADV7533_HDMI_CFG_MODE_MASK, mode);
+
+ hdmi_avi_infoframe_pack(&config.avi_infoframe, infoframe,
+ sizeof(infoframe));
+
+ /* The AVI infoframe id is not configurable */
+ regmap_bulk_write(adv7533->regmap_main, ADV7533_REG_AVI_INFOFRAME_VERSION,
+ infoframe + 1, sizeof(infoframe) - 1);
+
+ adv7533_packet_enable(adv7533, ADV7533_PACKET_ENABLE_AVI_INFOFRAME);
+}
+
+
+/* -----------------------------------------------------------------------------
+ * Interrupt and hotplug detection
+ */
+
+static bool adv7533_hpd(struct adv7533 *adv7533)
+{
+ unsigned int irq0;
+ int ret;
+
+ ret = regmap_read(adv7533->regmap_main, ADV7533_REG_INT(0), &irq0);
+ if (ret < 0)
+ return false;
+
+ if (irq0 & ADV7533_INT0_HDP)
+ return true;
+
+ return false;
+}
+
+static void adv7533_hotplug_work_func(struct work_struct *work)
+{
+ struct adv7533 *adv7533;
+ bool hpd_event_sent;
+
+ DRM_INFO("HDMI: hpd work in\n");
+ adv7533 = container_of(work, struct adv7533, hotplug_work.work);
+
+ if (adv7533->encoder && adv7533_hpd(adv7533)) {
+ hpd_event_sent = drm_helper_hpd_irq_event(adv7533->encoder->dev);
+ DRM_INFO("HDMI: hpd_event_sent=%d\n", hpd_event_sent);
+ }
+
+ wake_up_all(&adv7533->wq);
+ DRM_INFO("HDMI: hpd work out\n");
+}
+
+static irqreturn_t adv7533_irq_handler(int irq, void *devid)
+{
+ struct adv7533 *adv7533 = devid;
+
+ mod_delayed_work(system_wq, &adv7533->hotplug_work,
+ msecs_to_jiffies(1500));
+
+ return IRQ_HANDLED;
+}
+
+static unsigned int adv7533_is_interrupt_pending(struct adv7533 *adv7533,
+ unsigned int irq)
+{
+ unsigned int irq0, irq1;
+ unsigned int pending;
+ int ret;
+
+ ret = regmap_read(adv7533->regmap_main, ADV7533_REG_INT(0), &irq0);
+ if (ret < 0)
+ return 0;
+ ret = regmap_read(adv7533->regmap_main, ADV7533_REG_INT(1), &irq1);
+ if (ret < 0)
+ return 0;
+
+ pending = (irq1 << 8) | irq0;
+
+ return pending & irq;
+}
+
+static int adv7533_wait_for_interrupt(struct adv7533 *adv7533, int irq,
+ int timeout)
+{
+ unsigned int pending;
+ int ret;
+
+ if (adv7533->i2c_main->irq) {
+ ret = wait_event_interruptible_timeout(adv7533->wq,
+ adv7533_is_interrupt_pending(adv7533, irq),
+ msecs_to_jiffies(timeout));
+ if (ret <= 0)
+ return 0;
+ pending = adv7533_is_interrupt_pending(adv7533, irq);
+ } else {
+ if (timeout < 25)
+ timeout = 25;
+ do {
+ pending = adv7533_is_interrupt_pending(adv7533, irq);
+ if (pending)
+ break;
+ msleep(25);
+ timeout -= 25;
+ } while (timeout >= 25);
+ }
+
+ return pending;
+}
+
+/* -----------------------------------------------------------------------------
+ * EDID retrieval
+ */
+
+static int adv7533_get_edid_block(void *data, u8 *buf, unsigned int block,
+ size_t len)
+{
+ struct adv7533 *adv7533 = data;
+ struct i2c_msg xfer[2];
+ uint8_t offset;
+ unsigned int i;
+ int ret;
+
+ if (len > 128)
+ return -EINVAL;
+
+ if (adv7533->current_edid_segment != block / 2) {
+ unsigned int status;
+
+ ret = regmap_read(adv7533->regmap_main, ADV7533_REG_DDC_STATUS,
+ &status);
+ if (ret < 0)
+ return ret;
+
+ DRM_INFO("HDMI: status=0x%x, ret=%d\n", status, ret);
+ if (status != 2) {
+ /* Open EDID_READY and DDC_ERROR interrupts */
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_INT_ENABLE(0),
+ ADV7533_INT0_EDID_READY, ADV7533_INT0_EDID_READY);
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_INT_ENABLE(1),
+ ADV7533_INT1_DDC_ERROR, ADV7533_INT1_DDC_ERROR);
+ regmap_write(adv7533->regmap_main, ADV7533_REG_EDID_SEGMENT,
+ block);
+ ret = adv7533_wait_for_interrupt(adv7533,
+ ADV7533_INT0_EDID_READY |
+ (ADV7533_INT1_DDC_ERROR << 8), 200);
+
+ DRM_INFO("HDMI: ret=0x%x\n", ret);
+ if (!(ret & ADV7533_INT0_EDID_READY))
+ return -EIO;
+ }
+
+
+ /* Break this apart, hopefully more I2C controllers will
+ * support 64 byte transfers than 256 byte transfers
+ */
+
+ xfer[0].addr = adv7533->i2c_edid->addr;
+ xfer[0].flags = 0;
+ xfer[0].len = 1;
+ xfer[0].buf = &offset;
+ xfer[1].addr = adv7533->i2c_edid->addr;
+ xfer[1].flags = I2C_M_RD;
+ xfer[1].len = 64;
+ xfer[1].buf = adv7533->edid_buf;
+
+ offset = 0;
+
+ for (i = 0; i < 4; ++i) {
+ ret = i2c_transfer(adv7533->i2c_edid->adapter, xfer,
+ ARRAY_SIZE(xfer));
+ if (ret < 0)
+ return ret;
+ else if (ret != 2)
+ return -EIO;
+
+ xfer[1].buf += 64;
+ offset += 64;
+ }
+
+ adv7533->current_edid_segment = block / 2;
+ }
+
+ if (block % 2 == 0)
+ memcpy(buf, adv7533->edid_buf, len);
+ else
+ memcpy(buf, adv7533->edid_buf + 128, len);
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Encoder operations
+ */
+
+static int adv7533_get_modes(struct drm_encoder *encoder,
+ struct drm_connector *connector)
+{
+ struct adv7533 *adv7533 = encoder_to_adv7533(encoder);
+ struct edid *edid;
+ unsigned int count;
+
+ /* Reading the EDID only works if the device is powered */
+ if (adv7533->dpms_mode != DRM_MODE_DPMS_ON) {
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_POWER,
+ ADV7533_POWER_POWER_DOWN, 0);
+ adv7533->current_edid_segment = -1;
+ msleep(200); /* wait for EDID finish reading */
+ }
+
+ edid = drm_do_get_edid(connector, adv7533_get_edid_block, adv7533);
+
+ if (adv7533->dpms_mode != DRM_MODE_DPMS_ON)
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_POWER,
+ ADV7533_POWER_POWER_DOWN,
+ ADV7533_POWER_POWER_DOWN);
+
+ adv7533->edid = edid;
+ adv7533_set_config_csc(adv7533, connector, true);
+ if (!edid) {
+ DRM_ERROR("Reading edid block error!\n");
+ return 0;
+ }
+
+ drm_mode_connector_update_edid_property(connector, edid);
+ count = drm_add_edid_modes(connector, edid);
+
+ kfree(adv7533->edid);
+ adv7533->edid = NULL;
+ return count;
+}
+
+static void adv7533_dsi_receiver_dpms(struct adv7533 *adv7533, int mode)
+{
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ regmap_write(adv7533->regmap_dsi, 0x03, 0x89);
+ regmap_write(adv7533->regmap_dsi, 0x27, 0x0b); /* Timing generator off */
+ regmap_write(adv7533->regmap_dsi, 0x1C, 0x30); /* 3 lanes */
+ break;
+ default:
+ regmap_write(adv7533->regmap_dsi, 0x03, 0x0b);
+ break;
+ }
+}
+
+static void adv7533_encoder_dpms(struct drm_encoder *encoder, int mode)
+{
+ struct adv7533 *adv7533 = encoder_to_adv7533(encoder);
+
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ adv7533->current_edid_segment = -1;
+
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_POWER,
+ ADV7533_POWER_POWER_DOWN, 0);
+ /*
+ * Per spec it is allowed to pulse the HDP signal to indicate
+ * that the EDID information has changed. Some monitors do this
+ * when they wakeup from standby or are enabled. When the HDP
+ * goes low the adv7533 is reset and the outputs are disabled
+ * which might cause the monitor to go to standby again. To
+ * avoid this we ignore the HDP pin for the first few seconds
+ * after enabeling the output.
+ */
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_POWER2,
+ BIT(6), BIT(6));
+ /* Most of the registers are reset during power down or
+ * when HPD is low
+ */
+ regcache_sync(adv7533->regmap_main);
+ break;
+ default:
+ /* TODO: setup additional power down modes */
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_POWER,
+ ADV7533_POWER_POWER_DOWN,
+ ADV7533_POWER_POWER_DOWN);
+ regcache_mark_dirty(adv7533->regmap_main);
+ break;
+ }
+
+ /* dsi receiver dpms */
+ adv7533_dsi_receiver_dpms(adv7533, mode);
+ adv7533->dpms_mode = mode;
+}
+
+static enum drm_connector_status
+adv7533_encoder_detect(struct drm_encoder *encoder,
+ struct drm_connector *connector)
+{
+ struct adv7533 *adv7533 = encoder_to_adv7533(encoder);
+ enum drm_connector_status status;
+ unsigned int val;
+ bool hpd;
+ int ret;
+
+ ret = regmap_read(adv7533->regmap_main, ADV7533_REG_STATUS, &val);
+ if (ret < 0)
+ return connector_status_disconnected;
+
+ if (val & ADV7533_STATUS_HPD)
+ status = connector_status_connected;
+ else
+ status = connector_status_disconnected;
+
+ hpd = adv7533_hpd(adv7533);
+
+ DRM_INFO("HDMI: status=%d,hpd=%d,dpms=%d\n",
+ status, hpd, adv7533->dpms_mode);
+ return status;
+}
+
+static int adv7533_encoder_mode_valid(struct drm_encoder *encoder,
+ struct drm_display_mode *mode)
+{
+ if (mode->clock > 165000)
+ return MODE_CLOCK_HIGH;
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ return MODE_NO_INTERLACE;
+
+ return MODE_OK;
+}
+
+static void adv7533_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adj_mode)
+{
+}
+
+static struct drm_encoder_slave_funcs adv7533_encoder_funcs = {
+ .dpms = adv7533_encoder_dpms,
+ .mode_valid = adv7533_encoder_mode_valid,
+ .mode_set = adv7533_encoder_mode_set,
+ .detect = adv7533_encoder_detect,
+ .get_modes = adv7533_get_modes,
+};
+
+static int adv7533_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct adv7533 *adv7533;
+ struct device *dev = &i2c->dev;
+ unsigned int val;
+ int ret;
+
+ DRM_DEBUG_DRIVER("enter.\n");
+ if (!dev->of_node)
+ return -EINVAL;
+
+ adv7533 = devm_kzalloc(dev, sizeof(*adv7533), GFP_KERNEL);
+ if (!adv7533)
+ return -ENOMEM;
+
+ adv7533->dpms_mode = DRM_MODE_DPMS_OFF;
+
+ /*
+ * The power down GPIO is optional. If present, toggle it from active to
+ * inactive to wake up the encoder.
+ */
+ adv7533->gpio_pd = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_HIGH);
+ if (IS_ERR(adv7533->gpio_pd))
+ return PTR_ERR(adv7533->gpio_pd);
+
+ if (adv7533->gpio_pd) {
+ mdelay(5);
+ gpiod_set_value_cansleep(adv7533->gpio_pd, 0);
+ }
+
+ adv7533->regmap_main = devm_regmap_init_i2c(i2c, &adv7533_main_regmap_config);
+ if (IS_ERR(adv7533->regmap_main))
+ return PTR_ERR(adv7533->regmap_main);
+
+ ret = regmap_read(adv7533->regmap_main, ADV7533_REG_CHIP_REVISION, &val);
+ if (ret)
+ return ret;
+ dev_dbg(dev, "Rev. %d\n", val);
+ ret = regmap_register_patch(adv7533->regmap_main, adv7533_fixed_registers,
+ ARRAY_SIZE(adv7533_fixed_registers));
+ if (ret)
+ return ret;
+
+ regmap_write(adv7533->regmap_main, ADV7533_REG_EDID_I2C_ADDR, edid_i2c_addr);
+ regmap_write(adv7533->regmap_main, ADV7533_REG_PACKET_I2C_ADDR,
+ packet_i2c_addr);
+ regmap_write(adv7533->regmap_main, ADV7533_REG_CEC_I2C_ADDR, dsi_i2c_addr);
+ adv7533_packet_disable(adv7533, 0xffff);
+
+ adv7533->i2c_main = i2c;
+ adv7533->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1);
+ if (!adv7533->i2c_edid)
+ return -ENOMEM;
+
+ adv7533->i2c_dsi = i2c_new_dummy(i2c->adapter, dsi_i2c_addr >> 1);
+ if (!adv7533->i2c_dsi) {
+ ret = -ENOMEM;
+ goto err_i2c_unregister_edid;
+ }
+
+ adv7533->regmap_dsi = devm_regmap_init_i2c(adv7533->i2c_dsi,
+ &adv7533_dsi_regmap_config);
+ if (IS_ERR(adv7533->regmap_dsi)) {
+ ret = PTR_ERR(adv7533->regmap_dsi);
+ goto err_i2c_unregister_dsi;
+ }
+
+ ret = regmap_register_patch(adv7533->regmap_dsi, adv7533_dsi_fixed_registers,
+ ARRAY_SIZE(adv7533_dsi_fixed_registers));
+ if (ret)
+ return ret;
+
+ if (i2c->irq) {
+ init_waitqueue_head(&adv7533->wq);
+
+ INIT_DELAYED_WORK(&adv7533->hotplug_work, adv7533_hotplug_work_func);
+ ret = devm_request_threaded_irq(dev, i2c->irq, NULL,
+ adv7533_irq_handler,
+ IRQF_ONESHOT, dev_name(dev),
+ adv7533);
+ if (ret)
+ goto err_i2c_unregister_dsi;
+ }
+
+ /* CEC is unused for now */
+ regmap_write(adv7533->regmap_main, ADV7533_REG_CEC_CTRL,
+ ADV7533_CEC_CTRL_POWER_DOWN);
+
+ regmap_update_bits(adv7533->regmap_main, ADV7533_REG_POWER,
+ ADV7533_POWER_POWER_DOWN, ADV7533_POWER_POWER_DOWN);
+
+ adv7533->current_edid_segment = -1;
+
+ i2c_set_clientdata(i2c, adv7533);
+
+ DRM_DEBUG_DRIVER("exit success.\n");
+ return 0;
+
+err_i2c_unregister_dsi:
+ i2c_unregister_device(adv7533->i2c_dsi);
+err_i2c_unregister_edid:
+ i2c_unregister_device(adv7533->i2c_edid);
+
+ return ret;
+}
+
+static int adv7533_remove(struct i2c_client *i2c)
+{
+ struct adv7533 *adv7533 = i2c_get_clientdata(i2c);
+
+ i2c_unregister_device(adv7533->i2c_dsi);
+ i2c_unregister_device(adv7533->i2c_edid);
+
+ return 0;
+}
+
+static int adv7533_encoder_init(struct i2c_client *i2c, struct drm_device *dev,
+ struct drm_encoder_slave *encoder)
+{
+
+ struct adv7533 *adv7533 = i2c_get_clientdata(i2c);
+
+ encoder->slave_priv = adv7533;
+ encoder->slave_funcs = &adv7533_encoder_funcs;
+ adv7533->encoder = &encoder->base;
+
+ return 0;
+}
+
+static const struct i2c_device_id adv7533_i2c_ids[] = {
+ { "adv7533", 0},
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, adv7533_i2c_ids);
+
+static struct drm_i2c_encoder_driver adv7533_driver = {
+ .i2c_driver = {
+ .driver = {
+ .name = "adv7533",
+ .of_match_table = adv7533_of_ids,
+ },
+ .id_table = adv7533_i2c_ids,
+ .probe = adv7533_probe,
+ .remove = adv7533_remove,
+ },
+
+ .encoder_init = adv7533_encoder_init,
+};
+
+static int __init adv7533_init(void)
+{
+ return drm_i2c_encoder_register(THIS_MODULE, &adv7533_driver);
+}
+module_init(adv7533_init);
+
+static void __exit adv7533_exit(void)
+{
+ drm_i2c_encoder_unregister(&adv7533_driver);
+}
+module_exit(adv7533_exit);
+
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("ADV7533 HDMI transmitter driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/i2c/adv7533.h b/drivers/gpu/drm/i2c/adv7533.h
new file mode 100644
index 000000000000..90d3e098571a
--- /dev/null
+++ b/drivers/gpu/drm/i2c/adv7533.h
@@ -0,0 +1,223 @@
+/*
+ * Analog Devices ADV7533 HDMI transmitter driver
+ *
+ * Copyright 2015 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#ifndef __DRM_I2C_ADV7533_H__
+#define __DRM_I2C_ADV7533_H__
+
+#include <linux/hdmi.h>
+
+#define ADV7533_REG_CHIP_REVISION 0x00
+#define ADV7533_REG_N0 0x01
+#define ADV7533_REG_N1 0x02
+#define ADV7533_REG_N2 0x03
+#define ADV7533_REG_SPDIF_FREQ 0x04
+#define ADV7533_REG_CTS_AUTOMATIC1 0x05
+#define ADV7533_REG_CTS_AUTOMATIC2 0x06
+#define ADV7533_REG_CTS_MANUAL0 0x07
+#define ADV7533_REG_CTS_MANUAL1 0x08
+#define ADV7533_REG_CTS_MANUAL2 0x09
+#define ADV7533_REG_AUDIO_SOURCE 0x0a
+#define ADV7533_REG_AUDIO_CONFIG 0x0b
+#define ADV7533_REG_I2S_CONFIG 0x0c
+#define ADV7533_REG_I2S_WIDTH 0x0d
+#define ADV7533_REG_AUDIO_SUB_SRC0 0x0e
+#define ADV7533_REG_AUDIO_SUB_SRC1 0x0f
+#define ADV7533_REG_AUDIO_SUB_SRC2 0x10
+#define ADV7533_REG_AUDIO_SUB_SRC3 0x11
+#define ADV7533_REG_AUDIO_CFG1 0x12
+#define ADV7533_REG_AUDIO_CFG2 0x13
+#define ADV7533_REG_AUDIO_CFG3 0x14
+#define ADV7533_REG_I2C_FREQ_ID_CFG 0x15
+#define ADV7533_REG_VIDEO_INPUT_CFG1 0x16
+#define ADV7533_REG_CSC_UPPER(x) (0x18 + (x) * 2)
+#define ADV7533_REG_CSC_LOWER(x) (0x19 + (x) * 2)
+#define ADV7533_REG_SYNC_DECODER(x) (0x30 + (x))
+#define ADV7533_REG_DE_GENERATOR (0x35 + (x))
+#define ADV7533_REG_PIXEL_REPETITION 0x3b
+#define ADV7533_REG_VIC_MANUAL 0x3c
+#define ADV7533_REG_VIC_SEND 0x3d
+#define ADV7533_REG_VIC_DETECTED 0x3e
+#define ADV7533_REG_AUX_VIC_DETECTED 0x3f
+#define ADV7533_REG_PACKET_ENABLE0 0x40
+#define ADV7533_REG_POWER 0x41
+#define ADV7533_REG_STATUS 0x42
+#define ADV7533_REG_EDID_I2C_ADDR 0x43
+#define ADV7533_REG_PACKET_ENABLE1 0x44
+#define ADV7533_REG_PACKET_I2C_ADDR 0x45
+#define ADV7533_REG_DSD_ENABLE 0x46
+#define ADV7533_REG_VIDEO_INPUT_CFG2 0x48
+#define ADV7533_REG_INFOFRAME_UPDATE 0x4a
+#define ADV7533_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
+#define ADV7533_REG_AVI_INFOFRAME_VERSION 0x52
+#define ADV7533_REG_AVI_INFOFRAME_LENGTH 0x53
+#define ADV7533_REG_AVI_INFOFRAME_CHECKSUM 0x54
+#define ADV7533_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
+#define ADV7533_REG_AUDIO_INFOFRAME_VERSION 0x70
+#define ADV7533_REG_AUDIO_INFOFRAME_LENGTH 0x71
+#define ADV7533_REG_AUDIO_INFOFRAME_CHECKSUM 0x72
+#define ADV7533_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
+#define ADV7533_REG_INT_ENABLE(x) (0x94 + (x))
+#define ADV7533_REG_INT(x) (0x96 + (x))
+#define ADV7533_REG_INPUT_CLK_DIV 0x9d
+#define ADV7533_REG_PLL_STATUS 0x9e
+#define ADV7533_REG_HDMI_POWER 0xa1
+#define ADV7533_REG_HDCP_HDMI_CFG 0xaf
+#define ADV7533_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
+#define ADV7533_REG_HDCP_STATUS 0xb8
+#define ADV7533_REG_BCAPS 0xbe
+#define ADV7533_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
+#define ADV7533_REG_EDID_SEGMENT 0xc4
+#define ADV7533_REG_DDC_STATUS 0xc8
+#define ADV7533_REG_EDID_READ_CTRL 0xc9
+#define ADV7533_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
+#define ADV7533_REG_TIMING_GEN_SEQ 0xd0
+#define ADV7533_REG_POWER2 0xd6
+#define ADV7533_REG_HSYNC_PLACEMENT_MSB 0xfa
+
+#define ADV7533_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
+#define ADV7533_REG_TMDS_CLOCK_INV 0xde
+#define ADV7533_REG_ARC_CTRL 0xdf
+#define ADV7533_REG_CEC_I2C_ADDR 0xe1
+#define ADV7533_REG_CEC_CTRL 0xe2
+#define ADV7533_REG_CHIP_ID_HIGH 0xf5
+#define ADV7533_REG_CHIP_ID_LOW 0xf6
+
+#define ADV7533_CSC_ENABLE BIT(7)
+#define ADV7533_CSC_UPDATE_MODE BIT(5)
+
+#define ADV7533_INT0_HDP BIT(7)
+#define ADV7533_INT0_VSYNC BIT(5)
+#define ADV7533_INT0_AUDIO_FIFO_FULL BIT(4)
+#define ADV7533_INT0_EDID_READY BIT(2)
+#define ADV7533_INT0_HDCP_AUTHENTICATED BIT(1)
+
+#define ADV7533_INT1_DDC_ERROR BIT(7)
+#define ADV7533_INT1_BKSV BIT(6)
+#define ADV7533_INT1_CEC_TX_READY BIT(5)
+#define ADV7533_INT1_CEC_TX_ARBIT_LOST BIT(4)
+#define ADV7533_INT1_CEC_TX_RETRY_TIMEOUT BIT(3)
+#define ADV7533_INT1_CEC_RX_READY3 BIT(2)
+#define ADV7533_INT1_CEC_RX_READY2 BIT(1)
+#define ADV7533_INT1_CEC_RX_READY1 BIT(0)
+
+#define ADV7533_ARC_CTRL_POWER_DOWN BIT(0)
+
+#define ADV7533_CEC_CTRL_POWER_DOWN BIT(0)
+
+#define ADV7533_POWER_POWER_DOWN BIT(6)
+
+#define ADV7533_HDMI_CFG_MODE_MASK 0x2
+#define ADV7533_HDMI_CFG_MODE_DVI 0x0
+#define ADV7533_HDMI_CFG_MODE_HDMI 0x2
+
+#define ADV7533_AUDIO_SELECT_I2C 0x0
+#define ADV7533_AUDIO_SELECT_SPDIF 0x1
+#define ADV7533_AUDIO_SELECT_DSD 0x2
+#define ADV7533_AUDIO_SELECT_HBR 0x3
+#define ADV7533_AUDIO_SELECT_DST 0x4
+
+#define ADV7533_I2S_SAMPLE_LEN_16 0x2
+#define ADV7533_I2S_SAMPLE_LEN_20 0x3
+#define ADV7533_I2S_SAMPLE_LEN_18 0x4
+#define ADV7533_I2S_SAMPLE_LEN_22 0x5
+#define ADV7533_I2S_SAMPLE_LEN_19 0x8
+#define ADV7533_I2S_SAMPLE_LEN_23 0x9
+#define ADV7533_I2S_SAMPLE_LEN_24 0xb
+#define ADV7533_I2S_SAMPLE_LEN_17 0xc
+#define ADV7533_I2S_SAMPLE_LEN_21 0xd
+
+#define ADV7533_SAMPLE_FREQ_44100 0x0
+#define ADV7533_SAMPLE_FREQ_48000 0x2
+#define ADV7533_SAMPLE_FREQ_32000 0x3
+#define ADV7533_SAMPLE_FREQ_88200 0x8
+#define ADV7533_SAMPLE_FREQ_96000 0xa
+#define ADV7533_SAMPLE_FREQ_176400 0xc
+#define ADV7533_SAMPLE_FREQ_192000 0xe
+
+#define ADV7533_STATUS_POWER_DOWN_POLARITY BIT(7)
+#define ADV7533_STATUS_HPD BIT(6)
+#define ADV7533_STATUS_MONITOR_SENSE BIT(5)
+#define ADV7533_STATUS_I2S_32BIT_MODE BIT(3)
+
+#define ADV7533_PACKET_ENABLE_N_CTS BIT(8+6)
+#define ADV7533_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5)
+#define ADV7533_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)
+#define ADV7533_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3)
+#define ADV7533_PACKET_ENABLE_GC BIT(7)
+#define ADV7533_PACKET_ENABLE_SPD BIT(6)
+#define ADV7533_PACKET_ENABLE_MPEG BIT(5)
+#define ADV7533_PACKET_ENABLE_ACP BIT(4)
+#define ADV7533_PACKET_ENABLE_ISRC BIT(3)
+#define ADV7533_PACKET_ENABLE_GM BIT(2)
+#define ADV7533_PACKET_ENABLE_SPARE2 BIT(1)
+#define ADV7533_PACKET_ENABLE_SPARE1 BIT(0)
+
+#define ADV7533_REG_POWER2_HDP_SRC_MASK 0xc0
+#define ADV7533_REG_POWER2_HDP_SRC_BOTH 0x00
+#define ADV7533_REG_POWER2_HDP_SRC_HDP 0x40
+#define ADV7533_REG_POWER2_HDP_SRC_CEC 0x80
+#define ADV7533_REG_POWER2_HDP_SRC_NONE 0xc0
+#define ADV7533_REG_POWER2_TDMS_ENABLE BIT(4)
+#define ADV7533_REG_POWER2_GATE_INPUT_CLK BIT(0)
+
+#define ADV7533_LOW_REFRESH_RATE_NONE 0x0
+#define ADV7533_LOW_REFRESH_RATE_24HZ 0x1
+#define ADV7533_LOW_REFRESH_RATE_25HZ 0x2
+#define ADV7533_LOW_REFRESH_RATE_30HZ 0x3
+
+#define ADV7533_AUDIO_CFG3_LEN_MASK 0x0f
+#define ADV7533_I2C_FREQ_ID_CFG_RATE_MASK 0xf0
+
+#define ADV7533_AUDIO_SOURCE_I2S 0
+#define ADV7533_AUDIO_SOURCE_SPDIF 1
+
+#define ADV7533_I2S_FORMAT_I2S 0
+#define ADV7533_I2S_FORMAT_RIGHT_J 1
+#define ADV7533_I2S_FORMAT_LEFT_J 2
+
+#define ADV7533_PACKET(p, x) ((p) * 0x20 + (x))
+#define ADV7533_PACKET_SDP(x) ADV7533_PACKET(0, x)
+#define ADV7533_PACKET_MPEG(x) ADV7533_PACKET(1, x)
+#define ADV7533_PACKET_ACP(x) ADV7533_PACKET(2, x)
+#define ADV7533_PACKET_ISRC1(x) ADV7533_PACKET(3, x)
+#define ADV7533_PACKET_ISRC2(x) ADV7533_PACKET(4, x)
+#define ADV7533_PACKET_GM(x) ADV7533_PACKET(5, x)
+#define ADV7533_PACKET_SPARE(x) ADV7533_PACKET(6, x)
+
+
+/**
+ * enum adv7533_csc_scaling - Scaling factor for the ADV7533 CSC
+ * @ADV7533_CSC_SCALING_1: CSC results are not scaled
+ * @ADV7533_CSC_SCALING_2: CSC results are scaled by a factor of two
+ * @ADV7533_CSC_SCALING_4: CSC results are scalled by a factor of four
+ */
+enum adv7533_csc_scaling {
+ ADV7533_CSC_SCALING_1 = 0,
+ ADV7533_CSC_SCALING_2 = 1,
+ ADV7533_CSC_SCALING_4 = 2,
+};
+
+/**
+ * struct adv7533_video_config - Describes adv7533 hardware configuration
+ * @csc_enable: Whether to enable color space conversion
+ * @csc_scaling_factor: Color space conversion scaling factor
+ * @csc_coefficents: Color space conversion coefficents
+ * @hdmi_mode: Whether to use HDMI or DVI output mode
+ * @avi_infoframe: HDMI infoframe
+ */
+struct adv7533_video_config {
+ bool csc_enable;
+ enum adv7533_csc_scaling csc_scaling_factor;
+ const uint16_t *csc_coefficents;
+
+ bool hdmi_mode;
+ struct hdmi_avi_infoframe avi_infoframe;
+};
+
+
+#endif /* __DRM_I2C_ADV7533_H__ */
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index 2d56dcda1b69..42bad18c66c9 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
@@ -408,16 +408,6 @@ static struct sysrq_key_op sysrq_unrt_op = {
.enable_mask = SYSRQ_ENABLE_RTNICE,
};
-#ifdef CONFIG_DRM_SYSRQ_MODE_HACK
-extern void sysrq_handle_modehack(int key);
-static struct sysrq_key_op sysrq_modehack_op = {
- .handler = sysrq_handle_modehack,
- .help_msg = "Change drm mode",
- .action_msg = "Hack to switch DRM mode",
- .enable_mask = SYSRQ_ENABLE_HACK_DRM_MODE,
-};
-#endif
-
/* Key Operations table and lock */
static DEFINE_SPINLOCK(sysrq_key_table_lock);
@@ -444,11 +434,7 @@ static struct sysrq_key_op *sysrq_key_table[36] = {
&sysrq_term_op, /* e */
&sysrq_moom_op, /* f */
/* g: May be registered for the kernel debugger */
-#ifdef CONFIG_DRM_SYSRQ_MODE_HACK
- &sysrq_modehack_op, /* g */
-#else
NULL, /* g */
-#endif
NULL, /* h - reserved for help */
&sysrq_kill_op, /* i */
#ifdef CONFIG_BLOCK
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 04:21:08 +0000