diff options
| -rw-r--r-- | arch/arm64/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/misc/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/misc/Makefile | 4 | ||||
| -rw-r--r-- | drivers/misc/hi6220-sysconfig.c | 64 |
4 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0e25ce9d99c7..3b9213619aae 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -293,6 +293,7 @@ config ARCH_HISI select ARCH_REQUIRE_GPIOLIB select GPIO_PL061 select COMMON_CLK_HI6220 + select HI6220_SYSCFG select MFD_HI655X_PMIC select REGULATOR_HI655X help diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index eeaac87bb09b..63c526758039 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -515,6 +515,14 @@ config VEXPRESS_SYSCFG bus. System Configuration interface is one of the possible means of generating transactions on this bus. +config HI6220_SYSCFG + bool "Hisilicon HI6220 System Configuration driver" + depends on ARCH_HISI + default y + help + Hisilicon HI6220 uses some registers to configure some chip hosts to + work or not, e.g. disable the UART hosts reset and let's them work. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e2be6c6c0da8..7eaaccb62289 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -54,3 +54,7 @@ obj-$(CONFIG_SRAM) += sram.o obj-y += mic/ obj-$(CONFIG_GENWQE) += genwqe/ obj-$(CONFIG_HIP04_SERDES) += serdes/ +obj-$(CONFIG_ECHO) += echo/ +obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o +obj-$(CONFIG_CXL_BASE) += cxl/ +obj-$(CONFIG_HI6220_SYSCFG) += hi6220-sysconfig.o diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c new file mode 100644 index 000000000000..c4e03627a0ea --- /dev/null +++ b/drivers/misc/hi6220-sysconfig.c @@ -0,0 +1,64 @@ +/* + * For Hisilicon Hi6220 SoC, the reset of some hosts (e.g. UART) should be disabled + * before using them, this driver will handle the host chip reset disable. + * + * Copyright (C) 2015 Hisilicon Ltd. + * Author: Bintian Wang <bintian.wang@huawei.com> + * + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#define reset_offset 0x334 +#define pclk_offset 0x230 + +static int __init hi6220_sysconf(void) +{ + static void __iomem *base = NULL; + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); + if (!node) + return -ENOENT; + + base = of_iomap(node, 0); + if (base == NULL) { + printk(KERN_ERR "hi6220: sysctrl reg iomap failed!\n"); + return -ENOMEM; + } + + /*Disable UART1 reset and set pclk*/ + writel(BIT(5), base + reset_offset); + writel(BIT(5), base + pclk_offset); + + /*Disable UART2 reset and set pclk*/ + writel(BIT(6), base + reset_offset); + writel(BIT(6), base + pclk_offset); + + /*Disable UART3 reset and set pclk*/ + writel(BIT(7), base + reset_offset); + writel(BIT(7), base + pclk_offset); + + /*Disable UART4 reset and set pclk*/ + writel(BIT(8), base + reset_offset); + writel(BIT(8), base + pclk_offset); + + iounmap(base); + + return 0; +} +postcore_initcall(hi6220_sysconf); + +#ifdef CONFIG_ARM64 +#ifdef CONFIG_SPARSE_IRQ +#define NR_IRQS_LEGACY_HI6220 16 + +int __init arch_probe_nr_irqs(void) +{ + return NR_IRQS_LEGACY_HI6220; +} + +#endif +#endif |