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2015-11-08mmc: HiKey: configure the dw_mmc-k3 driver for estuary kernelXinwei Kong
Signed-off-by: Fei Wang <w.f@huawei.com> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
2015-11-08pmic/regulator: Add hisilicon hi655X pmic/regulator core driver for hi6220 SoCZhang Nian
Signed-off-by: Zhang Nian <zhangnian@huawei.com> Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Signed-off-by: Dongbin Yu <yudongbin@huawei.com> Signed-off-by: Fei Wang <w.f@huawei.com> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
2015-11-08dts: hi6220: Add device nodes for UART and enble UART3Xinwei Kong
Add UART device nodes to Hisilicon hi6220 SoC dts file. Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
2015-11-08gpio: hi6220: add dts for Hisilicom hi6220 SoCYunlei He
This patch adds gpio dts file for hi6220 SoC. It includes nineteen pl061 gpio device nodes and some association attributes about them, such as "interrupts", "clocks", etc. Signed-off-by: Yunlei He <heyunlei@huawei.com> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
2015-11-08pinctrl: hi6220: adds dts for Hisilicon hi6220 SoCYunlei He
This patch adds pinctrl dts file for hi6220 SoC. It includes three pinctrl-single device nodes and some association attributes about them. Signed-off-by: Yunlei He <heyunlei@huawei.com>
2015-11-08arm64: Kconfig: Add pinctrl/GPIO support for Hisilicon SoCFei Wang
Add the default support of pinctrl/GPIO for Hisilicon ARMv8 SoC families. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Signed-off-by: Fei Wang <w.f@huawei.com>
2015-11-08ARM: hisi: add missing maint irq in hi6220 gicHaojian Zhuang
The maintence irq is missed in GIC400 of Hi6220 SoC. The error message is in below. [ 2.695277] kvm [1]: Using HYP init bounce page @3c217000 [ 2.701327] kvm [1]: error getting vgic maintenance irq from DT [ 2.707742] kvm [1]: error initializing Hyp mode: -6 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2015-11-08Merge pull request #9 from kongzizaixian/masterkongzizaixian
clk: hi6220: fix compile error on arm32
2015-11-08clk: hi6220: fix compile error on arm32Xinwei Kong
Fix the following compile error when choose arm32 platform: drivers/built-in.o: In function i6220_clk_register_divider': :(.init.text+0x1a84c): undefined reference to i6220_register_clkdiv' Makefile:925: recipe for target 'vmlinux' failed make: *** [vmlinux] Error 1 Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Reported-by: tyler.baker@linaro.org
2015-11-06Merge pull request #6 from open-estuary/docker-devkongzizaixian
Enabled Docker related kernel features
2015-11-06Merge pull request #8 from wangzhou/pcie_for_kongxinwei_estuary_v2.1kongzizaixian
Pcie for kongxinwei estuary v2.1
2015-11-06dts:hip05 pcie dtsiGabriele Paoloni
Signed-off-by: liudongdong <liudongdong3@huawei.com>
2015-11-06DT: Hip05-d02: add pcie nodes for D02 boardSherlock Wang
Different boards have different PCIe cpu addresss assigned by DAW(e.g. 1p server board and D02 board). so here a new dtsi file is added to support pcie dts nodes of D02. This is a temporary solution as pcie node should be put under peripherals node. Obviously we should modify a lot for a formal one. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06PCI: hisi: Bypass SMMU for Hip06 PCIe controllerZhou Wang
SMMU only allocates memory for stream ID 0, however, stream ID sent to SMMU by PCIe controller is BDF of PCIe device, which will bring error. So this patch set Hip06 PCIe controller to bypass SMMU. Signed-off-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
2015-11-06PCI: hisi: Rearchitect the driver to enable multiple SoCs supportGabriele Paoloni
This patch re-architects the driver to support cleanly multiple SoCs: - Now there is a structure of function pointers that is specific to each SoC - Each SoC will implement its SoCs specific functions in a separate file The patch has been tested on D02 with a Mellanox MCX312B-XCCT It needs to be tested on Hip06 eval board Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
2015-11-06PCI: hisi: Add Hip06 PCIe host bridge supportGabriele Paoloni
This patch adds support for Hi1610 SoC Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
2015-11-06PCI: hisi: pass msi controller address by DTGabriele Paoloni
This patch reworks the code in order to get the address of the MSI controller from DT. This is needed to make the code cleaner as we are going to support multiple SoCs Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
2015-11-06dts bindings:hisilicon-pcie.txtGabriele Paoloni
add pcie pcs base and serdes base description Signed-off-by: liudongdong <liudongdong3@huawei.com>
2015-11-06PCI: hisi:add link functionGabriele Paoloni
1. add pcie link function 2. enable DFE when pcie link to GEN3 3. Fix gen3 equalization configure error Signed-off-by: liudongdong <liudongdong3@huawei.com> Signed-off-by: zhangjukuo <zhangjukuo@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
2015-11-06PCIE-HISI: fix the clear vmid and asid failed bugqiuzhenfa
we need to init the vmid and asid tables as 0 for p660, in fact, the hisi_pcie_config_context function can not clear the ram as the vmid and asid tables, we need to enable the options by setting ctrl20 reg. Signed-off-by: qiuzhenfa <qiuzhenfa@hisilicon.com> [hj: fix two trailing whitespace] Tested-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: hisi: add own wr_own_confgabriele paoloni
This patch implements HiSilicon own implementation of wr_own_conf in pcie_host_ops. PCI memory mapped configuration registers in Hisilicon SoCs can only be accessed by 32b memory read/write. Therefore the default implementation of dw_pcie_cfg_write() will not work with size equal to 1 byte or 2 bytes. Thus here we provide our own implementation that always reads memory using a 32b memory accesse, then adjusts the value according to what we want to write and finally writes the memory back using a 32b memory access Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: liudongdong <liudongdong3@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: hisi: use subsys_initcall for hisi pcie initKefeng Wang
Some pcie device drivers like vgaarb probe very early, so the pcie host driver should initialize earlier, use subsys_initcall instead of module_platform_driver. Cc: liudongdong <liudongdong3@huawei.com> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com> CC: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: hisi: refectoring and solve bar0 assigned failedliudongdong
Solve the problem of bar0 assigned failed. Port it to hulk-4.1 Signed-off-by: liudongdong <liudongdong3@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05Zhou Wang
This patch adds PCIe host support for HiSilicon SoC Hip05. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: designware: Add ARM64 supportZhou Wang
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci, move related operations to dw_pcie_host_init. This patch also try to use of_pci_get_host_bridge_resources for ARM32 and ARM64 according to the suggestion for Gabriele[1] Finally this patch reverts commit f4c55c5a3f7f "PCI: designware: Program ATU with untranslated address" based on 1/6 in this series. we delete *_mod_base in pcie-designware. This was discussed in [2] I have compiled the driver with multi_v7_defconfig. However, I don't have ARM32 PCIe related board to do test. It will be appreciated if someone could help to test it. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-By: James Morse <james.morse@arm.com> [1] http://www.spinics.net/lists/linux-pci/msg42194.html [2] http://www.spinics.net/lists/arm-kernel/msg436779.html Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: designware: move calculation of bus addresses to DRA7xxgabriele paoloni
Commit f4c55c5a3f7f "PCI: designware: Program ATU with untranslated address" added the calculation of PCI BUS addresses in designware, storing them in new fields added in "struct pcie_port". This calculation is done for every designware user even if is only applicable to DRA7xx. This patch moves the calculation of the bus addresses to the DRA7xx driver and is needed to allow the rework of designware to use the new DT parsing API. Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEMJisheng Zhang
Most transactions' type are cfg0 and MEM, so the current iATU usage is not balanced: iATU0 is hot while iATU1 is rarely used. Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM. This allocation idea comes from Minghuan Lian <Minghuan.Lian@freescale.com>: [bhelgaas: use link with Message-ID] Link: http://lkml.kernel.org/r/1429091315-31891-3-git-send-email-Minghuan.Lian@freescale.com Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: designware: Consolidate outbound iATU programming functionsJisheng Zhang
Currently, the outbound iATU programming functions are similar: the only difference is index, type, addr and size. Consolidate these functions into one. This saves about 1700 bytes in text: text data bss dec hex filename 9276 204 4 9484 250c pcie-designware.o-before 7532 204 4 7740 1e3c pcie-designware.o Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: designware: Add support for x8 linksZhou Wang
Add support for x8 links. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: remove hisi PCIe supportZhou Wang
This patch just remove PCIe support in hulk-4.1, make a preparation to apply PCIe patchs from community: http://www.spinics.net/lists/linux-pci/msg44192.html Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: PCIe HiSi: Fix drivers/pci/host/KconfigGabriele Paoloni
This patch: - adds dependency on ARM64 - selects PCIEPORTBUS - adds help menu Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06hulk: fix the config name for hisi pcie driversDing Tianhong
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06pcie: fix the warming for pcie drivers.Ding Tianhong
WARNING: drivers/built-in.o(.data+0x26e8): Section mismatch in reference from the variable hisi_pcie_driver to the function .init.text:hisi_pcie_probe() The variable hisi_pcie_driver references the function __init hisi_pcie_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06pcie: auto match of mpswangyufen
Signed-off-by: Jukuo Zhang <zhangjukuo@huawei.com> Signed-off-by: wangyufen <wangyufen@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06pcie: setting of the Directed Speed Change fieldwangyufen
Signed-off-by: Jukuo Zhang <zhangjukuo@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06check reg status to confirm resetJukuo Zhang
Signed-off-by: Jukuo Zhang <zhangjukuo@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06pcie: add 1s delay between link and enumerationwangyufen
Signed-off-by: Jukuo Zhang <zhangjukuo@huawei.com> Signed-off-by: wangyufen <wangyufen@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06pcie: designware: auto matches MPSJukuo Zhang
Signed-off-by: Jukuo Zhang <zhangjukuo@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06pcie: hisi: bugfix for gen3Kefeng Wang
To support lsi megaraid 2208 card. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06PCI: hisilicon: Add equalization and pcs init codeZhou Wang
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06PCI: host: Add PCIe host bridge support for hisiliconZhou Wang
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06PCI: designware: Add ARM64 supportZhou Wang
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
2015-11-06Documentation: DT: Add HiSilicon PCIe host bindingZhou Wang
This patch adds related DTS binding document for HiSilicon PCIe host driver. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
2015-11-06PCI: Delete Hip05 PCIe supportSherlock Wang
This patch removes all Hip05 PCIe support. Let us start with a clear directory. We will add Hip05/Hip06 PCIe patchset based on this commit for Estuary. Signed-off-by: Sherlock Wang <sherlock.wang@139.com>
2015-11-06Merge pull request #7 from flyingnosky/masterflyingnosky
hisi_sas: error handler for p660 and fix compile bug when enable SAS_12G
2015-11-06HISI_SAS:fix compile error when enable SAS_12Gflyingnosky
modify the name of function serdes_lane_reset to function serdes_lane_reset_v1_hw the name of function phy_rx_eye_diag_done to function phy_rx_eye_diag_done_v1_hw Signed-off-by: chenxiang <chenxiang66@hisilicon.com>
2015-11-06hisi_sas: improve error handler for p660 and hi1610flyingnosky
add error handler process for p660 and hi1610 Signed-off-by:chenxiang <chenxiang66@hisilicon.com>
2015-11-05Enabled Docker related kernel featuresshameer
Signed-off-by: shameer <shamiali2008@gmail.com>
2015-11-05Merge pull request #5 from kongzizaixian/masterkongzizaixian
estuary: add hikey min systerm
2015-11-05arm64: dts: Add dts files for Hisilicon Hi6220 SoC and HiKey boardBintian Wang
Add initial dtsi file to support Hisilicon Hi6220 SoC with support of Octal core CPUs in two clusters and each cluster has quard Cortex-A53. Also add dts file to support HiKey development board which is based on Hi6220 SoC. These dts files will be changed later and more nodes will be added to describe other devices. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Yiping Xu <xuyiping@hisilicon.com> Signed-off-by: John Stultz <john.stultz@linaro.org>
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