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| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2019-10-17 13:23:52 +0000 |
|---|---|---|
| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2019-10-17 13:23:52 +0000 |
| commit | c6112ca950563021561b1b46172bf92e83752067 (patch) | |
| tree | f6350632f43285714ca4ca45428d2d9eb4e72ad4 /gcc/testsuite/gcc.target/aarch64/sve2/eor3_1.c | |
| parent | 744b14b137cecf5f6523a10a4e4eb4d2f2d4967f (diff) | |
[AArch64][SVE2] Support for EOR3 and variants of BSL
2019-10-17 Yuliang Wang <yuliang.wang@arm.com>
gcc/
* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
(aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
(aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
(aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
New combine patterns.
* config/aarch64/iterators.md (BSL_DUP): New int iterator for the
above.
(bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.
gcc/testsuite/
* gcc.target/aarch64/sve2/eor3_1.c: New test.
* gcc.target/aarch64/sve2/nlogic_1.c: As above.
* gcc.target/aarch64/sve2/nlogic_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_1.c: As above.
* gcc.target/aarch64/sve2/bitsel_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_3.c: As above.
* gcc.target/aarch64/sve2/bitsel_4.c: As above.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@277110 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/gcc.target/aarch64/sve2/eor3_1.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve2/eor3_1.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/eor3_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/eor3_1.c new file mode 100644 index 00000000000..13df93e56b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/eor3_1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details --save-temps" } */ + +#define OP(x,y,z) ((x) ^ (y) ^ (z)) + +#include "bitsel_1.c" + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ + +/* { dg-final { scan-assembler-not {\teor\tz[0-9]+\.[bhsd]} } } */ + +/* { dg-final { scan-assembler-times {\teor3\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ |