* config/i386/i386.md (R8_REG, R9_REG): New constants.

	* config/i386/i386.h (CONDITIONAL_REGISTER_USAGE): Use named
	constants instead of magic numbers.
	(HARD_REGNO_CALLER_SAVE_MODE): Ditto.
	(QI_REG_P): Ditto.
	* config/i386/i386.c (x86_64_int_parameter_registers): Ditto.
	(x86_64_ms_abi_int_parameter_registers): Ditto.
	(x86_64_int_return_registers): Ditto.
	(ix86_expand_call): Ditto for clobbered_registers array.
	(ix86_hard_regno_mode_ok): Ditto.
	(x86_extended_QIreg_mentioned_p): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@144638 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 58 insertions, 37 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3f66fef7068..d2629d61ddf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,20 @@
+2009-03-05  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (R8_REG, R9_REG): New constants.
+	* config/i386/i386.h (CONDITIONAL_REGISTER_USAGE): Use named
+	constants instead of magic numbers.
+	(HARD_REGNO_CALLER_SAVE_MODE): Ditto.
+	(QI_REG_P): Ditto.
+	* config/i386/i386.c (x86_64_int_parameter_registers): Ditto.
+	(x86_64_ms_abi_int_parameter_registers): Ditto.
+	(x86_64_int_return_registers): Ditto.
+	(ix86_expand_call): Ditto for clobbered_registers array.
+	(ix86_hard_regno_mode_ok): Ditto.
+	(x86_extended_QIreg_mentioned_p): Ditto.
+
 2009-03-05  J"orn Rennecke  <joern.rennecke@arc.com>
 
-	PR tree-optimization/39349:
+	PR tree-optimization/39349
 	* cse.c (cse_insn): Fix loop to stop at VOIDmode.
 
 	* combine.c (gen_lowpart_for_combine): Use omode when generating
@@ -8,7 +22,7 @@
 
 2009-03-04  J"orn Rennecke  <joern.rennecke@arc.com>
 
-	PR rtl-optimization/39235:
+	PR rtl-optimization/39235
 	* loop-iv.c (get_simple_loop_desc): Use XCNEW.
 
 2009-03-04  Zdenek Dvorak  <ook@ucw.cz>
@@ -110,10 +124,10 @@
 
 	* config/i386/i386.md (ST?_REG, MM?_REG): New constants.
 	(*call_1_rex64_ms_sysv): Use named constants instead of magic
-	numbers to describe clobbbered registers.
+	numbers to describe clobbered registers.
 	(*call_value_0_rex64_ms_sysv): Ditto.
-	* config/i386/mmx.md (emms): Ditto.
-	(femms): Ditto.
+	* config/i386/mmx.md (mmx_emms): Ditto.
+	(mmx_femms): Ditto.
 
 2009-03-02  Richard Sandiford  <rdsandiford@googlemail.com>
 
@@ -321,7 +335,7 @@
 
 	PR tree-optimization/39259
 	* tree-inline.c (initialize_cfun): Remove asserts for calls_setjmp and
-	alls_alloca function flags.
+	calls_alloca function flags.
 	(copy_bb): Set calls_setjmp and alls_alloca function flags if such
 	calls are detected.
 
@@ -714,7 +728,7 @@
 
 	PR target/39149
 	* config/i386/i386.c (override_options): Correct warning
-	messages for -malign-loops,  -malign-jumps and -malign-functions.
+	messages for -malign-loops, -malign-jumps and -malign-functions.
 
 2009-02-13  H.J. Lu  <hongjiu.lu@intel.com>
 
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 120ab156fb1..4f7f943819d 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1533,24 +1533,8 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
   -1, -1, -1, -1, -1, -1, -1, -1,	/* extended SSE registers */
 };
 
-static int const x86_64_int_parameter_registers[6] =
-{
-  5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
-  FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
-};
-
-static int const x86_64_ms_abi_int_parameter_registers[4] =
-{
-  2 /*RCX*/, 1 /*RDX*/,
-  FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
-};
-
-static int const x86_64_int_return_registers[4] =
-{
-  0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
-};
-
 /* The "default" register map used in 64bit mode.  */
+
 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 1, 2, 3, 4, 5, 6, 7,		/* general regs */
@@ -1634,6 +1618,23 @@ rtx ix86_compare_op0 = NULL_RTX;
 rtx ix86_compare_op1 = NULL_RTX;
 rtx ix86_compare_emitted = NULL_RTX;
 
+/* Define parameter passing and return registers.  */
+
+static int const x86_64_int_parameter_registers[6] =
+{
+  DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
+};
+
+static int const x86_64_ms_abi_int_parameter_registers[4] =
+{
+  CX_REG, DX_REG, R8_REG, R9_REG
+};
+
+static int const x86_64_int_return_registers[4] =
+{
+  AX_REG, DX_REG, DI_REG, SI_REG
+};
+
 /* Define the structure for the machine field in struct function.  */
 
 struct stack_local_entry GTY(())
@@ -18684,8 +18685,12 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
      by SYSV calls.  */
   if (ix86_cfun_abi () == MS_ABI && function_call_abi == SYSV_ABI)
     {
-      static int clobbered_registers[] = {27, 28, 45, 46, 47, 48, 49, 50, 51,
-      					  52, SI_REG, DI_REG};
+      static int clobbered_registers[] = {
+	XMM6_REG, XMM7_REG, XMM8_REG,
+	XMM9_REG, XMM10_REG, XMM11_REG,
+	XMM12_REG, XMM13_REG, XMM14_REG,
+	XMM15_REG, SI_REG, DI_REG
+      };
       unsigned int i;
       rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
       rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
@@ -25757,7 +25762,7 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
     {
       /* Take care for QImode values - they can be in non-QI regs,
 	 but then they do cause partial register stalls.  */
-      if (regno < 4 || TARGET_64BIT)
+      if (regno <= BX_REG || TARGET_64BIT)
 	return 1;
       if (!TARGET_PARTIAL_REG_STALL)
 	return 1;
@@ -26869,7 +26874,7 @@ x86_extended_QIreg_mentioned_p (rtx insn)
   extract_insn_cached (insn);
   for (i = 0; i < recog_data.n_operands; i++)
     if (REG_P (recog_data.operand[i])
-	&& REGNO (recog_data.operand[i]) >= 4)
+	&& REGNO (recog_data.operand[i]) > BX_REG)
        return true;
   return false;
 }
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 5bdf379bca0..f2f4448d15e 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -938,10 +938,10 @@ do {									\
 	&& ((cfun && cfun->machine->call_abi == MS_ABI)			\
 	    || (!cfun && DEFAULT_ABI == MS_ABI)))			\
       {									\
-	call_used_regs[4 /*RSI*/] = 0;					\
-	call_used_regs[5 /*RDI*/] = 0;					\
-	call_used_regs[27 /*XMM6*/] = 0;				\
-	call_used_regs[28 /*XMM7*/] = 0;				\
+	call_used_regs[SI_REG] = 0;					\
+	call_used_regs[DI_REG] = 0;					\
+	call_used_regs[XMM6_REG] = 0;					\
+	call_used_regs[XMM7_REG] = 0;					\
 	for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)		\
 	  call_used_regs[i] = 0;					\
       }									\
@@ -1073,7 +1073,7 @@ do {									\
    : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode			\
    : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
    : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode		\
-   : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode 	\
+   : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode 	\
    : (MODE))
 
 /* Specify the registers used for certain standard purposes.
@@ -1310,7 +1310,7 @@ enum reg_class
 
 #define SMALL_REGISTER_CLASSES 1
 
-#define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
+#define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG)
 
 #define GENERAL_REGNO_P(N) \
   ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
@@ -1508,7 +1508,8 @@ enum reg_class
    prologue and apilogue.  This is not possible without
    ACCUMULATE_OUTGOING_ARGS.  */
 
-#define ACCUMULATE_OUTGOING_ARGS (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI)
+#define ACCUMULATE_OUTGOING_ARGS \
+  (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI)
 
 /* If defined, a C expression whose value is nonzero when we want to use PUSH
    instructions to pass outgoing arguments.  */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9c6ae1c12a6..761a5e70c68 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -291,6 +291,8 @@
    (MM5_REG			34)
    (MM6_REG			35)
    (MM7_REG			36)
+   (R8_REG			37)
+   (R9_REG			38)
    (R10_REG			39)
    (R11_REG			40)
    (R13_REG			42)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dfeb6fdb810..fc15129ffc6 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -53,8 +53,7 @@
 2009-03-03  Ira Rosen  <irar@il.ibm.com>
 
 	PR tree-optimization/39248
-	* gcc.dg/vect/vect-complex-1.c: Add attribute aligned
-	to the arrays.
+	* gcc.dg/vect/vect-complex-1.c: Add attribute aligned to the arrays.
 	* gcc.dg/vect/vect-iv-6.c: Don't expect to fail to vectorize
 	on targets without vector misalignment support.
 	* lib/target-supports.exp