diff options
Diffstat (limited to 'gcc/config/h8300/h8300.md')
| -rw-r--r-- | gcc/config/h8300/h8300.md | 51 |
1 files changed, 19 insertions, 32 deletions
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index a94a5ad55b2..7e49af5ef75 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -81,6 +81,12 @@ (const_int 6)))] (const_int 200))) +;; The necessity of instruction length adjustment. + +(define_attr "adjust_length" "yes,no" + (cond [(eq_attr "type" "branch") (const_string "no")] + (const_string "yes"))) + ;; Condition code settings. ;; none - insn does not affect cc ;; none_0hit - insn does not affect cc but it does modify operand 0 @@ -983,6 +989,7 @@ and %X2,%X0 bclr %W2,%R0" [(set_attr "length" "2,4") + (set_attr "adjust_length" "no") (set_attr "cc" "set_znv,none_0hit")]) (define_expand "andqi3" @@ -1087,6 +1094,7 @@ or %X2,%X0 bset %V2,%R0" [(set_attr "length" "2,4") + (set_attr "adjust_length" "no") (set_attr "cc" "set_znv,none_0hit")]) (define_expand "iorqi3" @@ -1173,6 +1181,7 @@ xor %X2,%X0 bnot %V2,%R0" [(set_attr "length" "2,4") + (set_attr "adjust_length" "no") (set_attr "cc" "set_znv,none_0hit")]) (define_expand "xorqi3" @@ -1687,15 +1696,17 @@ "TARGET_H8300" "") +;; %e prints the high part of a CONST_INT, not the low part. Arggh. (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))] + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))] "TARGET_H8300" "@ sub.w %e0,%e0 + mov.w %f1,%f0\;sub.w %e0,%e0 mov.w %e1,%f0\;sub.w %e0,%e0" - [(set_attr "length" "2,4") - (set_attr "cc" "clobber,clobber")]) + [(set_attr "length" "2,4,4") + (set_attr "cc" "clobber,clobber,clobber")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -2224,7 +2235,8 @@ "" "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1" [(set_attr "cc" "clobber") - (set_attr "length" "6")]) + (set_attr "length" "6") + (set_attr "adjust_length" "no")]) (define_insn "" [(set (match_operand:HI 0 "bit_operand" "=Ur") @@ -2238,39 +2250,14 @@ "" "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3" [(set_attr "cc" "clobber") - (set_attr "length" "6")]) + (set_attr "length" "6") + (set_attr "adjust_length" "no")]) ;; ---------------------------------------------- ;; Peepholes go at the end. ;; ---------------------------------------------- -;; Notice when two byte moves in a row could be a word move. - -(define_peephole - [(set (match_operand:QI 0 "register_operand" "=r") - (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r") - (match_operand:HI 2 "immediate_operand" "n")))) - (set (match_operand:QI 3 "register_operand" "=r") - (mem:QI (plus:HI (match_dup 1) - (match_operand:HI 4 "immediate_operand" "n"))))] - "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])" - "mov.w @(%u4,%T1),%T0" - [(set_attr "length" "6") - (set_attr "cc" "set_znv")]) - -(define_peephole - [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r") - (match_operand:HI 2 "immediate_operand" "n"))) - (match_operand:QI 0 "register_operand" "r")) - (set (mem:QI (plus:HI (match_dup 1) - (match_operand:HI 4 "immediate_operand" "n"))) - (match_operand:QI 3 "register_operand" "r"))] - "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])" - "mov.w %T0,@(%u4,%T1)" - [(set_attr "length" "6") - (set_attr "cc" "set_znv")]) - ;; Notice a move which could be post incremented. (define_peephole |