diff options
Diffstat (limited to 'gcc/config/m68k/m68k.md')
| -rw-r--r-- | gcc/config/m68k/m68k.md | 279 |
1 files changed, 121 insertions, 158 deletions
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index dfe0cbc313e..236bd9a0062 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -1,5 +1,5 @@ ;;- Machine description for GNU compiler, Motorola 68000 Version -;; Copyright (C) 1987, 88, 93-97, 1998 Free Software Foundation, Inc. +;; Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc. ;; This file is part of GNU CC. @@ -1224,8 +1224,8 @@ }") (define_insn "" - [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f") - (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))] + [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r") + (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))] "TARGET_68881" "* { @@ -1247,15 +1247,20 @@ return \"fmove%.x %1,%0\"; return \"fmove%.x %f1,%0\"; } - if (REG_P (operands[0])) + if (FP_REG_P (operands[1])) { - output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); - operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - output_asm_insn (\"move%.l %+,%0\", operands); - operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - return \"move%.l %+,%0\"; + if (REG_P (operands[0])) + { + output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); + operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); + output_asm_insn (\"move%.l %+,%0\", operands); + operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); + return \"move%.l %+,%0\"; + } + /* Must be memory destination. */ + return \"fmove%.x %f1,%0\"; } - return \"fmove%.x %f1,%0\"; + return output_move_double (operands); } ") @@ -1670,8 +1675,7 @@ (define_insn "extendqidi2" [(set (match_operand:DI 0 "general_operand" "=d") - (sign_extend:DI - (match_operand:QI 1 "general_operand" "rm")))] + (sign_extend:DI (match_operand:QI 1 "general_operand" "dm")))] "" "* { @@ -2099,7 +2103,7 @@ ;; (plus:DI (match_operand:DI 2 "general_operand" "%0") ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro") ;; (const_int 32))))] - (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "o,r") + (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r") (const_int 32)) (match_operand:DI 2 "general_operand" "0,0")))] "" @@ -2118,7 +2122,7 @@ ;; (plus:DI (match_operand:DI 2 "general_operand" "%0") ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro") ;; (const_int 32))))] - (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "o,r") + (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r") (const_int 32)) (match_operand:DI 2 "general_operand" "0,0")))] "" @@ -4558,9 +4562,10 @@ [(set (match_operand:DI 0 "general_operand" "=d") (ashift:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) - || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 - || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" + "(!TARGET_5200 + && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) + || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 + || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" "* { operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); @@ -4589,13 +4594,15 @@ [(set (match_operand:DI 0 "general_operand" "") (ashift:DI (match_operand:DI 1 "general_operand" "") (match_operand 2 "const_int_operand" "")))] - "" + "!TARGET_5200" " { + /* ??? This is a named pattern like this is not allowed to FAIL based + on its operands. */ if (GET_CODE (operands[2]) != CONST_INT - || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) - && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 - && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) + || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) + && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 + && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) FAIL; } ") @@ -4758,11 +4765,11 @@ [(set (match_operand:DI 0 "general_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "!TARGET_5200 + "(!TARGET_5200 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) - || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 - || INTVAL (operands[2]) == 31 - || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" + || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 + || INTVAL (operands[2]) == 31 + || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" "* { operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); @@ -4801,10 +4808,12 @@ "!TARGET_5200" " { + /* ??? This is a named pattern like this is not allowed to FAIL based + on its operands. */ if (GET_CODE (operands[2]) != CONST_INT - || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) - && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 - && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63))) + || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) + && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 + && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63))) FAIL; } ") @@ -4929,10 +4938,10 @@ [(set (match_operand:DI 0 "general_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "!TARGET_5200 + "(!TARGET_5200 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) - || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 - || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" + || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 + || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" "* { operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); @@ -4967,10 +4976,12 @@ "!TARGET_5200" " { + /* ??? This is a named pattern like this is not allowed to FAIL based + on its operands. */ if (GET_CODE (operands[2]) != CONST_INT - || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) - && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 - && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) + || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) + && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 + && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) FAIL; } ") @@ -5663,8 +5674,12 @@ return output_scc_di (operands[1], operands[2], operands[3], operands[0]); } ") +;; Note that operand 0 of an SCC insn is supported in the hardware as +;; memory, but we cannot allow it to be in memory in case the address +;; needs to be reloaded. + (define_expand "seq" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (eq:QI (cc0) (const_int 0)))] "" " @@ -5677,25 +5692,16 @@ }") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (eq:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* - cc_status = cc_prev_status; - OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); -") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (eq:QI (cc0) (const_int 0)))] - "TARGET_5200" + "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); ") (define_expand "sne" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (ne:QI (cc0) (const_int 0)))] "" " @@ -5708,25 +5714,16 @@ }") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (ne:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* - cc_status = cc_prev_status; - OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); -") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (ne:QI (cc0) (const_int 0)))] - "TARGET_5200" + "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); ") (define_expand "sgt" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (gt:QI (cc0) (const_int 0)))] "" " @@ -5739,45 +5736,30 @@ }") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (gt:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* - cc_status = cc_prev_status; - OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0); -") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (gt:QI (cc0) (const_int 0)))] - "TARGET_5200" + "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0); ") (define_expand "sgtu" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (gtu:QI (cc0) (const_int 0)))] "" "") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (gtu:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* cc_status = cc_prev_status; - return \"shi %0\"; ") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (gtu:QI (cc0) (const_int 0)))] - "TARGET_5200" - "* cc_status = cc_prev_status; - return \"shi %0\"; ") + "" + "* + cc_status = cc_prev_status; + return \"shi %0\"; ") (define_expand "slt" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (lt:QI (cc0) (const_int 0)))] "" " @@ -5790,41 +5772,29 @@ }") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (lt:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* cc_status = cc_prev_status; - OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (lt:QI (cc0) (const_int 0)))] - "TARGET_5200" - "* cc_status = cc_prev_status; - OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") + "" + "* + cc_status = cc_prev_status; + OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") (define_expand "sltu" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (ltu:QI (cc0) (const_int 0)))] "" "") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (ltu:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* cc_status = cc_prev_status; - return \"scs %0\"; ") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (ltu:QI (cc0) (const_int 0)))] - "TARGET_5200" - "* cc_status = cc_prev_status; - return \"scs %0\"; ") + "" + "* + cc_status = cc_prev_status; + return \"scs %0\"; ") (define_expand "sge" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (ge:QI (cc0) (const_int 0)))] "" " @@ -5837,41 +5807,29 @@ }") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (ge:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* cc_status = cc_prev_status; - OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (ge:QI (cc0) (const_int 0)))] - "TARGET_5200" - "* cc_status = cc_prev_status; - OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") + "" + "* + cc_status = cc_prev_status; + OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") (define_expand "sgeu" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (geu:QI (cc0) (const_int 0)))] "" "") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (geu:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* cc_status = cc_prev_status; - return \"scc %0\"; ") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (geu:QI (cc0) (const_int 0)))] - "TARGET_5200" - "* cc_status = cc_prev_status; - return \"scc %0\"; ") + "" + "* + cc_status = cc_prev_status; + return \"scc %0\"; ") (define_expand "sle" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (le:QI (cc0) (const_int 0)))] "" " @@ -5884,42 +5842,27 @@ }") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (le:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* - cc_status = cc_prev_status; - OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0); -") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (le:QI (cc0) (const_int 0)))] - "TARGET_5200" + "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0); ") (define_expand "sleu" - [(set (match_operand:QI 0 "general_operand" "") + [(set (match_operand:QI 0 "register_operand" "") (leu:QI (cc0) (const_int 0)))] "" "") (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=dm") - (leu:QI (cc0) (const_int 0)))] - "! TARGET_5200" - "* cc_status = cc_prev_status; - return \"sls %0\"; ") - -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=d") + [(set (match_operand:QI 0 "register_operand" "=d") (leu:QI (cc0) (const_int 0)))] - "TARGET_5200" - "* cc_status = cc_prev_status; - return \"sls %0\"; ") + "" + "* + cc_status = cc_prev_status; + return \"sls %0\"; ") ;; Basic conditional jump instructions. @@ -7492,7 +7435,7 @@ (define_insn "extendsfxf2" [(set (match_operand:XF 0 "general_operand" "=fm,f") - (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))] + (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))] "TARGET_68881" "* { @@ -7509,7 +7452,15 @@ return \"f%$move%.x %1,%0\"; } if (FP_REG_P (operands[0])) - return \"f%$move%.s %f1,%0\"; + { + if (FP_REG_P (operands[1])) + return \"f%$move%.x %1,%0\"; + else if (ADDRESS_REG_P (operands[1])) + return \"move%.l %1,%-\;f%$move%.s %+,%0\"; + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + return \"f%$move%.s %f1,%0\"; + } return \"fmove%.x %f1,%0\"; }") @@ -7517,7 +7468,7 @@ (define_insn "extenddfxf2" [(set (match_operand:XF 0 "general_operand" "=fm,f") (float_extend:XF - (match_operand:DF 1 "general_operand" "f,m")))] + (match_operand:DF 1 "general_operand" "f,rmE")))] "TARGET_68881" "* { @@ -7534,7 +7485,19 @@ return \"fmove%.x %1,%0\"; } if (FP_REG_P (operands[0])) - return \"f%&move%.d %f1,%0\"; + { + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"move%.l %1,%-\", xoperands); + output_asm_insn (\"move%.l %1,%-\", operands); + return \"f%&move%.d %+,%0\"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_double (operands); + return \"f%&move%.d %f1,%0\"; + } return \"fmove%.x %f1,%0\"; }") |