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-rw-r--r--gcc/doc/invoke.texi16
1 files changed, 12 insertions, 4 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 25f6ec4ef17..250f1358b20 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -8587,8 +8587,8 @@ count register BK@.
Enable (disable) generation of code using decrement and branch,
DBcond(D), instructions. This is enabled by default for the C4x. To be
on the safe side, this is disabled for the C3x, since the maximum
-iteration count on the C3x is @math{2^{23} + 1} (but who iterates loops more than
-@math{2^{23}} times on the C3x?). Note that GCC will try to reverse a loop so
+iteration count on the C3x is @math{2^23 + 1} (but who iterates loops more than
+@math{2^23} times on the C3x?). Note that GCC will try to reverse a loop so
that it can utilise the decrement and branch instruction, but will give
up if there is more than one memory reference in the loop. Thus a loop
where the loop counter is decremented can generate slightly more
@@ -8656,9 +8656,9 @@ instruction, it is disabled by default.
@opindex mloop-unsigned
@opindex mno-loop-unsigned
The maximum iteration count when using RPTS and RPTB (and DB on the C40)
-is @math{2^{31} + 1} since these instructions test if the iteration count is
+is @math{2^31 + 1} since these instructions test if the iteration count is
negative to terminate the loop. If the iteration count is unsigned
-there is a possibility than the @math{2^{31} + 1} maximum iteration count may be
+there is a possibility than the @math{2^31 + 1} maximum iteration count may be
exceeded. This switch allows an unsigned iteration count.
@item -mti
@@ -9210,6 +9210,14 @@ A fixed register is one that the register allocator can not use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
+
+@item -mearly-stop-bits
+@itemx -mno-early-stop-bits
+@opindex mearly-stop-bits
+@opindex mno-early-stop-bits
+Allow stop bits to be placed earlier than immediately preceding the
+instruction that triggered the stop bit. This can improve instruction
+scheduling, but does not always do so.
@end table
@node D30V Options