aboutsummaryrefslogtreecommitdiff
path: root/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c
blob: 0bd326a879d8294f7b75c5ff32a1a2bc904c5bfc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
/* { dg-do compile } */
/* { dg-options "-O2" } */

/* The integer variable shift and rotate instructions truncate their
   shift amounts by the datasize.  Make sure that we don't emit a redundant
   masking operation.  */

unsigned
f1 (unsigned x, int y)
{
  return x << (y & 31);
}

unsigned long long
f2 (unsigned long long x, int y)
{
  return x << (y & 63);
}

unsigned long long
f3 (unsigned long long bit_addr, int y)
{
  unsigned long bitnumb = bit_addr & 63;
  return (1LL << bitnumb);
}

unsigned int
f4 (unsigned int x, unsigned int y)
{
  y &= 31;
  return x >> y | (x << (32 - y));
}

unsigned long long
f5 (unsigned long long x, unsigned long long y)
{
  y &= 63;
  return x >> y | (x << (64 - y));
}

unsigned int
f6 (unsigned int x, unsigned int y)
{
  return (x << (32 - (y & 31)));
}

unsigned long long
f7 (unsigned long long x, unsigned long long y)
{
  return (x << (64 - (y & 63)));
}

unsigned long long
f8 (unsigned long long x, unsigned long long y)
{
  return (x << -(y & 63));
}

/* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
/* { dg-final { scan-assembler-times "lsl\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 4 } } */
/* { dg-final { scan-assembler-times "ror\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "ror\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-not "and\tw\[0-9\]+, w\[0-9\]+, 31" } } */
/* { dg-final { scan-assembler-not "and\tx\[0-9\]+, x\[0-9\]+, 63" } } */
/* { dg-final { scan-assembler-not "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */