diff options
| author | Gary Funck <gary@intrepid.com> | 2016-07-16 17:57:33 +0000 |
|---|---|---|
| committer | Gary Funck <gary@intrepid.com> | 2016-07-16 17:57:33 +0000 |
| commit | 3f0c687f86f0480fe042244ecbcadaa0a4f313fc (patch) | |
| tree | 7a9c3e6b0cd8538944582828d38a3468032f9221 | |
| parent | b7c339a37ce3ab2ef8f2fef17d6c6e8779a866c2 (diff) | |
| parent | b1a2f7b8ad5fa3d9916fbd0d8f5228abc8d9f279 (diff) | |
Merge GCC 6.0 version 238402 into gupc-6-branch.gupc-6-branch
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/gupc-6-branch@238415 138bc75d-0d04-0410-961f-82ee72b054a4
422 files changed, 14169 insertions, 1185 deletions
diff --git a/fixincludes/ChangeLog b/fixincludes/ChangeLog index a44e1308c55..c15fc033a32 100644 --- a/fixincludes/ChangeLog +++ b/fixincludes/ChangeLog @@ -1,3 +1,18 @@ +2016-06-15 David Edelsohn <dje.gcc@gmail.com> + + Backport from mainline + 2016-06-13 David Edelsohn <dje.gcc@gmail.com> + + * inclhack.def (aix_stdlib_malloc): New fix. + (aix_stdlib_realloc): New fix. + (aix_stdlib_calloc): New fix. + (aix_stdlib_valloc): New fix. + * fixincl.x: Regenerate. + * tests/base/stdlib.h [AIX_STDLIB_MALLOC]: New test. + [AIX_STDLIB_REALLOC]: New test. + [AIX_STDLIB_CALLOC]: New test. + [AIX_STDLIB_VALLOC]: New test. + 2016-04-27 Release Manager * GCC 6.1.0 released. diff --git a/fixincludes/fixincl.x b/fixincludes/fixincl.x index 38338117690..c79a6e4fb2c 100644 --- a/fixincludes/fixincl.x +++ b/fixincludes/fixincl.x @@ -2,11 +2,11 @@ * * DO NOT EDIT THIS FILE (fixincl.x) * - * It has been AutoGen-ed Sunday January 31, 2016 at 07:52:05 PM EST + * It has been AutoGen-ed June 10, 2016 at 12:56:52 PM by AutoGen 5.18.3 * From the definitions inclhack.def * and the template file fixincl */ -/* DO NOT SVN-MERGE THIS FILE, EITHER Sun 31 Jan 2016 19:52:05 EST +/* DO NOT SVN-MERGE THIS FILE, EITHER Fri Jun 10 12:56:52 UTC 2016 * * You must regenerate it. Use the ./genfixes script. * @@ -15,7 +15,7 @@ * certain ANSI-incompatible system header files which are fixed to work * correctly with ANSI C and placed in a directory that GNU C will search. * - * This file contains 231 fixup descriptions. + * This file contains 235 fixup descriptions. * * See README for more information. * @@ -1547,6 +1547,154 @@ static const char* apzAix_Stdio_InlinePatch[] = { /* * * * * * * * * * * * * * * * * * * * * * * * * * * + * Description of Aix_Stdlib_Malloc fix + */ +tSCC zAix_Stdlib_MallocName[] = + "aix_stdlib_malloc"; + +/* + * File name selection pattern + */ +tSCC zAix_Stdlib_MallocList[] = + "stdlib.h\0"; +/* + * Machine/OS name selection pattern + */ +tSCC* apzAix_Stdlib_MallocMachs[] = { + "*-*-aix*", + (const char*)NULL }; + +/* + * content selection pattern - do fix if pattern found + */ +tSCC zAix_Stdlib_MallocSelect0[] = + "#define[ \t]+malloc[ \t]+__linux_malloc"; + +#define AIX_STDLIB_MALLOC_TEST_CT 1 +static tTestDesc aAix_Stdlib_MallocTests[] = { + { TT_EGREP, zAix_Stdlib_MallocSelect0, (regex_t*)NULL }, }; + +/* + * Fix Command Arguments for Aix_Stdlib_Malloc + */ +static const char* apzAix_Stdlib_MallocPatch[] = { + "format", + "extern void *malloc(size_t) __asm__(\"__linux_malloc\");", + (char*)NULL }; + +/* * * * * * * * * * * * * * * * * * * * * * * * * * + * + * Description of Aix_Stdlib_Realloc fix + */ +tSCC zAix_Stdlib_ReallocName[] = + "aix_stdlib_realloc"; + +/* + * File name selection pattern + */ +tSCC zAix_Stdlib_ReallocList[] = + "stdlib.h\0"; +/* + * Machine/OS name selection pattern + */ +tSCC* apzAix_Stdlib_ReallocMachs[] = { + "*-*-aix*", + (const char*)NULL }; + +/* + * content selection pattern - do fix if pattern found + */ +tSCC zAix_Stdlib_ReallocSelect0[] = + "#define[ \t]+realloc[ \t]+__linux_realloc"; + +#define AIX_STDLIB_REALLOC_TEST_CT 1 +static tTestDesc aAix_Stdlib_ReallocTests[] = { + { TT_EGREP, zAix_Stdlib_ReallocSelect0, (regex_t*)NULL }, }; + +/* + * Fix Command Arguments for Aix_Stdlib_Realloc + */ +static const char* apzAix_Stdlib_ReallocPatch[] = { + "format", + "extern void *realloc(void *, size_t) __asm__(\"__linux_realloc\");", + (char*)NULL }; + +/* * * * * * * * * * * * * * * * * * * * * * * * * * + * + * Description of Aix_Stdlib_Calloc fix + */ +tSCC zAix_Stdlib_CallocName[] = + "aix_stdlib_calloc"; + +/* + * File name selection pattern + */ +tSCC zAix_Stdlib_CallocList[] = + "stdlib.h\0"; +/* + * Machine/OS name selection pattern + */ +tSCC* apzAix_Stdlib_CallocMachs[] = { + "*-*-aix*", + (const char*)NULL }; + +/* + * content selection pattern - do fix if pattern found + */ +tSCC zAix_Stdlib_CallocSelect0[] = + "#define[ \t]+calloc[ \t]+__linux_calloc"; + +#define AIX_STDLIB_CALLOC_TEST_CT 1 +static tTestDesc aAix_Stdlib_CallocTests[] = { + { TT_EGREP, zAix_Stdlib_CallocSelect0, (regex_t*)NULL }, }; + +/* + * Fix Command Arguments for Aix_Stdlib_Calloc + */ +static const char* apzAix_Stdlib_CallocPatch[] = { + "format", + "extern void *calloc(size_t, size_t) __asm__(\"__linux_calloc\");", + (char*)NULL }; + +/* * * * * * * * * * * * * * * * * * * * * * * * * * + * + * Description of Aix_Stdlib_Valloc fix + */ +tSCC zAix_Stdlib_VallocName[] = + "aix_stdlib_valloc"; + +/* + * File name selection pattern + */ +tSCC zAix_Stdlib_VallocList[] = + "stdlib.h\0"; +/* + * Machine/OS name selection pattern + */ +tSCC* apzAix_Stdlib_VallocMachs[] = { + "*-*-aix*", + (const char*)NULL }; + +/* + * content selection pattern - do fix if pattern found + */ +tSCC zAix_Stdlib_VallocSelect0[] = + "#define[ \t]+valloc[ \t]+__linux_valloc"; + +#define AIX_STDLIB_VALLOC_TEST_CT 1 +static tTestDesc aAix_Stdlib_VallocTests[] = { + { TT_EGREP, zAix_Stdlib_VallocSelect0, (regex_t*)NULL }, }; + +/* + * Fix Command Arguments for Aix_Stdlib_Valloc + */ +static const char* apzAix_Stdlib_VallocPatch[] = { + "format", + "extern void *valloc(size_t) __asm__(\"__linux_valloc\");", + (char*)NULL }; + +/* * * * * * * * * * * * * * * * * * * * * * * * * * + * * Description of Aix_Strtof_Const fix */ tSCC zAix_Strtof_ConstName[] = @@ -9485,9 +9633,9 @@ static const char* apzX11_SprintfPatch[] = { * * List of all fixes */ -#define REGEX_COUNT 268 +#define REGEX_COUNT 272 #define MACH_LIST_SIZE_LIMIT 187 -#define FIX_COUNT 231 +#define FIX_COUNT 235 /* * Enumerate the fixes @@ -9525,6 +9673,10 @@ typedef enum { AIX_STDINT_4_FIXIDX, AIX_STDINT_5_FIXIDX, AIX_STDIO_INLINE_FIXIDX, + AIX_STDLIB_MALLOC_FIXIDX, + AIX_STDLIB_REALLOC_FIXIDX, + AIX_STDLIB_CALLOC_FIXIDX, + AIX_STDLIB_VALLOC_FIXIDX, AIX_STRTOF_CONST_FIXIDX, AIX_SYSMACHINE_FIXIDX, AIX_SYSWAIT_2_FIXIDX, @@ -9887,6 +10039,26 @@ tFixDesc fixDescList[ FIX_COUNT ] = { AIX_STDIO_INLINE_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, aAix_Stdio_InlineTests, apzAix_Stdio_InlinePatch, 0 }, + { zAix_Stdlib_MallocName, zAix_Stdlib_MallocList, + apzAix_Stdlib_MallocMachs, + AIX_STDLIB_MALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, + aAix_Stdlib_MallocTests, apzAix_Stdlib_MallocPatch, 0 }, + + { zAix_Stdlib_ReallocName, zAix_Stdlib_ReallocList, + apzAix_Stdlib_ReallocMachs, + AIX_STDLIB_REALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, + aAix_Stdlib_ReallocTests, apzAix_Stdlib_ReallocPatch, 0 }, + + { zAix_Stdlib_CallocName, zAix_Stdlib_CallocList, + apzAix_Stdlib_CallocMachs, + AIX_STDLIB_CALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, + aAix_Stdlib_CallocTests, apzAix_Stdlib_CallocPatch, 0 }, + + { zAix_Stdlib_VallocName, zAix_Stdlib_VallocList, + apzAix_Stdlib_VallocMachs, + AIX_STDLIB_VALLOC_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, + aAix_Stdlib_VallocTests, apzAix_Stdlib_VallocPatch, 0 }, + { zAix_Strtof_ConstName, zAix_Strtof_ConstList, apzAix_Strtof_ConstMachs, AIX_STRTOF_CONST_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE, diff --git a/fixincludes/inclhack.def b/fixincludes/inclhack.def index 8b6d1fe3a13..8adb07678bc 100644 --- a/fixincludes/inclhack.def +++ b/fixincludes/inclhack.def @@ -911,6 +911,48 @@ fix = { test_text = "#ifdef __cplusplus\n}\n\n#ifdef ferror"; }; +/* + * stdlib.h on AIX uses #define on malloc and friends. + */ +fix = { + hackname = aix_stdlib_malloc; + mach = "*-*-aix*"; + files = stdlib.h; + select = "#define[ \t]+malloc[ \t]+__linux_malloc"; + c_fix = format; + c_fix_arg = "extern void *malloc(size_t) __asm__(\"__linux_malloc\");"; + test_text = "#define malloc __linux_malloc"; +}; + +fix = { + hackname = aix_stdlib_realloc; + mach = "*-*-aix*"; + files = stdlib.h; + select = "#define[ \t]+realloc[ \t]+__linux_realloc"; + c_fix = format; + c_fix_arg = "extern void *realloc(void *, size_t) __asm__(\"__linux_realloc\");"; + test_text = "#define realloc __linux_realloc"; +}; + +fix = { + hackname = aix_stdlib_calloc; + mach = "*-*-aix*"; + files = stdlib.h; + select = "#define[ \t]+calloc[ \t]+__linux_calloc"; + c_fix = format; + c_fix_arg = "extern void *calloc(size_t, size_t) __asm__(\"__linux_calloc\");"; + test_text = "#define calloc __linux_calloc"; +}; + +fix = { + hackname = aix_stdlib_valloc; + mach = "*-*-aix*"; + files = stdlib.h; + select = "#define[ \t]+valloc[ \t]+__linux_valloc"; + c_fix = format; + c_fix_arg = "extern void *valloc(size_t) __asm__(\"__linux_valloc\");"; + test_text = "#define valloc __linux_valloc"; +}; /* * stdlib.h on AIX 4.3 declares strtof() with a non-const first argument. diff --git a/fixincludes/tests/base/stdlib.h b/fixincludes/tests/base/stdlib.h index 2f91e07636a..cee7e5db413 100644 --- a/fixincludes/tests/base/stdlib.h +++ b/fixincludes/tests/base/stdlib.h @@ -9,6 +9,26 @@ +#if defined( AIX_STDLIB_MALLOC_CHECK ) +extern void *malloc(size_t) __asm__("__linux_malloc"); +#endif /* AIX_STDLIB_MALLOC_CHECK */ + + +#if defined( AIX_STDLIB_REALLOC_CHECK ) +extern void *realloc(void *, size_t) __asm__("__linux_realloc"); +#endif /* AIX_STDLIB_REALLOC_CHECK */ + + +#if defined( AIX_STDLIB_CALLOC_CHECK ) +extern void *calloc(size_t, size_t) __asm__("__linux_calloc"); +#endif /* AIX_STDLIB_CALLOC_CHECK */ + + +#if defined( AIX_STDLIB_VALLOC_CHECK ) +extern void *valloc(size_t) __asm__("__linux_valloc"); +#endif /* AIX_STDLIB_VALLOC_CHECK */ + + #if defined( AIX_STRTOF_CONST_CHECK ) extern float strtof(const char *, char **); #endif /* AIX_STRTOF_CONST_CHECK */ diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e133038851b..6a1b16c408f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,1059 @@ +2016-07-15 Alan Modra <amodra@gmail.com> + + Apply from mainline + 2016-07-11 Alan Modra <amodra@gmail.com> + * config/rs6000/rs6000.md (UNSPEC_DOLOOP): New unspec. + (ctr<mode>): Add unspec. + (ctr<mode>_internal*): Likewise. + +2016-07-14 Alan Modra <amodra@gmail.com> + + PR target/71733 + * config/rs6000/rs6000.c (rs6000_option_override_internal): Deal + with p9_vector override before power9-dform override. + +2016-07-13 Ilya Enkovich <ilya.enkovich@intel.com> + + Backport from mainline r238086. + 2016-07-07 Ilya Enkovich <ilya.enkovich@intel.com> + + PR ipa/71624 + * ipa-inline-analysis.c (compute_inline_parameters): Set + local.can_change_signature to false for intrumentation + thunk callees. + +2016-07-12 Michael Meissner <meissner@linux.vnet.ibm.com> + Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-05 Michael Meissner <meissner@linux.vnet.ibm.com> + Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/rs6000-protos.h (rs6000_split_signbit): New + prototype. + * config/rs6000/rs6000.c (rs6000_split_signbit): New function. + * config/rs6000/rs6000.md (UNSPEC_SIGNBIT): New constant. + (SIGNBIT): New mode iterator. + (Fsignbit): New mode attribute. + (signbit<mode>2): Change operand1 to match FLOAT128 instead of + IBM128; dispatch to gen_signbit{kf,tf}2_dm for __float128 + when direct moves are available. + (signbit<mode>2_dm): New define_insn_and_split). + (signbit<mode>2_dm2): New define_insn. + +2016-07-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71805 + * config/rs6000/altivec.md (altivec_vperm_<mode>_internal): + The xxperm and xxpermr instructions require that the 2nd input + operand overlap with the output operand, and not the 1st. + (altivec_vperm_v8hiv16qi): Likewise. + (altivec_vperm_<mode>_uns_internal): Likewise. + (altivec_vpermr_<mode>_internal): Likewise. + (vperm_v8hiv4si): Likewise. + (vperm_v16qiv8hi): Likewise. + +2016-07-12 Segher Boessenkool <segher@kernel.crashing.org> + + Backport from mainline + 2016-07-06 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/70098 + PR target/71763 + * config/rs6000/rs6000.md (*ctr<mode>_internal1, *ctr<mode>_internal2, + *ctr<mode>_internal5, *ctr<mode>_internal6): Add *wi to the output + constraint. + +2016-07-11 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71758 + * omp-low.c (expand_omp_target): Gimplify device. + + PR tree-optimization/71823 + * tree-vect-stmts.c (vectorizable_operation): Use vect_get_vec_defs + to get vec_oprnds2 from op2. + +2016-07-11 Yuri Rumyantsev <ysrumyan@gmail.com> + + Backport from mainline r238055. + 2016-07-06 Yuri Rumyantsev <ysrumyan@gmail.com> + + PR tree-optimization/71518 + * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Adjust + misalign also for outer loops with negative step. + +2016-07-08 Martin Liska <mliska@suse.cz> + + Backported from mainline + 2016-07-08 Martin Liska <mliska@suse.cz> + + PR middle-end/71606 + * fold-const.c (fold_convertible_p): As COMPLEX_TYPE + folding produces SAVE_EXPRs, thus return false for the type. + +2016-07-08 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/rs6000-builtin.def (BU_P9_MISC_1): Remove + redundant and erroneous definition of this macro accidentally + inserted during backporting. + (BU_P9_64BIT_MISC_0): Likewise. + (BU_P9_MISC_0): Likewise. + +2016-07-08 Jiong Wang <jiong.wang@arm.com> + + Back port from the trunk + 2016-07-08 Jiong Wang <jiong.wang@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (smax): Remove float + variants. + (smin): Likewise. + (fmax): New entry. + (fmin): Likewise. + * config/aarch64/arm_neon.h (vmaxnm_f32): Use + __builtin_aarch64_fmaxv2sf. + (vmaxnmq_f32): Likewise. + (vmaxnmq_f64): Likewise. + (vminnm_f32): Likewise. + (vminnmq_f32): Likewise. + (vminnmq_f64): Likewise. + +2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk + 2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71806 + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Do not + enable -mfloat128-hardware by default. + (ISA_3_0_MASKS_IEEE): New macro to give all of the VSX options + that IEEE 128-bit hardware support needs. + * config/rs6000/rs6000.c (rs6000_option_override_internal): If + -mcpu=power9 -mfloat128, enable -mfloat128-hardware by default. + Use ISA_3_0_MASKS_IEEE as the set of options that IEEE 128-bit + floating point requires. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document + -mfloat128 and -mfloat128-hardware changes. + +2016-07-08 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from mainline r237912 + 2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/altivec.md (*altivec_vpermr_<mode>_internal): + Exchange the order of the second and third operands in the vpermr + instruction tmeplate. + +2016-07-07 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from the trunk + 2016-07-01 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71720 + * config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting + the insns, use an insn form that does not adjust the offset on + little endian systems. + +2016-07-07 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from mainline r237885 + 2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/altivec.md (darn_32): Change the condition to + TARGET_P9_MISC instead of TARGET_MODULO. + (darn_raw): Replace TARGET_MODULO with TARGET_P9_MISC in the + condition expression. + (darn): Replace TARGET_MODULO with TARGET_P9_MISC in the + condition expression. + * config/rs6000/dfp.md (UNSPEC_DTSTSFI): New unspec constant. + (DFP_TEST): New code iterator. + (dfptstsfi_<code>_mode>): New define_expand. + (*dfp_sgnfcnc_<mode>): New define_insn. + * config/rs6000/rs6000-builtin.def (BU_P9_MISC_0): Move this macro + definition next to BU_P9_MISC_1 definition and change the MASK + value to RS6000_BTM_P9_MISC. + (BU_P9_MISC_1): Change the MASK value to RS6000_BTM_P9_MISC. + (BU_P9_64BIT_MISC_0): Likewise. + (BU_P9_DFP_MISC_0): New macro definition. + (BU_P9_DFP_MISC_1): New macro definition. + (BU_P9_DFP_MISC_2): New macro definition. + (BU_P9_DFP_OVERLOAD_1): New macro definition. + (BU_P9_DFP_OVERLOAD_2): New macro definition. + (BU_P9_DFP_OVERLOAD_3): New macro definition. + (TSTSFI_LT_DD): New BU_P9_DFP_MISC_2. + (TSTSFI_LT_TD): Likewise. + (TSTSFI_EQ_DD): Likewise. + (TSTSFI_EQ_TD): Likewise. + (TSTSFI_GT_DD): Likewise. + (TSTSFI_GT_TD): Likewise. + (TSTSFI_OV_DD): Likewise. + (TSTSFI_OV_TD): Likewise. + (TSTSFI_LT): New BU_P9_DFP_OVERLOAD_2. + (TSTSFI_LT_DD): Likewise. + (TSTSFI_LT_TD): Likewise. + (TSTSFI_EQ): Likewise. + (TSTSFI_EQ_DD): Likewise. + (TSTSFI_EQ_TD): Likewise. + (TSTSFI_GT): Likewise. + (TSTSFI_GT_DD): Likewise. + (TSTSFI_GT_TD): Likewise. + (TSTSFI_OV): Likewise. + (TSTSFI_OV_DD): Likewise. + (TSTSFI_OV_TD): Likewise. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + overloaded test significance functions. + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add + OPTION_MASK_P9_MISC into the representation of this mask. + (POWERPC_MASKS): Add OPTION_MASK_P9_MISC into the representation + of this mask. + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Set the + RS6000_BTM_P9_MISC flag in the return value if TARGET_P9_MISC is + non-zero. + (rs6000_expand_binop_builtin): Enforce that argument 0 of the exp + argument is a 6-bit unsigned literal value if the icode argument + represents a DFP test significance built-in call. + (rs6000_invalid_builtin): Add support for the RS6000_BTM_P9_MISC + flag used independently and in combination with the + RS6000_BTM_64BIT flag. + (rs6000_opt_masks): Add entry for power9-misc command-line option. + (rs6000_builtin_mask_names): Add entry for power9-misc + command-line option. + * config/rs6000/rs6000.h: Redefine TARGET_P9_MISC as 0 if + HAVE_AS_POWER9 is not a defined macro. Define MASK_P9_MISC and + RS6000_BTM_P9_MISC macros. + * config/rs6000/rs6000.opt: Add support for the -mpower9-misc + option and change the description of the -mpower9-vector option to + enable only vector instructions, removing its erroneously claimed + support for scalar instructions. + * doc/extend.texi (PowerPC AltiVec Built-in Functions): Document + the ISA 3.0 digital floating point test significance built-in + functions. + +2016-07-07 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-06-13 Richard Biener <rguenther@suse.de> + + PR middle-end/64516 + * fold-const.c (fold_unary_loc): Preserve alignment when + folding a VIEW_CONVERT_EXPR into a MEM_REF. + +2016-07-07 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-05-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71264 + * tree-vect-stmts.c (vect_init_vector): Properly deal with + vector type val. + + 2016-06-07 Richard Biener <rguenther@suse.de> + + PR middle-end/71423 + * match.pd ((X | ~Y) -> Y <= X): Properly invert the comparison + for signed ops. + + 2016-06-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71521 + * tree-vrp.c (extract_range_from_binary_expr_1): Guard + division int_const_binop against zero divisor. + + 2016-06-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71452 + * tree-ssa.c (non_rewritable_lvalue_p): Make sure that the + type used for the SSA rewrite has enough precision to cover + the dynamic type of the location. + + 2016-06-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71522 + * tree-ssa.c (non_rewritable_lvalue_p): Do not rewrite non-float + copying into float copying. + +2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> + + Backport from mainline + 2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> + + PR target/50739 + * config/avr/avr.c (avr_asm_select_section): Strip off + SECTION_DECLARED from flags when calling get_section. + +2016-07-05 Pat Haugen <pthaugen@us.ibm.com> + + Backport from mainline + 2016-06-28 Pat Haugen <pthaugen@us.ibm.com> + + * config/rs6000/rs6000.md ('type' attribute): Add htmsimple/dfp types. + ('size' attribute): Add '128'. + Include power9.md. + (*mov<mode>_hardfloat32, *mov<mode>_hardfloat64, *movdi_internal32, + *movdi_internal64, *movdf_update1): Set size attribute to '64'. + (add<mode>3, sub<mode>3, mul<mode>3, div<mode>3, sqrt<mode>2, + copysign<mode>3, neg<mode>2_hw, abs<mode>2_hw, *nabs<mode>2_hw, + *fma<mode>4_hw, *fms<mode>4_hw, *nfma<mode>4_hw, *nfms<mode>4_hw, + extend<SFDF:mode><IEEE128:mode>2_hw, trunc<mode>df2_hw, + *xscvqp<su>wz_<mode>, *xscvqp<su>dz_<mode>, *xscv<su>dqp_<mode>, + *trunc<mode>df2_odd): Set size attribute to '128'. + (*cmp<mode>_hw): Change type to veccmp and set size attribute to '128'. + * config/rs6000/power6.md (power6-fp): Include dfp type. + * config/rs6000/power7.md (power7-fp): Likewise. + * config/rs6000/power8.md (power8-fp): Likewise. + * config/rs6000/power9.md: New file. + * config/rs6000/t-rs6000 (MD_INCLUDES): Add power9.md. + * config/rs6000/htm.md (*tabort, *tabort<wd>c, *tabort<wd>ci, + *trechkpt, *treclaim, *tsr, *ttest): Change type attribute to + htmsimple. + * config/rs6000/dfp.md (extendsddd2, truncddsd2, extendddtd2, + trunctddd2, adddd3, addtd3, subdd3, subtd3, muldd3, multd3, divdd3, + divtd3, *cmpdd_internal1, *cmptd_internal1, floatdidd2, floatditd2, + ftruncdd2, fixdddi2, ftrunctd2, fixtddi2, dfp_ddedpd_<mode>, + dfp_denbcd_<mode>, dfp_dxex_<mode>, dfp_diex_<mode>, dfp_dscli_<mode>, + dfp_dscri_<mode>): Change type attribute to dfp. + * config/rs6000/crypto.md (crypto_vshasigma<CR_char>): Change type + attribute to vecsimple. + * config/rs6000/rs6000.c (power9_cost): Update costs, cache size + and prefetch streams. + (rs6000_option_override_internal): Remove temporary code setting + tuning to power8. Don't set rs6000_sched_groups for power9. + (last_scheduled_insn): Change to rtx_insn *. + (divide_cnt, vec_load_pendulum): New variables. + (rs6000_adjust_cost): Add Power9 to test for store->load separation. + (rs6000_issue_rate): Set issue rate for Power9. + (is_power9_pairable_vec_type): New. + (power9_sched_reorder2): New. + (rs6000_sched_reorder2): Call new function for Power9 specific + reordering. + (insn_must_be_first_in_group): Remove Power9. + (insn_must_be_last_in_group): Likewise. + (force_new_group): Likewise. + (rs6000_sched_init): Fix initialization of last_scheduled_insn. + Initialize divide_cnt/vec_load_pendulum. + (_rs6000_sched_context, rs6000_init_sched_context, + rs6000_set_sched_context): Handle context save/restore of new + variables. + +2016-07-05 Pat Haugen <pthaugen@us.ibm.com> + + Backport from mainline + 2016-06-27 Pat Haugen <pthaugen@us.ibm.com> + + * config/rs6000/rs6000.md ('type' attribute): Add + veclogical,veccmpfx,vecexts,vecmove insn types. + (*abs<mode>2_fpr, *nabs<mode>2_fpr, *neg<mode>2_fpr, *extendsfdf2_fpr, + copysign<mode>3_fcpsgn, trunc<mode>df2_internal1, neg<mode>2_internal, + p8_fmrgow_<mode>, pack<mode>): Change type to fpsimple. + (*xxsel<mode>, copysign<mode>3_hard, neg<mode>2_hw, abs<mode>2_hw, + *nabs<mode>2_hw): Change type to vecmove. + (*and<mode>3_internal, *bool<mode>3_internal, *boolc<mode>3_internal, + *boolcc<mode>3_internal, *eqv<mode>3_internal, + *one_cmpl<mode>3_internal, *ieee_128bit_vsx_neg<mode>2_internal, + *ieee_128bit_vsx_abs<mode>2_internal, + *ieee_128bit_vsx_nabs<mode>2_internal, extendkftf2, trunctfkf2, + *ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit, + *ieee128_mtvsrd_32bit): Change type to veclogical. + (mov<mode>_hardfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64, + *movdi_internal32, *movdi_internal64): Update insn types. + * config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>, + vsx_extract_<mode>): Change type to veclogical. + (*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns): Change type to vecmove. + (vsx_sign_extend_qi_<mode>, *vsx_sign_extend_hi_<mode>, + *vsx_sign_extend_si_v2di): Change type to vecexts. + * config/rs6000/altivec.md (*altivec_mov<mode>, *altivec_movti): Change + type to veclogical. + (*altivec_eq<mode>, *altivec_gt<mode>, *altivec_gtu<mode>, + *altivec_vcmpequ<VI_char>_p, *altivec_vcmpgts<VI_char>_p, + *altivec_vcmpgtu<VI_char>_p): Change type to veccmpfx. + (*altivec_vsel<mode>, *altivec_vsel<mode>_uns): Change type to vecmove. + * config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr, + negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple. + * config/rs6000/40x.md (ppc405-float): Add fpsimple. + * config/rs6000/440.md (ppc440-fp): Add fpsimple. + * config/rs6000/476.md (ppc476-fp): Add fpsimple. + * config/rs6000/601.md (ppc601-fp): Add fpsimple. + * config/rs6000/603.md (ppc603-fp): Add fpsimple. + * config/rs6000/6xx.md (ppc604-fp): Add fpsimple. + * config/rs6000/7xx.md (ppc750-fp): Add fpsimple. + (ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx. + * config/rs6000/7450.md (ppc7450-fp): Add fpsimple. + (ppc7450-vecsimple): Add veclogical, vecmove. + (ppc7450-veccmp): Add veccmpfx. + * config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical, + vecmove. + (ppc8540_vector_compare): Add veccmpfx. + * config/rs6000/a2.md (ppca2-fp): Add fpsimple. + * config/rs6000/cell.md (cell-fp): Add fpsimple. + (cell-vecsimple): Add veclogical, vecmove. + (cell-veccmp): Add veccmpfx. + * config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple. + * config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove, + veccmpfx. + * config/rs6000/mpc.md (mpccore-fp): Add fpsimple. + * config/rs6000/power4.md (power4-fp): Add fpsimple. + (power4-vecsimple): Add veclogical, vecmove. + (power4-veccmp): Add veccmpfx. + * config/rs6000/power5.md (power5-fp): Add fpsimple. + * config/rs6000/power6.md (power6-fp): Add fpsimple. + (power6-vecsimple): Add veclogical, vecmove. + (power6-veccmp): Add veccmpfx. + * config/rs6000/power7.md (power7-fp): Add fpsimple. + (power7-vecsimple): Add veclogical, vecmove, veccmpfx. + * config/rs6000/power8.md (power8-fp): Add fpsimple. + (power8-vecsimple): Add veclogical, vecmove, veccmpfx. + * config/rs6000/rs64.md (rs64a-fp): Add fpsimple. + * config/rs6000/titan.md (titan_fp): Add fpsimple. + * config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add + fpsimple. + * config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE. + +2016-07-05 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from mainline r237391 + 2016-06-13 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/rs6000.h (RS6000_BTM_COMMON): Add the + RS6000_BTM_MODULO flag into the set of flags that are considered + to be part of the common configuration. + +2016-07-04 Jakub Jelinek <jakub@redhat.com> + + PR c++/71739 + * tree.c (attribute_value_equal): Use get_attribute_name instead of + directly using TREE_PURPOSE. + +2016-07-04 Segher Boessenkool <segher@kernel.crashing.org> + + Backport from mainline + 2016-06-27 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/71670 + * config/rs6000/rs6000.md (ashdi3_extswsli_dot): Use + gen_ashdi3_extswsli_dot2 instead of gen_ashdi3_extswsli_dot. + +2016-07-02 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-06-28 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71626 + * config/i386/i386.c (ix86_expand_vector_move): For SUBREG of + a constant, force its SUBREG_REG into memory or register instead + of whole op1. + + 2016-06-20 Jakub Jelinek <jakub@redhat.com> + + PR target/71559 + * config/i386/i386.c (ix86_fp_cmp_code_to_pcmp_immediate): Fix up + returned values and add UN*/LTGT/*ORDERED cases with values matching + D operand modifier on vcmp for AVX. + +2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from trunk r237659 + 2016-06-21 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/rs6000.h: Add conditional preprocessing directives + to disable Power9-specific compiler features if HAVE_AS_POWER9 is + not defined. + +2016-07-01 Peter Bergner <bergner@vnet.ibm.com> + + Backport from trunk + 2016-06-27 Peter Bergner <bergner@vnet.ibm.com> + + PR target/71656 + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add + OPTION_MASK_P9_DFORM_VECTOR. + * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not + disable -mpower9-dform-vector when using reload. + (quad_address_p): Remove 'gpr_p' argument and all associated code. + New 'strict' argument. Update all callers. Add strict addressing + support. + (rs6000_legitimate_offset_address_p): Remove call to + virtual_stack_registers_memory_p. + (rs6000_legitimize_reload_address): Add quad address support. + (rs6000_legitimate_address_p): Move call to quad_address_p above + call to virtual_stack_registers_memory_p. Adjust quad_address_p args + to account for new strict usage. + (rs6000_output_move_128bit): Adjust quad_address_p args to account + for new strict usage. + * config/rs6000/predicates.md (quad_memory_operand): Likewise. + +2016-07-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-06-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/rs6000-builtin.def (BU_FLOAT128_2): New #define. + (BU_FLOAT128_1): Likewise. + (FABSQ): Likewise. + (COPYSIGNQ): Likewise. + (RS6000_BUILTIN_NANQ): Likewise. + (RS6000_BUILTIN_NANSQ): Likewise. + (RS6000_BUILTIN_INFQ): Likewise. + (RS6000_BUILTIN_HUGE_VALQ): Likewise. + * config/rs6000/rs6000.c (rs6000_fold_builtin): New prototype. + (TARGET_FOLD_BUILTIN): New #define. + (rs6000_builtin_mask_calculate): Add TARGET_FLOAT128 entry. + (rs6000_invalid_builtin): Add handling for RS6000_BTM_FLOAT128. + (rs6000_fold_builtin): New target hook implementation, handling + folding of 128-bit NaNs and infinities. + (rs6000_init_builtins): Initialize const_str_type_node; ensure all + entries are filled in to avoid problems during bootstrap + self-test; define builtins for 128-bit NaNs and infinities. + (rs6000_opt_mask): Add entry for float128. + * config/rs6000/rs6000.h (RS6000_BTM_FLOAT128): New #define. + (RS6000_BTM_COMMON): Include RS6000_BTM_FLOAT128. + (rs6000_builtin_type_index): Add RS6000_BTI_const_str. + (const_str_type_node): New #define. + * config/rs6000/rs6000.md (copysign<mode>3 for IEEE128): Convert + to a define_expand that dispatches to either copysign<mode>3_soft + or copysign<mode>3_hard. + (copysign<mode>3_hard): Rename from copysign<mode>3. + (copysign<mode>3_soft): New define_insn. + * doc/extend.texi: Document new builtins. + +2016-07-01 Peter Bergner <bergner@vnet.ibm.com> + + Backport from trunk + 2016-07-01 Peter Bergner <bergner@vnet.ibm.com> + + PR target/71698 + * config/rs6000/rs6000.c (rs6000_secondary_reload_simple_move): Disallow + TDmode values. + +2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from trunk r236992 + 2016-06-01 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/altivec.h (vec_slv): New macro. + (vec_srv): New macro. + * config/rs6000/altivec.md (UNSPEC_VSLV): New value. + (UNSPEC_VSRV): New value. + (vslv): New insn. + (vsrv): New insn. + * config/rs6000/rs6000-builtin.def (vslv): New builtin definition. + (vsrv): New builtin definition. + * config/rs6000/rs6000-c.c (P9V_BUILTIN_VSLV): Macro expansion to + define argument types for new builtin. + (P9V_BUILTIN_VSRV): Macro expansion to define argument types for + new builtin. + * doc/extend.texi: Document the new vec_vslv and vec_srv built-in + functions. + +2016-07-01 Eric Botcazou <ebotcazou@adacore.com> + + * config/arm/arm.c (arm_function_ok_for_sibcall): Add another check + for NULL decl. + +2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from trunk r237390 + 2016-06-13 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * config/rs6000/altivec.h (vec_absd): New macro for vector absolute + difference unsigned. + (vec_absdb): New macro for vector absolute difference unsigned + byte. + (vec_absdh): New macro for vector absolute difference unsigned + half-word. + (vec_absdw): New macro for vector absolute difference unsigned word. + * config/rs6000/altivec.md (UNSPEC_VADU): New value. + (vadu<mode>3): New insn. + (*p9_vadu<mode>3): New insn. + * config/rs6000/rs6000-builtin.def (vadub): New built-in + definition. + (vaduh): New built-in definition. + (vaduw): New built-in definition. + (vadu): New overloaded built-in definition. + (vadub): New overloaded built-in definition. + (vaduh): New overloaded built-in definition. + (vaduw): New overloaded built-in definition. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + overloaded vector absolute difference unsigned functions. + * doc/extend.texi (PowerPC AltiVec Built-in Functions): Document + the ISA 3.0 vector absolute difference unsigned built-in functions. + +2016-06-30 David Malcolm <dmalcolm@redhat.com> + + Backport from trunk r237880. + 2016-06-30 David Malcolm <dmalcolm@redhat.com> + + PR driver/71651 + * gcc.c (driver::build_option_suggestions): Pass "option" to + add_misspelling_candidates. + * opts-common.c (add_misspelling_candidates): Add "option" param; + use it to avoid adding negated forms for options marked with + RejectNegative. + * opts.h (add_misspelling_candidates): Add "option" param. + +2016-06-30 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71693 + * fold-const.c (fold_binary_loc) <case RROTATE_EXPR>: Cast + TREE_OPERAND (arg0, 0) and TREE_OPERAND (arg0, 1) to type + first when permuting bitwise operation with rotate. Cast + TREE_OPERAND (arg0, 0) to type when cancelling two rotations. + +2016-06-30 Martin Liska <mliska@suse.cz> + + Parting backport from mainline + 2016-06-29 Martin Liska <mliska@suse.cz> + + * ipa-inline-transform.c (inline_call): Remove unnecessary call + of build_optimization_node. + +2016-06-29 Eric Botcazou <ebotcazou@adacore.com> + + Backport from mainline + 2016-06-09 Eric Botcazou <ebotcazou@adacore.com> + + * df-problems.c (df_note_bb_compute): Guard use of DF_INSN_INFO_GET. + +2016-06-27 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk + 2016-06-21 Michael Meissner <meissner@linux.vnet.ibm.com> + + * stor-layout.c (layout_type): Move setting complex MODE to + layout_type, instead of setting it ahead of time by the caller. + + Back port from trunk + 2016-05-11 Alan Modra <amodra@gmail.com> + + * config/rs6000/rs6000.c (is_complex_IBM_long_double, + abi_v4_pass_in_fpr): New functions. + (rs6000_function_arg_boundary): Exclude complex IBM long double + from 64-bit alignment when ABI_V4. + (rs6000_function_arg, rs6000_function_arg_advance_1, + rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr. + + Back port from trunk + 2016-05-02 Michael Meissner <meissner@linux.vnet.ibm.com> + + * machmode.h (mode_complex): Add support to give the complex mode + for a given mode. + (GET_MODE_COMPLEX_MODE): Likewise. + * stor-layout.c (layout_type): For COMPLEX_TYPE, use the mode + stored by build_complex_type and gfc_build_complex_type instead of + trying to figure out the appropriate mode based on the size. Raise + an assertion error, if the type was not set. + * genmodes.c (struct mode_data): Add field for the complex type of + the given type. + (blank_mode): Likewise. + (make_complex_modes): Remember the complex mode created in the + base type. + (emit_mode_complex): Write out the mode_complex array to map a + type mode to the complex version. + (emit_insn_modes_c): Likewise. + * tree.c (build_complex_type): Set the complex type to use before + calling layout_type. + * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Add + support for __float128 complex datatypes. + (rs6000_hard_regno_mode_ok): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_complex_function_value): Likewise. + * config/rs6000/rs6000.h (FLOAT128_IEEE_P): Likewise. + __float128 and __ibm128 complex. + (FLOAT128_IBM_P): Likewise. + (ALTIVEC_ARG_MAX_RETURN): Likewise. + * doc/extend.texi (Additional Floating Types): Document that + -mfloat128 must be used to enable __float128. Document complex + __float128 and __ibm128 support. + +2016-06-24 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71647 + * omp-low.c (lower_rec_input_clauses): Convert + omp_clause_aligned_alignment (c) to size_type_node for the + last argument of __builtin_assume_aligned. + +2016-06-22 Eric Botcazou <ebotcazou@adacore.com> + + * function.c (assign_parm_setup_reg): Prevent sharing in another case. + +2016-06-21 Georg-Johann Lay <avr@gjlay.de> + + Backport from 2016-06-21 trunk r237639. + + PR target/30417 + * config/avr/gen-avr-mmcu-specs.c (print_mcu): + [*link_data_start]: Wrap -Tdata into %{!Tdata:...}. + [*link_text_start]: Wrap -Ttext into %{!Ttext:...}. + +2016-06-21 Georg-Johann Lay <avr@gjlay.de> + + PR target/71103 + * config/avr/avr.md (movqi): Only handle loading subreg:qi of + constant addresses if can_create_pseudo_p. + +2016-06-21 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71588 + * tree-ssa-strlen.c (valid_builtin_call): New function. + (adjust_last_stmt, handle_builtin_memset, strlen_optimize_stmt): Use + it. + + Backported from mainline + 2016-06-20 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71581 + * tree-ssa-uninit.c (warn_uninit): If EXPR and VAR are NULL, + see if T isn't anonymous SSA_NAME with COMPLEX_EXPR created + for conversion of scalar user var to complex type and use the + underlying SSA_NAME_VAR in that case. If EXPR is still NULL, + punt. + + 2016-06-16 Jakub Jelinek <jakub@redhat.com> + + * gimplify.c (gimplify_scan_omp_clauses): Handle COMPONENT_REFs + with base of reference to struct. + +2016-06-20 Ilya Enkovich <ilya.enkovich@intel.com> + + Backport from mainline r237484. + 2016-06-15 Ilya Enkovich <ilya.enkovich@intel.com> + + PR middle-end/71529 + * ipa-chkp.c (chkp_build_instrumented_fndecl): Fix + DECL_CONTEXT for copied arguments. + +2016-06-20 Georg-Johann Lay <avr@gjlay.de> + Pitchumani Sivanupandi <pitchumani.s@atmel.com> + + Backport from 2016-06-20 trunk r237589, r236558. + + PR target/71103 + * config/avr/avr.md (movqi): Handle loading subreg:qi (const, + symbol_ref,label_ref). + +2016-06-16 Jakub Jelinek <jakub@redhat.com> + + PR target/71554 + * config/i386/i386.md (setcc + movzbl peephole2): Use reg_set_p. + (setcc + and peephole2): Likewise. + +2016-06-15 Andreas Tobler <andreast@gcc.gnu.org> + + Backported from mainline + 2016-06-14 Andreas Tobler <andreast@gcc.gnu.org> + + * config/arm/freebsd.h: Only enable unaligned access for armv6 on + FreeBSD 11 and above. + +2016-06-15 Ilya Verbin <ilya.verbin@intel.com> + + Backport from mainline + 2016-04-30 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * config/darwin.h (LINK_COMMAND_SPEC_A): Handle -fcilkplus. + +2016-06-14 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-06-10 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71494 + * tree-nested.c (convert_nonlocal_reference_stmt): For GIMPLE_GOTO + without LABEL_DECL, set *handled_ops_p to false instead of true. + + 2016-06-08 Jakub Jelinek <jakub@redhat.com> + Richard Biener <rguenther@suse.de> + + PR c++/71448 + * fold-const.c (fold_comparison): Handle CONSTANT_CLASS_P (base0) + the same as DECL_P (base0) for indirect_base0. Use equality_code + in one further place. + + 2016-06-04 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71405 + * tree-ssa.c (execute_update_addresses_taken): For clobber with + incompatible type, build a new clobber with the right type instead + of building a VIEW_CONVERT_EXPR around it. + +2016-06-13 Eric Botcazou <ebotcazou@adacore.com> + + * tree-ssa-sccvn.c (vn_reference_lookup_3): Use a uniform test and + update shared_lookup_references only once after changing operands. + +2016-06-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71505 + * tree-vect-data-refs.c (vect_analyze_data_ref_accesses): Make + assert match comment. + +2016-06-13 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + Backport from mainline + 2016-06-13 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + + PR target/71379 + * config/s390/s390.c (s390_expand_builtin): Increase MAX_ARGS by + one. + +2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/71373 + Backport from trunk r237291: + * tree-nested.c (convert_nonlocal_omp_clauses) + (convert_local_omp_clauses): Handle OMP_CLAUSE_ASYNC, + OMP_CLAUSE_WAIT, OMP_CLAUSE_INDEPENDENT, OMP_CLAUSE_AUTO, + OMP_CLAUSE__CACHE_, OMP_CLAUSE_TILE. + + Backport from trunk r237291: + * gimplify.c (gimplify_adjust_omp_clauses): Discard + OMP_CLAUSE_TILE. + * omp-low.c (scan_sharing_clauses): Don't expect OMP_CLAUSE_TILE. + + Backport from trunk r237290: + * omp-low.c (scan_sharing_clauses): Don't expect + OMP_CLAUSE__CACHE_. + + Backport trunk r235964: + 2016-05-06 Nathan Sidwell <nathan@codesourcery.com> + + * gimple.c (gimple_call_same_target_p): Unique functions are eq. + * tree-ssa-tail-merge.c (same_succ::equal): Check pointer eq + equality first. + +2016-06-09 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk + 2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/vsx.md (vsx_splat_<mode>, V2DI/V2DF): Simplify + alternatives, eliminating preferred register class. Add support + for the MTVSRDD instruction in ISA 3.0. + (vsx_splat_v4si_internal): Use splat_input_operand instead of + reg_or_indexed_operand. + (vsx_splat_v4sf_internal): Likewise. + + Back port from trunk + 2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71186 + * config/rs6000/vsx.md (xxspltib_<mode>_nosplit): Add alternatives + for loading up all 0's or all 1's. + + Back port from trunk + 2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/70915 + * config/rs6000/constraints.md (wE constraint): New constraint + for a vector constant that can be loaded with XXSPLTIB. + (wM constraint): New constraint for a vector constant of a 1's. + (wS constraint): New constraint for a vector constant that can be + loaded with XXSPLTIB and a vector sign extend instruction. + * config/rs6000/predicates.md (xxspltib_constant_split): New + predicates for wE/wS constraints. + (xxspltib_constant_nosplit): Likewise. + (easy_vector_constant): Add support for constants that can be + loaded via XXSPLTIB. + (splat_input_operand): Add support for ISA 3.0 word splat operations. + * config/rs6000/rs6000.c (xxspltib_constant_p): New function to + return if a constant can be loaded with the ISA 3.0 XXSPLTIB + instruction and possibly with a sign extension. + (output_vec_const_move): Add support for XXSPLTIB. If we are + loading up 0/-1 into Altivec registers, prefer using VSPLTISW + instead of XXLXOR/XXLORC. + (rs6000_expand_vector_init): Add support for ISA 3.0 word splat + operations. + (rs6000_legitimize_reload_address): Likewise. + (rs6000_output_move_128bit): Use output_vec_const_move to emit + constants. + * config/rs6000/vsx.md (VSX_M): Add TImode (if -mvsx-timode) and + combine VSX_M and VSX_M2 into one iterator. + (VSX_M2): Likewise. + (VSINT_84): New iterators for loading constants with XXSPLTIB. + (VSINT_842): Likewise. + (UNSPEC_VSX_SIGN_EXTEND): New UNSPEC. + (xxspltib_v16qi): New insns to load up constants with the ISA 3.0 + XXSPLTIB instruction. + (xxspltib_<mode>_nosplit): Likewise. + (xxspltib_<mode>_split): New insn to load up constants with + XXSPLTIB and a sign extend instruction. + (vsx_mov<mode>): Replace single move that handled all vector types + with separate 32-bit and 64-bit moves. Combine the movti_<bit> + moves (when -mvsx-timode is in effect) into the main vector + moves. Eliminate separate moves for <VSr> <VSa>, where the + preferred register class (<VSr>) is listed first, and the + secondary register class (<VSa>) is listed second with a '?' to + discourage use. Prefer loading 0/-1 in any VSX register for ISA + 3.0, and Altivec registers for ISA 2.06/2.07 (PR target/70915) so + that if the register was involved in a slow operation, the + clear/set operation does not wait for the slow operation to + finish. Adjust the length attributes for 32-bit mode. Use + rs6000_output_move_128bit and drop the use of the string + instructions for 32-bit movti when -mvsx-timode is in effect. Use + spacing so that the alternatives and attributes don't generate + long lines, and put things in columns, so that it is easier to + match up the operands and attributes with the insn alternatives. + (vsx_mov<mode>_64bit): Likewise. + (vsx_mov<mode>_32bit): Likewise. + (vsx_movti_64bit): Fold movti into normal vector moves. + (vsx_movti_32bit): Likewise. + (vsx_splat_<mode>, V4SI/V4SF modes): Add support for ISA 3.0 word + splat instructions. + (vsx_splat_v4si_internal): Likewise. + (vsx_splat_v4sf_internal): Likewise. + (vector fusion peepholes): Use VSX_M instead of VSX_M2. + (vsx_sign_extend_qi_<mode>): New ISA 3.0 instructions to sign + extend vector elements. + (vsx_sign_extend_hi_<mode>): Likewise. + (vsx_sign_extend_si_v2di): Likewise. + * config/rs6000/rs6000-protos.h (xxspltib_constant_p): Add + declaration. + * doc/md.texi (PowerPC constraints): Document the wE, wM, and wS + constraints. Add trailing period to wL documentation. + +2016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com> + + Backport from mainline + 2016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/driver-sparc.c (cpu_names): Fix the entry for the + SPARC-M7 and add an entry for SPARC-S7 cpus (Sonoma). + +2016-06-08 Eric Botcazou <ebotcazou@adacore.com> + + Backport from mainline + 2016-06-06 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/sparc/sparc.md (cpu): Add niagara7 cpu type. + Include the M7 SPARC DFA scheduler. + New attribute v3pipe. + Annotate insns with v3pipe where appropriate. + Define cpu_feature vis4. + Add lzd instruction type and set it on clzdi_sp64 and clzsi_sp64. + Add (V8QI "8") to vbits. + Add insns {add,sub}v8qi3 + Add insns ss{add,sub}v8qi3 + Add insns us{add,sub}{v8qi,v4hi}3 + Add insns {min,max}{v8qi,v4hi,v2si}3 + Add insns {minu,maxu}{v8qi,v4hi,v2si}3 + Add insns fpcmp{le,gt,ule,ug,ule,ugt}{8,16,32}_vis. + * config/sparc/niagara4.md: Add a comment explaining the + discrepancy between the documented latenty numbers and the + implemented ones. + * config/sparc/niagara7.md: New file. + * configure.ac (HAVE_AS_SPARC5_VIS4): Define if the assembler + supports SPARC5 and VIS 4.0 instructions. + * configure: Regenerate. + * config.in: Likewise. + * config.gcc: niagara7 is a supported cpu in sparc*-*-* targets. + * config/sparc/sol2.h (ASM_CPU32_DEFAUILT_SPEC): Set for + TARGET_CPU_niagara7. + (ASM_CPU64_DEFAULT_SPEC): Likewise. + (CPP_CPU_SPEC): Handle niagara7. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sparc-opts.h (processor_type): Add + PROCESSOR_NIAGARA7. + (mvis4): New option. + * config/sparc/sparc.h (TARGET_CPU_niagara7): Define. + (AS_NIAGARA7_FLAG): Define. + (ASM_CPU64_DEFAULT_SPEC): Set for niagara7. + (CPP_CPU64_DEFAULT_SPEC): Likewise. + (CPP_CPU_SPEC): Handle niagara7. + (ASM_CPU_SPEC): Likewise. + * config/sparc/sparc.c (niagara7_costs): Define. + (sparc_option_override): Handle niagara7 and adjust cache-related + parameters with better values for niagara cpus. Also support VIS4. + (sparc32_initialize_trampoline): Likewise. + (sparc_use_sched_lookahead): Likewise. + (sparc_issue_rate): Likewise. + (sparc_register_move_cost): Likewise. + (dump_target_flag_bits): Support VIS4. + (sparc_vis_init_builtins): Likewise. + (sparc_builtins): Likewise. + * config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__ for + VIS4 4.0. + * config/sparc/driver-sparc.c (cpu_names): Add SPARC-M7 and + UltraSparc M7. + * config/sparc/sparc.opt (sparc_processor_type): New value + niagara7. + * config/sparc/visintrin.h (__attribute__): Prototypes for the + VIS4 builtins. + * doc/invoke.texi (SPARC Options): Document -mcpu=niagara7 and + -mvis4. + * doc/extend.texi (SPARC VIS Built-in Functions): Document the + VIS4 builtins. + + 2016-05-30 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config.gcc (sparc*-*-*): Support cpu_32, cpu_64, tune_32 and + tune_64. + * doc/install.texi (--with-cpu-32, --with-cpu-64): Document + support on SPARC. + * config/sparc/linux64.h (OPTION_DEFAULT_SPECS): Add entries for + cpu_32, cpu_64, tune_32 and tune_64. + * config/sparc/sol2.h (OPTION_DEFAULT_SPECS): Likewise. + +2016-06-08 Ilya Verbin <ilya.verbin@intel.com> + + Backport from mainline + 2016-05-25 Ilya Verbin <ilya.verbin@intel.com> + + * config/i386/i386-builtin-types.def: Add V16SI_FTYPE_V16SF, + V8DF_FTYPE_V8DF_ROUND, V16SF_FTYPE_V16SF_ROUND, V16SI_FTYPE_V16SF_ROUND. + * config/i386/i386.c (enum ix86_builtins): Add + IX86_BUILTIN_CVTPS2DQ512_MASK, IX86_BUILTIN_FLOORPS512, + IX86_BUILTIN_FLOORPD512, IX86_BUILTIN_CEILPS512, IX86_BUILTIN_CEILPD512, + IX86_BUILTIN_TRUNCPS512, IX86_BUILTIN_TRUNCPD512, + IX86_BUILTIN_CVTPS2DQ512, IX86_BUILTIN_VEC_PACK_SFIX512, + IX86_BUILTIN_FLOORPS_SFIX512, IX86_BUILTIN_CEILPS_SFIX512, + IX86_BUILTIN_ROUNDPS_AZ_SFIX512. + (builtin_description bdesc_args): Add __builtin_ia32_floorps512, + __builtin_ia32_ceilps512, __builtin_ia32_truncps512, + __builtin_ia32_floorpd512, __builtin_ia32_ceilpd512, + __builtin_ia32_truncpd512, __builtin_ia32_cvtps2dq512, + __builtin_ia32_vec_pack_sfix512, __builtin_ia32_roundps_az_sfix512, + __builtin_ia32_floorps_sfix512, __builtin_ia32_ceilps_sfix512. + Change IX86_BUILTIN_CVTPS2DQ512 to IX86_BUILTIN_CVTPS2DQ512_MASK for + __builtin_ia32_cvtps2dq512_mask. + (ix86_expand_args_builtin): Handle V8DF_FTYPE_V8DF_ROUND, + V16SF_FTYPE_V16SF_ROUND, V16SI_FTYPE_V16SF_ROUND, V16SI_FTYPE_V16SF. + (ix86_builtin_vectorized_function): Handle builtins mentioned above. + * config/i386/sse.md + (<mask_codefor>avx512f_fix_notruncv16sfv16si<mask_name><round_name>): + Rename to ... + (avx512f_fix_notruncv16sfv16si<mask_name><round_name>): ... this. + (<mask_codefor>avx512f_cvtpd2dq512<mask_name><round_name>): Rename + to ... + (avx512f_cvtpd2dq512<mask_name><round_name>): ... this. + (avx512f_vec_pack_sfix_v8df): New define_expand. + (avx512f_roundpd512): Rename to ... + (avx512f_round<castmode>512): ... this. Change iterator. + (avx512f_roundps512_sfix): New define_expand. + (round<mode>2_sfix): Change iterator. + +2016-06-07 Peter Bergner <bergner@vnet.ibm.com> + + Backport from mainline + 2016-06-07 Peter Bergner <bergner@vnet.ibm.com> + + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mhtm and + -mno-htm. + +2016-06-07 Uros Bizjak <ubizjak@gmail.com> + + PR target/71389 + * config/i386/i386.c (ix86_avx256_split_vector_move_misalign): + Copy op1 RTX to avoid invalid sharing. + (ix86_expand_vector_move_misalign): Ditto. + +2016-06-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71259 + * tree-vect-slp.c (vect_get_constant_vectors): For + VECTOR_BOOLEAN_TYPE_P, return all ones constant instead of + one for constant op, and use COND_EXPR for non-constant. + 2016-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Backport from trunk diff --git a/gcc/ChangeLog.upc b/gcc/ChangeLog.upc index 90bd95d9922..fb54640de12 100644 --- a/gcc/ChangeLog.upc +++ b/gcc/ChangeLog.upc @@ -1,3 +1,7 @@ +2016-07-15 Gary Funck <gary@intrepid.com> + + Merge GCC 6.0 version 238402 into gupc-6-branch. + 2016-06-06 Gary Funck <gary@intrepid.com> Merge GCC 6.0 version 237141 into gupc-6-branch. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 602e5397582..de638f77d53 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20160606 +20160715 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 59d25a7c97e..233e0976dea 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,17 @@ +2016-06-13 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Deal with + PLUS_EXPR in the expression of a renaming. + +2016-06-11 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/trans.c (Case_Statement_to_gnu): Deal with characters. + +2016-06-11 Pierre-Marie de Rodat <derodat@adacore.com> + + * gcc-interface/decl.c (gnat_to_gnu_entity): Do not clobber + gnat_entity_name with temporary names for XUP and XUT types. + 2016-06-06 Eric Botcazou <ebotcazou@adacore.com> * gcc-interface/utils.c (gnat_internal_attribute_table): Add support diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index 87026e742bb..6f2b0bbfd2d 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -966,6 +966,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) && !call_is_atomic_load (inner)) || TREE_CODE (inner) == ADDR_EXPR || TREE_CODE (inner) == NULL_EXPR + || TREE_CODE (inner) == PLUS_EXPR || TREE_CODE (inner) == CONSTRUCTOR || CONSTANT_CLASS_P (inner) /* We need to detect the case where a temporary is created to @@ -2321,10 +2322,12 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) gnat_name = Packed_Array_Impl_Type (gnat_entity); else gnat_name = gnat_entity; - if (gnat_encodings != DWARF_GNAT_ENCODINGS_MINIMAL) - gnu_entity_name = create_concat_name (gnat_name, "XUP"); - create_type_decl (gnu_entity_name, gnu_fat_type, artificial_p, - debug_info_p, gnat_entity); + tree xup_name + = (gnat_encodings == DWARF_GNAT_ENCODINGS_MINIMAL) + ? get_entity_name (gnat_name) + : create_concat_name (gnat_name, "XUP"); + create_type_decl (xup_name, gnu_fat_type, artificial_p, debug_info_p, + gnat_entity); /* Create the type to be designated by thin pointers: a record type for the array and its template. We used to shift the fields to have the @@ -2334,11 +2337,11 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) Note that GDB can handle standard DWARF information for them, so we don't have to name them as a GNAT encoding, except if specifically asked to. */ - if (gnat_encodings != DWARF_GNAT_ENCODINGS_MINIMAL) - gnu_entity_name = create_concat_name (gnat_name, "XUT"); - else - gnu_entity_name = get_entity_name (gnat_name); - tem = build_unc_object_type (gnu_template_type, tem, gnu_entity_name, + tree xut_name + = (gnat_encodings == DWARF_GNAT_ENCODINGS_MINIMAL) + ? get_entity_name (gnat_name) + : create_concat_name (gnat_name, "XUT"); + tem = build_unc_object_type (gnu_template_type, tem, xut_name, debug_info_p); SET_TYPE_UNCONSTRAINED_ARRAY (tem, gnu_type); diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index aa288154788..cf64d229a5b 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -2483,13 +2483,15 @@ Attribute_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p, int attribute) static tree Case_Statement_to_gnu (Node_Id gnat_node) { - tree gnu_result, gnu_expr, gnu_label; + tree gnu_result, gnu_expr, gnu_type, gnu_label; Node_Id gnat_when; location_t end_locus; bool may_fallthru = false; gnu_expr = gnat_to_gnu (Expression (gnat_node)); gnu_expr = convert (get_base_type (TREE_TYPE (gnu_expr)), gnu_expr); + gnu_expr = maybe_character_value (gnu_expr); + gnu_type = TREE_TYPE (gnu_expr); /* We build a SWITCH_EXPR that contains the code with interspersed CASE_LABEL_EXPRs for each label. */ @@ -2559,6 +2561,11 @@ Case_Statement_to_gnu (Node_Id gnat_node) gcc_assert (!gnu_low || TREE_CODE (gnu_low) == INTEGER_CST); gcc_assert (!gnu_high || TREE_CODE (gnu_high) == INTEGER_CST); + if (gnu_low && TREE_TYPE (gnu_low) != gnu_type) + gnu_low = convert (gnu_type, gnu_low); + if (gnu_high && TREE_TYPE (gnu_high) != gnu_type) + gnu_high = convert (gnu_type, gnu_high); + add_stmt_with_node (build_case_label (gnu_low, gnu_high, label), gnat_choice); choices_added_p = true; @@ -2590,8 +2597,8 @@ Case_Statement_to_gnu (Node_Id gnat_node) /* Now emit a definition of the label the cases branch to, if any. */ if (may_fallthru) add_stmt (build1 (LABEL_EXPR, void_type_node, gnu_label)); - gnu_result = build3 (SWITCH_EXPR, TREE_TYPE (gnu_expr), gnu_expr, - end_stmt_group (), NULL_TREE); + gnu_result + = build3 (SWITCH_EXPR, gnu_type, gnu_expr, end_stmt_group (), NULL_TREE); return gnu_result; } diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 73a882c9e91..ecef102d262 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,22 @@ +2016-07-05 Markus Trippelsdorf <markus@trippelsdorf.de> + + PR c++/71214 + * c-cppbuiltin.c (c_cpp_builtins): Define __cpp_rvalue_references. + +2016-06-14 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-06-10 Jakub Jelinek <jakub@redhat.com> + + PR c/68657 + * c.opt (Wpsabi): Add Warning flag. + +2016-06-13 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/71498 + * c-gimplify.c (ubsan_walk_array_refs_r): Set *walk_subtrees = 0 on + all BIND_EXPRs, and on all BIND_EXPRs recurse also on BIND_EXPR_BODY. + 2016-05-30 Jakub Jelinek <jakub@redhat.com> PR c++/71349 diff --git a/gcc/c-family/c-cppbuiltin.c b/gcc/c-family/c-cppbuiltin.c index 0cd4f1feb54..2f63feaa3fb 100644 --- a/gcc/c-family/c-cppbuiltin.c +++ b/gcc/c-family/c-cppbuiltin.c @@ -935,6 +935,7 @@ c_cpp_builtins (cpp_reader *pfile) cpp_define (pfile, "__cpp_decltype=200707"); cpp_define (pfile, "__cpp_attributes=200809"); cpp_define (pfile, "__cpp_rvalue_reference=200610"); + cpp_define (pfile, "__cpp_rvalue_references=200610"); cpp_define (pfile, "__cpp_variadic_templates=200704"); cpp_define (pfile, "__cpp_initializer_lists=200806"); cpp_define (pfile, "__cpp_delegating_constructors=200604"); diff --git a/gcc/c-family/c-gimplify.c b/gcc/c-family/c-gimplify.c index 0757193beea..c18b057727c 100644 --- a/gcc/c-family/c-gimplify.c +++ b/gcc/c-family/c-gimplify.c @@ -67,23 +67,23 @@ ubsan_walk_array_refs_r (tree *tp, int *walk_subtrees, void *data) { hash_set<tree> *pset = (hash_set<tree> *) data; - /* Since walk_tree doesn't call the callback function on the decls - in BIND_EXPR_VARS, we have to walk them manually. */ if (TREE_CODE (*tp) == BIND_EXPR) { + /* Since walk_tree doesn't call the callback function on the decls + in BIND_EXPR_VARS, we have to walk them manually, so we can avoid + instrumenting DECL_INITIAL of TREE_STATIC vars. */ + *walk_subtrees = 0; for (tree decl = BIND_EXPR_VARS (*tp); decl; decl = DECL_CHAIN (decl)) { if (TREE_STATIC (decl)) - { - *walk_subtrees = 0; - continue; - } + continue; walk_tree (&DECL_INITIAL (decl), ubsan_walk_array_refs_r, pset, pset); walk_tree (&DECL_SIZE (decl), ubsan_walk_array_refs_r, pset, pset); walk_tree (&DECL_SIZE_UNIT (decl), ubsan_walk_array_refs_r, pset, pset); } + walk_tree (&BIND_EXPR_BODY (*tp), ubsan_walk_array_refs_r, pset, pset); } else if (TREE_CODE (*tp) == ADDR_EXPR && TREE_CODE (TREE_OPERAND (*tp, 0)) == ARRAY_REF) diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt index 8b88726f2f0..a79ee9a38af 100644 --- a/gcc/c-family/c.opt +++ b/gcc/c-family/c.opt @@ -265,7 +265,7 @@ C++ ObjC++ Var(warn_abi_tag) Warning Warn if a subobject has an abi_tag attribute that the complete object type does not have. Wpsabi -C ObjC C++ ObjC++ LTO Var(warn_psabi) Init(1) Undocumented LangEnabledBy(C ObjC C++ ObjC++,Wabi) +C ObjC C++ ObjC++ LTO Var(warn_psabi) Init(1) Warning Undocumented LangEnabledBy(C ObjC C++ ObjC++,Wabi) Waddress C ObjC C++ ObjC++ Var(warn_address) Warning LangEnabledBy(C ObjC C++ ObjC++,Wall) diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index fc8921678ba..781a40f021a 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,19 @@ +2016-07-02 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-06-29 Jakub Jelinek <jakub@redhat.com> + + PR c/71685 + * c-typeck.c (c_build_qualified_type): Don't clear + C_TYPE_INCOMPLETE_VARS for the main variant. + +2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + + PR c/71381 + Backport from trunk r237290: + * c-parser.c (c_parser_omp_variable_list) <OMP_CLAUSE__CACHE_>: + Loosen checking. + 2016-05-30 Jakub Jelinek <jakub@redhat.com> PR c++/71349 diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c index 9b0d1c89336..8f8ca505b78 100644 --- a/gcc/c/c-parser.c +++ b/gcc/c/c-parser.c @@ -11153,6 +11153,8 @@ c_parser_omp_variable_list (c_parser *parser, switch (kind) { case OMP_CLAUSE__CACHE_: + /* The OpenACC cache directive explicitly only allows "array + elements or subarrays". */ if (c_parser_peek_token (parser)->type != CPP_OPEN_SQUARE) { c_parser_error (parser, "expected %<[%>"); @@ -11215,25 +11217,6 @@ c_parser_omp_variable_list (c_parser *parser, break; } - if (kind == OMP_CLAUSE__CACHE_) - { - if (TREE_CODE (low_bound) != INTEGER_CST - && !TREE_READONLY (low_bound)) - { - error_at (clause_loc, - "%qD is not a constant", low_bound); - t = error_mark_node; - } - - if (TREE_CODE (length) != INTEGER_CST - && !TREE_READONLY (length)) - { - error_at (clause_loc, - "%qD is not a constant", length); - t = error_mark_node; - } - } - t = tree_cons (low_bound, length, t); } break; diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index ce00f3e1abd..4cd52d36ac3 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -13877,7 +13877,8 @@ c_build_qualified_type (tree type, int type_quals, layout_qualifier)); /* A variant type does not inherit the list of incomplete vars from the type main variant. */ - if (RECORD_OR_UNION_TYPE_P (var_type)) + if (RECORD_OR_UNION_TYPE_P (var_type) + && TYPE_MAIN_VARIANT (var_type) != var_type) C_TYPE_INCOMPLETE_VARS (var_type) = 0; return var_type; } diff --git a/gcc/config.gcc b/gcc/config.gcc index beb50faec22..82cc9a9959b 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4278,9 +4278,9 @@ case "${target}" in esac ;; sparc*-*-*) - supported_defaults="cpu float tune" + supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64" - for which in cpu tune; do + for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do eval "val=\$with_$which" case ${val} in "" | sparc | sparcv9 | sparc64 \ @@ -4289,7 +4289,7 @@ case "${target}" in | sparclite | f930 | f934 | sparclite86x \ | sparclet | tsc701 \ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \ - | niagara3 | niagara4) + | niagara3 | niagara4 | niagara7) # OK ;; *) diff --git a/gcc/config.in b/gcc/config.in index 43b7dc8c90b..042d70c9b11 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -622,6 +622,12 @@ #endif +/* Define if your assembler supports SPARC5 and VIS 4.0 instructions. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_SPARC5_VIS4 +#endif + + /* Define if your assembler and linker support GOTDATA_OP relocs. */ #ifndef USED_FOR_TARGET #undef HAVE_AS_SPARC_GOTDATA_OP diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index dd045792b21..f440907aed3 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -244,13 +244,17 @@ /* Implemented by <maxmin><mode>3. smax variants map to fmaxnm, smax_nan variants map to fmax. */ - BUILTIN_VDQIF (BINOP, smax, 3) - BUILTIN_VDQIF (BINOP, smin, 3) + BUILTIN_VDQ_BHSI (BINOP, smax, 3) + BUILTIN_VDQ_BHSI (BINOP, smin, 3) BUILTIN_VDQ_BHSI (BINOP, umax, 3) BUILTIN_VDQ_BHSI (BINOP, umin, 3) BUILTIN_VDQF (BINOP, smax_nan, 3) BUILTIN_VDQF (BINOP, smin_nan, 3) + /* Implemented by <fmaxmin><mode>3. */ + BUILTIN_VDQF (BINOP, fmax, 3) + BUILTIN_VDQF (BINOP, fmin, 3) + /* Implemented by aarch64_<maxmin_uns>p<mode>. */ BUILTIN_VDQ_BHSI (BINOP, smaxp, 0) BUILTIN_VDQ_BHSI (BINOP, sminp, 0) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 2612a325718..ec543684eda 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -17856,19 +17856,19 @@ vpminnms_f32 (float32x2_t a) __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmaxnm_f32 (float32x2_t __a, float32x2_t __b) { - return __builtin_aarch64_smaxv2sf (__a, __b); + return __builtin_aarch64_fmaxv2sf (__a, __b); } __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vmaxnmq_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_aarch64_smaxv4sf (__a, __b); + return __builtin_aarch64_fmaxv4sf (__a, __b); } __extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) vmaxnmq_f64 (float64x2_t __a, float64x2_t __b) { - return __builtin_aarch64_smaxv2df (__a, __b); + return __builtin_aarch64_fmaxv2df (__a, __b); } /* vmaxv */ @@ -18086,19 +18086,19 @@ vminq_u32 (uint32x4_t __a, uint32x4_t __b) __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vminnm_f32 (float32x2_t __a, float32x2_t __b) { - return __builtin_aarch64_sminv2sf (__a, __b); + return __builtin_aarch64_fminv2sf (__a, __b); } __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vminnmq_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_aarch64_sminv4sf (__a, __b); + return __builtin_aarch64_fminv4sf (__a, __b); } __extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) vminnmq_f64 (float64x2_t __a, float64x2_t __b) { - return __builtin_aarch64_sminv2df (__a, __b); + return __builtin_aarch64_fminv2df (__a, __b); } /* vminv */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9a1a158b1aa..24b204a1d42 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -6704,7 +6704,7 @@ arm_function_ok_for_sibcall (tree decl, tree exp) /* The PIC register is live on entry to VxWorks PLT entries, so we must make the call before restoring the PIC register. */ - if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl)) + if (TARGET_VXWORKS_RTP && flag_pic && decl && !targetm.binds_local_p (decl)) return false; /* If we are interworking and the function is not declared static diff --git a/gcc/config/arm/freebsd.h b/gcc/config/arm/freebsd.h index 948fdd6843e..0ade4e99be1 100644 --- a/gcc/config/arm/freebsd.h +++ b/gcc/config/arm/freebsd.h @@ -120,6 +120,9 @@ #define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9 #endif +/* FreeBSD 10 does not support unaligned access for armv6 and up. + Unaligned access support was added in FreeBSD 11. */ +#if FBSD_MAJOR < 11 #define SUBTARGET_OVERRIDE_INTERNAL_OPTIONS \ do { \ if (opts_set->x_unaligned_access == 1) \ @@ -127,6 +130,7 @@ do { \ if (opts->x_unaligned_access) \ opts->x_unaligned_access = 0; \ } while (0) +#endif #undef MAX_SYNC_LIBFUNC_SIZE #define MAX_SYNC_LIBFUNC_SIZE 4 /* UNITS_PER_WORD not defined yet. */ diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index a7728e3b10c..024717da7ad 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -9721,7 +9721,9 @@ avr_asm_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align) { const char *sname = ACONCAT ((new_prefix, name + strlen (old_prefix), NULL)); - return get_section (sname, sect->common.flags, sect->named.decl); + return get_section (sname, + sect->common.flags & ~SECTION_DECLARED, + sect->named.decl); } } diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index c9884461841..98951865b1e 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -641,6 +641,22 @@ if (avr_mem_flash_p (dest)) DONE; + if (QImode == <MODE>mode + && SUBREG_P (src) + && CONSTANT_ADDRESS_P (SUBREG_REG (src)) + && can_create_pseudo_p()) + { + // store_bitfield may want to store a SYMBOL_REF or CONST in a + // structure that's represented as PSImode. As the upper 16 bits + // of PSImode cannot be expressed as an HImode subreg, the rhs is + // decomposed into QImode (word_mode) subregs of SYMBOL_REF, + // CONST or LABEL_REF; cf. PR71103. + + rtx const_addr = SUBREG_REG (src); + operands[1] = src = copy_rtx (src); + SUBREG_REG (src) = copy_to_mode_reg (GET_MODE (const_addr), const_addr); + } + /* One of the operands has to be in a register. */ if (!register_operand (dest, <MODE>mode) && !reg_or_0_operand (src, <MODE>mode)) diff --git a/gcc/config/avr/gen-avr-mmcu-specs.c b/gcc/config/avr/gen-avr-mmcu-specs.c index de8680a8a1b..fabe8c2c59b 100644 --- a/gcc/config/avr/gen-avr-mmcu-specs.c +++ b/gcc/config/avr/gen-avr-mmcu-specs.c @@ -27,7 +27,7 @@ #include "avr-devices.c" -// Get rid of "defaults.h". We just need tm.h for `WITH_AVRLIBS' and +// Get rid of "defaults.h". We just need tm.h for `WITH_AVRLIBC' and // and `WITH_RTEMS'. */ #define GCC_DEFAULTS_H @@ -242,12 +242,13 @@ print_mcu (const avr_mcu_t *mcu) fprintf (f, "*link_data_start:\n"); if (mcu->data_section_start != arch->default_data_section_start) - fprintf (f, "\t-Tdata 0x%lX", 0x800000UL + mcu->data_section_start); + fprintf (f, "\t%%{!Tdata:-Tdata 0x%lX}", + 0x800000UL + mcu->data_section_start); fprintf (f, "\n\n"); fprintf (f, "*link_text_start:\n"); if (mcu->text_section_start != 0x0) - fprintf (f, "\t-Ttext 0x%lX", 0UL + mcu->text_section_start); + fprintf (f, "\t%%{!Ttext:-Ttext 0x%lX}", 0UL + mcu->text_section_start); fprintf (f, "\n\n"); } diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h index 73b1dbe1c55..6583266cf4e 100644 --- a/gcc/config/darwin.h +++ b/gcc/config/darwin.h @@ -180,6 +180,7 @@ extern GTY(()) int darwin_ms_struct; %{L*} %(link_libgcc) %o %{fprofile-arcs|fprofile-generate*|coverage:-lgcov} \ %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1): \ %{static|static-libgcc|static-libstdc++|static-libgfortran: libgomp.a%s; : -lgomp } } \ + %{fcilkplus:%:include(libcilkrts.spec)%(link_cilkrts)} \ %{fgnu-tm: \ %{static|static-libgcc|static-libstdc++|static-libgfortran: libitm.a%s; : -litm } } \ %{fupc:%:include(libgupc.spec)%(link_upc)} \ diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index b892f086798..86139db4abd 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -292,6 +292,7 @@ DEF_FUNCTION_TYPE (V8DF, V4DF) DEF_FUNCTION_TYPE (V8DF, V2DF) DEF_FUNCTION_TYPE (V16SI, V4SI) DEF_FUNCTION_TYPE (V16SI, V8SI) +DEF_FUNCTION_TYPE (V16SI, V16SF) DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, UHI) DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, UQI) DEF_FUNCTION_TYPE (V8DI, PV8DI) @@ -1035,14 +1036,17 @@ DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT, INT, INT) DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4DF_FTYPE_V4DF, ROUND) +DEF_FUNCTION_TYPE_ALIAS (V8DF_FTYPE_V8DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4SF_FTYPE_V4SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V8SF_FTYPE_V8SF, ROUND) +DEF_FUNCTION_TYPE_ALIAS (V16SF_FTYPE_V16SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4SI_FTYPE_V2DF_V2DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V8SI_FTYPE_V4DF_V4DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V16SI_FTYPE_V8DF_V8DF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V4SI_FTYPE_V4SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (V8SI_FTYPE_V8SF, ROUND) +DEF_FUNCTION_TYPE_ALIAS (V16SI_FTYPE_V16SF, ROUND) DEF_FUNCTION_TYPE_ALIAS (INT_FTYPE_V2DF_V2DF, PTEST) DEF_FUNCTION_TYPE_ALIAS (INT_FTYPE_V2DI_V2DI, PTEST) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 63eb1f2a09b..ff87333b07d 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18802,12 +18802,29 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[]) of the register, once we have that information we may be able to handle some of them more efficiently. */ if (can_create_pseudo_p () - && register_operand (op0, mode) && (CONSTANT_P (op1) || (SUBREG_P (op1) && CONSTANT_P (SUBREG_REG (op1)))) - && !standard_sse_constant_p (op1)) - op1 = validize_mem (force_const_mem (mode, op1)); + && ((register_operand (op0, mode) + && !standard_sse_constant_p (op1)) + /* ix86_expand_vector_move_misalign() does not like constants. */ + || (SSE_REG_MODE_P (mode) + && MEM_P (op0) + && MEM_ALIGN (op0) < align))) + { + if (SUBREG_P (op1)) + { + machine_mode imode = GET_MODE (SUBREG_REG (op1)); + rtx r = force_const_mem (imode, SUBREG_REG (op1)); + if (r) + r = validize_mem (r); + else + r = force_reg (imode, SUBREG_REG (op1)); + op1 = simplify_gen_subreg (mode, r, imode, SUBREG_BYTE (op1)); + } + else + op1 = validize_mem (force_const_mem (mode, op1)); + } /* We need to check memory alignment for SSE mode since attribute can make operands unaligned. */ @@ -18818,13 +18835,8 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[]) { rtx tmp[2]; - /* ix86_expand_vector_move_misalign() does not like constants ... */ - if (CONSTANT_P (op1) - || (SUBREG_P (op1) - && CONSTANT_P (SUBREG_REG (op1)))) - op1 = validize_mem (force_const_mem (mode, op1)); - - /* ... nor both arguments in memory. */ + /* ix86_expand_vector_move_misalign() does not like both + arguments in memory. */ if (!register_operand (op0, mode) && !register_operand (op1, mode)) op1 = force_reg (mode, op1); @@ -18910,7 +18922,7 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1) m = adjust_address (op0, mode, 0); emit_insn (extract (m, op1, const0_rtx)); m = adjust_address (op0, mode, 16); - emit_insn (extract (m, op1, const1_rtx)); + emit_insn (extract (m, copy_rtx (op1), const1_rtx)); } else emit_insn (store_unaligned (op0, op1)); @@ -19218,7 +19230,7 @@ ix86_expand_vector_move_misalign (machine_mode mode, rtx operands[]) m = adjust_address (op0, V2SFmode, 0); emit_insn (gen_sse_storelps (m, op1)); m = adjust_address (op0, V2SFmode, 8); - emit_insn (gen_sse_storehps (m, op1)); + emit_insn (gen_sse_storehps (m, copy_rtx (op1))); } } } @@ -23042,17 +23054,33 @@ ix86_fp_cmp_code_to_pcmp_immediate (enum rtx_code code) switch (code) { case EQ: - return 0x08; + return 0x00; case NE: return 0x04; case GT: - return 0x16; + return 0x0e; case LE: - return 0x1a; + return 0x02; case GE: - return 0x15; + return 0x0d; case LT: - return 0x19; + return 0x01; + case UNLE: + return 0x0a; + case UNLT: + return 0x09; + case UNGE: + return 0x05; + case UNGT: + return 0x06; + case UNEQ: + return 0x18; + case LTGT: + return 0x0c; + case ORDERED: + return 0x07; + case UNORDERED: + return 0x03; default: gcc_unreachable (); } @@ -30701,7 +30729,7 @@ enum ix86_builtins IX86_BUILTIN_CVTPD2PS512, IX86_BUILTIN_CVTPD2UDQ512, IX86_BUILTIN_CVTPH2PS512, - IX86_BUILTIN_CVTPS2DQ512, + IX86_BUILTIN_CVTPS2DQ512_MASK, IX86_BUILTIN_CVTPS2PD512, IX86_BUILTIN_CVTPS2PH512, IX86_BUILTIN_CVTPS2UDQ512, @@ -32141,14 +32169,25 @@ enum ix86_builtins IX86_BUILTIN_COPYSIGNQ, /* Vectorizer support builtins. */ - IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, IX86_BUILTIN_CPYSGNPS, IX86_BUILTIN_CPYSGNPD, IX86_BUILTIN_CPYSGNPS256, IX86_BUILTIN_CPYSGNPS512, IX86_BUILTIN_CPYSGNPD256, IX86_BUILTIN_CPYSGNPD512, + IX86_BUILTIN_FLOORPS512, + IX86_BUILTIN_FLOORPD512, + IX86_BUILTIN_CEILPS512, + IX86_BUILTIN_CEILPD512, + IX86_BUILTIN_TRUNCPS512, + IX86_BUILTIN_TRUNCPD512, + IX86_BUILTIN_CVTPS2DQ512, + IX86_BUILTIN_VEC_PACK_SFIX512, + IX86_BUILTIN_FLOORPS_SFIX512, IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, + IX86_BUILTIN_CEILPS_SFIX512, + IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, + IX86_BUILTIN_ROUNDPS_AZ_SFIX512, IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, @@ -33963,6 +34002,17 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF }, { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512, "__builtin_ia32_floorps512", IX86_BUILTIN_FLOORPS512, (enum rtx_code) ROUND_FLOOR, (int) V16SF_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512, "__builtin_ia32_ceilps512", IX86_BUILTIN_CEILPS512, (enum rtx_code) ROUND_CEIL, (int) V16SF_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512, "__builtin_ia32_truncps512", IX86_BUILTIN_TRUNCPS512, (enum rtx_code) ROUND_TRUNC, (int) V16SF_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd512, "__builtin_ia32_floorpd512", IX86_BUILTIN_FLOORPD512, (enum rtx_code) ROUND_FLOOR, (int) V8DF_FTYPE_V8DF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd512, "__builtin_ia32_ceilpd512", IX86_BUILTIN_CEILPD512, (enum rtx_code) ROUND_CEIL, (int) V8DF_FTYPE_V8DF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd512, "__builtin_ia32_truncpd512", IX86_BUILTIN_TRUNCPD512, (enum rtx_code) ROUND_TRUNC, (int) V8DF_FTYPE_V8DF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si, "__builtin_ia32_cvtps2dq512", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_pack_sfix_v8df, "__builtin_ia32_vec_pack_sfix512", IX86_BUILTIN_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv16sf2_sfix, "__builtin_ia32_roundps_az_sfix512", IX86_BUILTIN_ROUNDPS_AZ_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V16SF }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512_sfix, "__builtin_ia32_floorps_sfix512", IX86_BUILTIN_FLOORPS_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V16SF_ROUND }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundps512_sfix, "__builtin_ia32_ceilps_sfix512", IX86_BUILTIN_CEILPS_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V16SF_ROUND }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND }, @@ -34879,7 +34929,7 @@ static const struct builtin_description bdesc_round_args[] = { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT }, - { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT }, @@ -38456,10 +38506,13 @@ ix86_expand_args_builtin (const struct builtin_description *d, { case V2DF_FTYPE_V2DF_ROUND: case V4DF_FTYPE_V4DF_ROUND: + case V8DF_FTYPE_V8DF_ROUND: case V4SF_FTYPE_V4SF_ROUND: case V8SF_FTYPE_V8SF_ROUND: + case V16SF_FTYPE_V16SF_ROUND: case V4SI_FTYPE_V4SF_ROUND: case V8SI_FTYPE_V8SF_ROUND: + case V16SI_FTYPE_V16SF_ROUND: return ix86_expand_sse_round (d, exp, target); case V4SI_FTYPE_V2DF_V2DF_ROUND: case V8SI_FTYPE_V4DF_V4DF_ROUND: @@ -38573,6 +38626,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V16SI_FTYPE_V8SI: case V16SF_FTYPE_V4SF: case V16SI_FTYPE_V4SI: + case V16SI_FTYPE_V16SF: case V16SF_FTYPE_V16SF: case V8DI_FTYPE_UQI: case V8DF_FTYPE_V4DF: @@ -42278,6 +42332,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX512); } break; @@ -42303,6 +42359,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX512); } break; @@ -42315,6 +42373,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX); else if (out_n == 8 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX256); + else if (out_n == 16 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX512); } if (out_mode == SImode && in_mode == SFmode) { @@ -42322,6 +42382,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ512); } break; @@ -42347,6 +42409,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX512); } break; @@ -42361,6 +42425,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_FLOORPD); else if (out_n == 4 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_FLOORPD256); + else if (out_n == 8 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_FLOORPD512); } if (out_mode == SFmode && in_mode == SFmode) { @@ -42368,6 +42434,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_FLOORPS); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_FLOORPS256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_FLOORPS512); } break; @@ -42382,6 +42450,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CEILPD); else if (out_n == 4 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_CEILPD256); + else if (out_n == 8 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_CEILPD512); } if (out_mode == SFmode && in_mode == SFmode) { @@ -42389,6 +42459,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_CEILPS); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_CEILPS256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_CEILPS512); } break; @@ -42403,6 +42475,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_TRUNCPD); else if (out_n == 4 && in_n == 4) return ix86_get_builtin (IX86_BUILTIN_TRUNCPD256); + else if (out_n == 8 && in_n == 8) + return ix86_get_builtin (IX86_BUILTIN_TRUNCPD512); } if (out_mode == SFmode && in_mode == SFmode) { @@ -42410,6 +42484,8 @@ ix86_builtin_vectorized_function (unsigned int fn, tree type_out, return ix86_get_builtin (IX86_BUILTIN_TRUNCPS); else if (out_n == 8 && in_n == 8) return ix86_get_builtin (IX86_BUILTIN_TRUNCPS256); + else if (out_n == 16 && in_n == 16) + return ix86_get_builtin (IX86_BUILTIN_TRUNCPS512); } break; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index b1780a7bcad..c4c4cd85934 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11856,8 +11856,7 @@ "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) && ! reg_overlap_mentioned_p (operands[3], operands[0]) - && ! (GET_CODE (operands[4]) == CLOBBER - && reg_mentioned_p (operands[3], operands[4]))" + && ! reg_set_p (operands[3], operands[4])" [(parallel [(set (match_dup 5) (match_dup 0)) (match_dup 4)]) (set (strict_low_part (match_dup 6)) @@ -11901,8 +11900,7 @@ "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) && ! reg_overlap_mentioned_p (operands[3], operands[0]) - && ! (GET_CODE (operands[4]) == CLOBBER - && reg_mentioned_p (operands[3], operands[4]))" + && ! reg_set_p (operands[3], operands[4])" [(parallel [(set (match_dup 5) (match_dup 0)) (match_dup 4)]) (set (strict_low_part (match_dup 6)) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a30b0b84501..42506efc52c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4488,7 +4488,7 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<mask_codefor>avx512f_fix_notruncv16sfv16si<mask_name><round_name>" +(define_insn "avx512f_fix_notruncv16sfv16si<mask_name><round_name>" [(set (match_operand:V16SI 0 "register_operand" "=v") (unspec:V16SI [(match_operand:V16SF 1 "<round_nimm_predicate>" "<round_constraint>")] @@ -5046,7 +5046,7 @@ (set_attr "ssememalign" "64") (set_attr "mode" "V2DF")]) -(define_insn "<mask_codefor>avx512f_cvtpd2dq512<mask_name><round_name>" +(define_insn "avx512f_cvtpd2dq512<mask_name><round_name>" [(set (match_operand:V8SI 0 "register_operand" "=v") (unspec:V8SI [(match_operand:V8DF 1 "<round_nimm_predicate>" "<round_constraint>")] @@ -6006,6 +6006,23 @@ DONE; }) +(define_expand "avx512f_vec_pack_sfix_v8df" + [(match_operand:V16SI 0 "register_operand") + (match_operand:V8DF 1 "nonimmediate_operand") + (match_operand:V8DF 2 "nonimmediate_operand")] + "TARGET_AVX512F" +{ + rtx r1, r2; + + r1 = gen_reg_rtx (V8SImode); + r2 = gen_reg_rtx (V8SImode); + + emit_insn (gen_avx512f_cvtpd2dq512 (r1, operands[1])); + emit_insn (gen_avx512f_cvtpd2dq512 (r2, operands[2])); + emit_insn (gen_avx_vec_concatv16si (operands[0], r1, r2)); + DONE; +}) + (define_expand "vec_pack_sfix_v4df" [(match_operand:V8SI 0 "register_operand") (match_operand:V4DF 1 "nonimmediate_operand") @@ -15247,13 +15264,25 @@ DONE; }) -(define_expand "avx512f_roundpd512" - [(match_operand:V8DF 0 "register_operand") - (match_operand:V8DF 1 "nonimmediate_operand") +(define_expand "avx512f_round<castmode>512" + [(match_operand:VF_512 0 "register_operand") + (match_operand:VF_512 1 "nonimmediate_operand") + (match_operand:SI 2 "const_0_to_15_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_rndscale<mode> (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "avx512f_roundps512_sfix" + [(match_operand:V16SI 0 "register_operand") + (match_operand:V16SF 1 "nonimmediate_operand") (match_operand:SI 2 "const_0_to_15_operand")] "TARGET_AVX512F" { - emit_insn (gen_avx512f_rndscalev8df (operands[0], operands[1], operands[2])); + rtx tmp = gen_reg_rtx (V16SFmode); + emit_insn (gen_avx512f_rndscalev16sf (tmp, operands[1], operands[2])); + emit_insn (gen_fix_truncv16sfv16si2 (operands[0], tmp)); DONE; }) @@ -15353,7 +15382,7 @@ (define_expand "round<mode>2_sfix" [(match_operand:<sseintvecmode> 0 "register_operand") - (match_operand:VF1_128_256 1 "register_operand")] + (match_operand:VF1 1 "register_operand")] "TARGET_ROUND && !flag_trapping_math" { rtx tmp = gen_reg_rtx (<MODE>mode); diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index 91e5cffaa32..98d9ae02ba4 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -119,6 +119,6 @@ "bpu_40x") (define_insn_reservation "ppc405-float" 11 - (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv") + (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv") (eq_attr "cpu" "ppc405")) "fpu_405*10") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index 6d07ef3ea3c..c33f4accb00 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -107,7 +107,7 @@ "ppc440_issue,ppc440_f_pipe+ppc440_i_pipe") (define_insn_reservation "ppc440-fp" 5 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_f_pipe") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index 8c266b992da..4cae8fcc9e0 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -124,7 +124,7 @@ ppc476_f_pipe+ppc476_i_pipe") (define_insn_reservation "ppc476-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "ppc476")) "ppc476_issue_fp,\ ppc476_f_pipe") diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index e34c9bf20f1..aa869d86d8a 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -86,7 +86,7 @@ "(fpu_ppc601+iu_ppc601*2),nothing*2,bpu_ppc601") (define_insn_reservation "ppc601-fp" 4 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc601")) "fpu_ppc601") diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md index 3b07461bf0e..052c1c1c95a 100644 --- a/gcc/config/rs6000/603.md +++ b/gcc/config/rs6000/603.md @@ -105,7 +105,7 @@ "(fpu_603+iu_603*2),bpu_603") (define_insn_reservation "ppc603-fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc603")) "fpu_603") diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md index 29893aeeefd..3ab80a2b263 100644 --- a/gcc/config/rs6000/6xx.md +++ b/gcc/config/rs6000/6xx.md @@ -160,7 +160,7 @@ "fpu_6xx") (define_insn_reservation "ppc604-fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc604,ppc604e,ppc620")) "fpu_6xx") diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md index 81463693999..0ebf6fa0cd5 100644 --- a/gcc/config/rs6000/7450.md +++ b/gcc/config/rs6000/7450.md @@ -120,7 +120,7 @@ "ppc7450_du,fpu_7450") (define_insn_reservation "ppc7450-fp" 5 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "ppc7450")) "ppc7450_du,fpu_7450") @@ -162,7 +162,7 @@ ;; Altivec (define_insn_reservation "ppc7450-vecsimple" 1 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "ppc7450")) "ppc7450_du,ppc7450_vec_du,vecsmpl_7450") @@ -172,7 +172,7 @@ "ppc7450_du,ppc7450_vec_du,veccmplx_7450") (define_insn_reservation "ppc7450-veccmp" 2 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "ppc7450")) "ppc7450_du,ppc7450_vec_du,veccmplx_7450") diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md index 1da48b77fd9..70e2eb17f12 100644 --- a/gcc/config/rs6000/7xx.md +++ b/gcc/config/rs6000/7xx.md @@ -113,7 +113,7 @@ "ppc750_du,fpu_7xx") (define_insn_reservation "ppc750-fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc750,ppc7400")) "ppc750_du,fpu_7xx") @@ -165,7 +165,7 @@ ;; Altivec (define_insn_reservation "ppc7400-vecsimple" 1 - (and (eq_attr "type" "vecsimple,veccmp") + (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") (eq_attr "cpu" "ppc7400")) "ppc750_du,ppc7400_vec_du,veccmplx_7xx") diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md index ae4e45f89bb..f39f1f67513 100644 --- a/gcc/config/rs6000/8540.md +++ b/gcc/config/rs6000/8540.md @@ -190,7 +190,7 @@ ;; Simple vector (define_insn_reservation "ppc8540_simple_vector" 1 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "ppc8540,ppc8548")) "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") @@ -202,7 +202,7 @@ ;; Vector compare (define_insn_reservation "ppc8540_vector_compare" 1 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "ppc8540,ppc8548")) "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md index 1fcf1cfb204..e0b800ce61b 100644 --- a/gcc/config/rs6000/a2.md +++ b/gcc/config/rs6000/a2.md @@ -81,7 +81,7 @@ ;; D.8.1 (define_insn_reservation "ppca2-fp" 6 - (and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only). + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppca2")) "axu") diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index f9fac682b7b..f77d4466469 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -399,6 +399,14 @@ #ifdef _ARCH_PPC64 #define vec_vprtybq __builtin_vec_vprtybq #endif + +#define vec_slv __builtin_vec_vslv +#define vec_srv __builtin_vec_vsrv + +#define vec_absd __builtin_vec_vadu +#define vec_absdb __builtin_vec_vadub +#define vec_absdh __builtin_vec_vaduh +#define vec_absdw __builtin_vec_vaduw #endif /* Predicates. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 3707091019a..362fa221c1e 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -114,6 +114,9 @@ UNSPEC_STVLXL UNSPEC_STVRX UNSPEC_STVRXL + UNSPEC_VSLV + UNSPEC_VSRV + UNSPEC_VADU UNSPEC_VMULWHUB UNSPEC_VMULWLUB UNSPEC_VMULWHSB @@ -239,7 +242,7 @@ default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*") + [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*,*") (set_attr "length" "4,4,4,20,20,20,4,8,32")]) ;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode @@ -265,7 +268,7 @@ default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")]) + [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*")]) ;; Load up a vector with the most significant bit set by loading up -1 and ;; doing a shift left @@ -600,7 +603,7 @@ (match_operand:VI2 2 "altivec_register_operand" "v")))] "<VI_unit>" "vcmpequ<VI_char> %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_gt<mode>" [(set (match_operand:VI2 0 "altivec_register_operand" "=v") @@ -608,7 +611,7 @@ (match_operand:VI2 2 "altivec_register_operand" "v")))] "<VI_unit>" "vcmpgts<VI_char> %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_gtu<mode>" [(set (match_operand:VI2 0 "altivec_register_operand" "=v") @@ -616,7 +619,7 @@ (match_operand:VI2 2 "altivec_register_operand" "v")))] "<VI_unit>" "vcmpgtu<VI_char> %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_eqv4sf" [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") @@ -651,7 +654,7 @@ (match_operand:VM 3 "altivec_register_operand" "v")))] "VECTOR_MEM_ALTIVEC_P (<MODE>mode)" "vsel %0,%3,%2,%1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) (define_insn "*altivec_vsel<mode>_uns" [(set (match_operand:VM 0 "altivec_register_operand" "=v") @@ -662,7 +665,7 @@ (match_operand:VM 3 "altivec_register_operand" "v")))] "VECTOR_MEM_ALTIVEC_P (<MODE>mode)" "vsel %0,%3,%2,%1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) ;; Fused multiply add. @@ -1631,6 +1634,24 @@ "vslo %0,%1,%2" [(set_attr "type" "vecperm")]) +(define_insn "vslv" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VSLV))] + "TARGET_P9_VECTOR" + "vslv %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "vsrv" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VSRV))] + "TARGET_P9_VECTOR" + "vsrv %0,%1,%2" + [(set_attr "type" "vecsimple")]) + (define_insn "*altivec_vsl<VI_char>" [(set (match_operand:VI2 0 "register_operand" "=v") (ashift:VI2 (match_operand:VI2 1 "register_operand" "v") @@ -1964,27 +1985,27 @@ ;; Slightly prefer vperm, since the target does not overlap the source (define_insn "*altivec_vperm_<mode>_internal" [(set (match_operand:VM 0 "register_operand" "=v,?wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,0") - (match_operand:VM 2 "register_operand" "v,wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") + (match_operand:VM 2 "register_operand" "v,0") (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3" + xxperm %x0,%x1,%x3" [(set_attr "type" "vecperm") (set_attr "length" "4")]) (define_insn "altivec_vperm_v8hiv16qi" [(set (match_operand:V16QI 0 "register_operand" "=v,?wo") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,0") - (match_operand:V8HI 2 "register_operand" "v,wo") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wo") + (match_operand:V8HI 2 "register_operand" "v,0") (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERM))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3" + xxperm %x0,%x1,%x3" [(set_attr "type" "vecperm") (set_attr "length" "4")]) @@ -2005,14 +2026,14 @@ (define_insn "*altivec_vperm_<mode>_uns_internal" [(set (match_operand:VM 0 "register_operand" "=v,?wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,0") - (match_operand:VM 2 "register_operand" "v,wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") + (match_operand:VM 2 "register_operand" "v,0") (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3" + xxperm %x0,%x1,%x3" [(set_attr "type" "vecperm") (set_attr "length" "4")]) @@ -2045,14 +2066,14 @@ (define_insn "*altivec_vpermr_<mode>_internal" [(set (match_operand:VM 0 "register_operand" "=v,?wo") - (unspec:VM [(match_operand:VM 1 "register_operand" "v,0") - (match_operand:VM 2 "register_operand" "v,wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") + (match_operand:VM 2 "register_operand" "v,0") (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERMR))] "TARGET_P9_VECTOR" "@ - vpermr %0,%1,%2,%3 - xxpermr %x0,%x2,%x3" + vpermr %0,%2,%1,%3 + xxpermr %x0,%x1,%x3" [(set_attr "type" "vecperm") (set_attr "length" "4")]) @@ -2262,7 +2283,7 @@ (match_dup 2)))] "<VI_unit>" "vcmpequ<VI_char>. %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgts<VI_char>_p" [(set (reg:CC 74) @@ -2274,7 +2295,7 @@ (match_dup 2)))] "<VI_unit>" "vcmpgts<VI_char>. %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgtu<VI_char>_p" [(set (reg:CC 74) @@ -2286,7 +2307,7 @@ (match_dup 2)))] "<VI_unit>" "vcmpgtu<VI_char>. %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpeqfp_p" [(set (reg:CC 74) @@ -2824,27 +2845,27 @@ (define_insn "vperm_v8hiv4si" [(set (match_operand:V4SI 0 "register_operand" "=v,?wo") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,0") - (match_operand:V4SI 2 "register_operand" "v,wo") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wo") + (match_operand:V4SI 2 "register_operand" "v,0") (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERMSI))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3" + xxperm %x0,%x1,%x3" [(set_attr "type" "vecperm") (set_attr "length" "4")]) (define_insn "vperm_v16qiv8hi" [(set (match_operand:V8HI 0 "register_operand" "=v,?wo") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,0") - (match_operand:V8HI 2 "register_operand" "v,wo") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wo") + (match_operand:V8HI 2 "register_operand" "v,0") (match_operand:V16QI 3 "register_operand" "v,wo")] UNSPEC_VPERMHI))] "TARGET_ALTIVEC" "@ vperm %0,%1,%2,%3 - xxperm %x0,%x2,%x3" + xxperm %x0,%x1,%x3" [(set_attr "type" "vecperm") (set_attr "length" "4")]) @@ -3394,6 +3415,24 @@ [(set_attr "length" "4") (set_attr "type" "vecsimple")]) +;; Vector absolute difference unsigned +(define_expand "vadu<mode>3" + [(set (match_operand:VI 0 "register_operand") + (unspec:VI [(match_operand:VI 1 "register_operand") + (match_operand:VI 2 "register_operand")] + UNSPEC_VADU))] + "TARGET_P9_VECTOR") + +;; Vector absolute difference unsigned +(define_insn "*p9_vadu<mode>3" + [(set (match_operand:VI 0 "register_operand" "=v") + (unspec:VI [(match_operand:VI 1 "register_operand" "v") + (match_operand:VI 2 "register_operand" "v")] + UNSPEC_VADU))] + "TARGET_P9_VECTOR" + "vabsdu<wd> %0,%1,%2" + [(set_attr "type" "vecsimple")]) + ;; Vector count trailing zeros (define_insn "*p9v_ctz<mode>2" [(set (match_operand:VI2 0 "register_operand" "=v") @@ -3591,21 +3630,21 @@ (define_insn "darn_32" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] - "TARGET_MODULO" + "TARGET_P9_MISC" "darn %0,0" [(set_attr "type" "integer")]) (define_insn "darn_raw" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] - "TARGET_MODULO && TARGET_64BIT" + "TARGET_P9_MISC && TARGET_64BIT" "darn %0,2" [(set_attr "type" "integer")]) (define_insn "darn" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(const_int 0)] UNSPEC_DARN))] - "TARGET_MODULO && TARGET_64BIT" + "TARGET_P9_MISC && TARGET_64BIT" "darn %0,1" [(set_attr "type" "integer")]) diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index b780f09efe0..7eee77cd5f1 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -306,7 +306,7 @@ ; Basic FP latency is 10 cycles, thoughput is 1/cycle (define_insn_reservation "cell-fp" 10 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "cell")) "slot01,vsu1_cell,vsu1_cell*8") @@ -329,7 +329,7 @@ ; VMX (define_insn_reservation "cell-vecsimple" 4 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "cell")) "slot01,vsu1_cell,vsu1_cell*2") @@ -341,7 +341,7 @@ ;; TODO: add support for recording instructions (define_insn_reservation "cell-veccmp" 4 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "cell")) "slot01,vsu1_cell,vsu1_cell*2") diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index a3abe6ab80a..ef8f617d9a8 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -140,6 +140,10 @@ (and (match_code "const_int") (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) +(define_constraint "wE" + "Vector constant that can be loaded with the XXSPLTIB instruction." + (match_test "xxspltib_constant_nosplit (op, mode)")) + ;; Extended fusion store (define_memory_constraint "wF" "Memory operand suitable for power9 fusion load/stores" @@ -156,6 +160,12 @@ (and (match_test "TARGET_DIRECT_MOVE_128") (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)")))) +;; Generate the XXORC instruction to set a register to all 1's +(define_constraint "wM" + "Match vector constant with all 1's if the XXLORC instruction is available" + (and (match_test "TARGET_P8_VECTOR") + (match_operand 0 "all_ones_constant"))) + ;; ISA 3.0 vector d-form addresses (define_memory_constraint "wO" "Memory operand suitable for the ISA 3.0 vector d-form instructions." @@ -166,6 +176,10 @@ "Memory operand suitable for the load/store quad instructions" (match_operand 0 "quad_memory_operand")) +(define_constraint "wS" + "Vector constant that can be loaded with XXSPLTIB & sign extension." + (match_test "xxspltib_constant_split (op, mode)")) + ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" "Indexed or indirect memory operand, ignoring the bottom 4 bits" diff --git a/gcc/config/rs6000/crypto.md b/gcc/config/rs6000/crypto.md index 5957abb8f5d..83a26aef365 100644 --- a/gcc/config/rs6000/crypto.md +++ b/gcc/config/rs6000/crypto.md @@ -107,4 +107,4 @@ UNSPEC_VSHASIGMA))] "TARGET_CRYPTO" "vshasigma<CR_char> %0,%1,%2,%3" - [(set_attr "type" "crypto")]) + [(set_attr "type" "vecsimple")]) diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index a631ff5fd9e..e6ed70ed8ec 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -58,7 +58,7 @@ (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))] "TARGET_DFP" "dctdp %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_expand "extendsdtd2" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") @@ -76,7 +76,7 @@ (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "drsp %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_expand "negdd2" [(set (match_operand:DD 0 "gpc_reg_operand" "") @@ -89,7 +89,7 @@ (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" "fneg %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_expand "absdd2" [(set (match_operand:DD 0 "gpc_reg_operand" "") @@ -102,14 +102,14 @@ (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" "fabs %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_insn "*nabsdd2_fpr" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))] "TARGET_HARD_FLOAT && TARGET_FPRS" "fnabs %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_expand "negtd2" [(set (match_operand:TD 0 "gpc_reg_operand" "") @@ -124,7 +124,7 @@ "@ fneg %0,%1 fneg %0,%1\;fmr %L0,%L1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "4,8")]) (define_expand "abstd2" @@ -140,7 +140,7 @@ "@ fabs %0,%1 fabs %0,%1\;fmr %L0,%L1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "4,8")]) (define_insn "*nabstd2_fpr" @@ -150,7 +150,7 @@ "@ fnabs %0,%1 fnabs %0,%1\;fmr %L0,%L1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "4,8")]) ;; Hardware support for decimal floating point operations. @@ -160,7 +160,7 @@ (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dctqpq %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) ;; The result of drdpq is an even/odd register pair with the converted ;; value in the even register and zero in the odd register. @@ -173,7 +173,7 @@ (clobber (match_scratch:TD 2 "=d"))] "TARGET_DFP" "drdpq %2,%1\;fmr %0,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "adddd3" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") @@ -181,7 +181,7 @@ (match_operand:DD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dadd %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "addtd3" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") @@ -189,7 +189,7 @@ (match_operand:TD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "daddq %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "subdd3" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") @@ -197,7 +197,7 @@ (match_operand:DD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dsub %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "subtd3" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") @@ -205,7 +205,7 @@ (match_operand:TD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dsubq %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "muldd3" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") @@ -213,7 +213,7 @@ (match_operand:DD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dmul %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "multd3" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") @@ -221,7 +221,7 @@ (match_operand:TD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dmulq %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "divdd3" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") @@ -229,7 +229,7 @@ (match_operand:DD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "ddiv %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "divtd3" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") @@ -237,7 +237,7 @@ (match_operand:TD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "ddivq %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "*cmpdd_internal1" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") @@ -245,7 +245,7 @@ (match_operand:DD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dcmpu %0,%1,%2" - [(set_attr "type" "fpcompare")]) + [(set_attr "type" "dfp")]) (define_insn "*cmptd_internal1" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") @@ -253,21 +253,21 @@ (match_operand:TD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dcmpuq %0,%1,%2" - [(set_attr "type" "fpcompare")]) + [(set_attr "type" "dfp")]) (define_insn "floatdidd2" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))] "TARGET_DFP && TARGET_POPCNTD" "dcffix %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "floatditd2" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dcffixq %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) ;; Convert a decimal64 to a decimal64 whose value is an integer. ;; This is the first stage of converting it to an integer type. @@ -277,7 +277,7 @@ (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "drintn. 0,%0,%1,1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) ;; Convert a decimal64 whose value is an integer to an actual integer. ;; This is the second stage of converting decimal float to integer type. @@ -287,7 +287,7 @@ (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dctfix %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) ;; Convert a decimal128 to a decimal128 whose value is an integer. ;; This is the first stage of converting it to an integer type. @@ -297,7 +297,7 @@ (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "drintnq. 0,%0,%1,1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) ;; Convert a decimal128 whose value is an integer to an actual integer. ;; This is the second stage of converting decimal float to integer type. @@ -307,7 +307,7 @@ (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dctfixq %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) ;; Decimal builtin support @@ -318,8 +318,11 @@ UNSPEC_DXEX UNSPEC_DIEX UNSPEC_DSCLI + UNSPEC_DTSTSFI UNSPEC_DSCRI]) +(define_code_iterator DFP_TEST [eq lt gt unordered]) + (define_mode_iterator D64_D128 [DD TD]) (define_mode_attr dfp_suffix [(DD "") @@ -332,7 +335,7 @@ UNSPEC_DDEDPD))] "TARGET_DFP" "ddedpd<dfp_suffix> %1,%0,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "dfp_denbcd_<mode>" [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") @@ -341,7 +344,7 @@ UNSPEC_DENBCD))] "TARGET_DFP" "denbcd<dfp_suffix> %1,%0,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "dfp_dxex_<mode>" [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") @@ -349,7 +352,7 @@ UNSPEC_DXEX))] "TARGET_DFP" "dxex<dfp_suffix> %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "dfp_diex_<mode>" [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") @@ -358,6 +361,42 @@ UNSPEC_DXEX))] "TARGET_DFP" "diex<dfp_suffix> %0,%1,%2" + [(set_attr "type" "dfp")]) + +(define_expand "dfptstsfi_<code>_<mode>" + [(set (match_dup 3) + (compare:CCFP + (unspec:D64_D128 + [(match_operand:SI 1 "const_int_operand" "n") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DTSTSFI) + (match_dup 4))) + (set (match_operand:SI 0 "register_operand" "") + (DFP_TEST:SI (match_dup 3) + (const_int 0))) + ] + "TARGET_P9_MISC" +{ + operands[3] = gen_reg_rtx (CCFPmode); + operands[4] = const0_rtx; +}) + +(define_insn "*dfp_sgnfcnc_<mode>" + [(set (match_operand:CCFP 0 "" "=y") + (compare:CCFP + (unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DTSTSFI) + (match_operand:SI 3 "zero_constant" "j")))] + "TARGET_P9_MISC" +{ + /* If immediate operand is greater than 63, it will behave as if + the value had been 63. The code generator does not support + immediate operand values greater than 63. */ + if (!(IN_RANGE (INTVAL (operands[1]), 0, 63))) + operands[1] = GEN_INT (63); + return "dtstsfi<dfp_suffix> %0,%1,%2"; +} [(set_attr "type" "fp")]) (define_insn "dfp_dscli_<mode>" @@ -367,7 +406,7 @@ UNSPEC_DSCLI))] "TARGET_DFP" "dscli<dfp_suffix> %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) (define_insn "dfp_dscri_<mode>" [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") @@ -376,4 +415,4 @@ UNSPEC_DSCRI))] "TARGET_DFP" "dscri<dfp_suffix> %0,%1,%2" - [(set_attr "type" "fp")]) + [(set_attr "type" "dfp")]) diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md index 5865e95e2d2..e48979979ab 100644 --- a/gcc/config/rs6000/e300c2c3.md +++ b/gcc/config/rs6000/e300c2c3.md @@ -150,7 +150,7 @@ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") (define_insn_reservation "ppce300c3_fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppce300c3")) "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md index 428222d14bf..e094192d61d 100644 --- a/gcc/config/rs6000/e6500.md +++ b/gcc/config/rs6000/e6500.md @@ -205,7 +205,7 @@ ;; VSFX. (define_insn_reservation "e6500_vecsimple" 1 - (and (eq_attr "type" "vecsimple,veccmp") + (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") (eq_attr "cpu" "ppce6500")) "e6500_decode,e6500_vec") diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md index 0d0823824a8..c0203a9c0ca 100644 --- a/gcc/config/rs6000/htm.md +++ b/gcc/config/rs6000/htm.md @@ -72,7 +72,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabort. %0" - [(set_attr "type" "htm") + [(set_attr "type" "htmsimple") (set_attr "length" "4")]) (define_expand "tabort<wd>c" @@ -98,7 +98,7 @@ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabort<wd>c. %0,%1,%2" - [(set_attr "type" "htm") + [(set_attr "type" "htmsimple") (set_attr "length" "4")]) (define_expand "tabort<wd>ci" @@ -124,7 +124,7 @@ (set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabort<wd>ci. %0,%1,%2" - [(set_attr "type" "htm") + [(set_attr "type" "htmsimple") (set_attr "length" "4")]) (define_expand "tbegin" @@ -208,7 +208,7 @@ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "trechkpt." - [(set_attr "type" "htm") + [(set_attr "type" "htmsimple") (set_attr "length" "4")]) (define_expand "treclaim" @@ -230,7 +230,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "treclaim. %0" - [(set_attr "type" "htm") + [(set_attr "type" "htmsimple") (set_attr "length" "4")]) (define_expand "tsr" @@ -252,7 +252,7 @@ (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tsr. %0" - [(set_attr "type" "htm") + [(set_attr "type" "htmsimple") (set_attr "length" "4")]) (define_expand "ttest" @@ -272,7 +272,7 @@ (set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))] "TARGET_HTM" "tabortwci. 0,1,0" - [(set_attr "type" "htm") + [(set_attr "type" "htmsimple") (set_attr "length" "4")]) (define_insn "htm_mfspr_<mode>" diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md index 010dc9444e0..42cb11a5980 100644 --- a/gcc/config/rs6000/mpc.md +++ b/gcc/config/rs6000/mpc.md @@ -81,7 +81,7 @@ "fpu_mpc,bpu_mpc") (define_insn_reservation "mpccore-fp" 4 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "mpccore")) "fpu_mpc*2") diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index 7b0ccbedaac..84ac439fe97 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -381,7 +381,7 @@ ; Basic FP latency is 6 cycles (define_insn_reservation "power4-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "power4")) "fpq_power4") @@ -410,7 +410,7 @@ ; VMX (define_insn_reservation "power4-vecsimple" 2 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "power4")) "vq_power4") @@ -421,7 +421,7 @@ ; vecfp compare (define_insn_reservation "power4-veccmp" 8 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "power4")) "vq_power4") diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index 2d7c15e59c0..b00d5ead143 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -322,7 +322,7 @@ ; Basic FP latency is 6 cycles (define_insn_reservation "power5-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "power5")) "fpq_power5") diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md index 15d31eb81a2..a94052417e9 100644 --- a/gcc/config/rs6000/power6.md +++ b/gcc/config/rs6000/power6.md @@ -500,7 +500,7 @@ (define_bypass 9 "power6-mtcr" "power6-branch") (define_insn_reservation "power6-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul,dfp") (eq_attr "cpu" "power6")) "FPU_power6") @@ -556,7 +556,7 @@ "LSF_power6") (define_insn_reservation "power6-vecsimple" 3 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "power6")) "FPU_power6") @@ -568,7 +568,7 @@ (define_bypass 4 "power6-vecsimple" "power6-vecstore" ) (define_insn_reservation "power6-veccmp" 1 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "power6")) "FPU_power6") diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md index 9c6326dd26b..91ebbf97f9d 100644 --- a/gcc/config/rs6000/power7.md +++ b/gcc/config/rs6000/power7.md @@ -292,7 +292,7 @@ ; VS Unit (includes FP/VSX/VMX/DFP) (define_insn_reservation "power7-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul,dfp") (eq_attr "cpu" "power7")) "DU_power7,VSU_power7") @@ -324,7 +324,7 @@ "DU_power7,VSU_power7") (define_insn_reservation "power7-vecsimple" 2 - (and (eq_attr "type" "vecsimple,veccmp") + (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") (eq_attr "cpu" "power7")) "DU_power7,vsu1_power7") diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md index 6b6f0ffb8de..4bb323ff435 100644 --- a/gcc/config/rs6000/power8.md +++ b/gcc/config/rs6000/power8.md @@ -317,7 +317,7 @@ ; VS Unit (includes FP/VSX/VMX/DFP/Crypto) (define_insn_reservation "power8-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul,dfp") (eq_attr "cpu" "power8")) "DU_any_power8,VSU_power8") @@ -350,7 +350,8 @@ "DU_any_power8,VSU_power8") (define_insn_reservation "power8-vecsimple" 2 - (and (eq_attr "type" "vecperm,vecsimple,veccmp") + (and (eq_attr "type" "vecperm,vecsimple,veclogical,vecmove,veccmp, + veccmpfx") (eq_attr "cpu" "power8")) "DU_any_power8,VSU_power8") diff --git a/gcc/config/rs6000/power9.md b/gcc/config/rs6000/power9.md new file mode 100644 index 00000000000..015b5ba58b4 --- /dev/null +++ b/gcc/config/rs6000/power9.md @@ -0,0 +1,477 @@ +;; Scheduling description for IBM POWER9 processor. +;; Copyright (C) 2016 Free Software Foundation, Inc. +;; +;; Contributed by Pat Haugen (pthaugen@us.ibm.com). + +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_automaton "power9dsp,power9lsu,power9vsu,power9misc") + +(define_cpu_unit "lsu0_power9,lsu1_power9,lsu2_power9,lsu3_power9" "power9lsu") +(define_cpu_unit "vsu0_power9,vsu1_power9,vsu2_power9,vsu3_power9" "power9vsu") +; Two vector permute units, part of vsu +(define_cpu_unit "prm0_power9,prm1_power9" "power9vsu") +; Two fixed point divide units, not pipelined +(define_cpu_unit "fx_div0_power9,fx_div1_power9" "power9misc") +(define_cpu_unit "bru_power9,cryptu_power9,dfu_power9" "power9misc") + +(define_cpu_unit "x0_power9,x1_power9,xa0_power9,xa1_power9, + x2_power9,x3_power9,xb0_power9,xb1_power9, + br0_power9,br1_power9" "power9dsp") + + +; Dispatch port reservations +; +; Power9 can dispatch a maximum of 6 iops per cycle with the following +; general restrictions (other restrictions also apply): +; 1) At most 2 iops per execution slice +; 2) At most 2 iops to the branch unit +; Note that insn position in a dispatch group of 6 insns does not infer which +; execution slice the insn is routed to. The units are used to infer the +; conflicts that exist (i.e. an 'even' requirement will preclude dispatch +; with 2 insns with 'superslice' requirement). + +; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but +; are listed as separate units to allow those insns that preclude its use to +; still be scheduled two to a superslice while reserving the 3rd slot. The +; same applies for xb0/xb1. +(define_reservation "DU_xa_power9" "xa0_power9+xa1_power9") +(define_reservation "DU_xb_power9" "xb0_power9+xb1_power9") + +; Any execution slice dispatch +(define_reservation "DU_any_power9" + "x0_power9|x1_power9|DU_xa_power9|x2_power9|x3_power9| + DU_xb_power9") + +; Even slice, actually takes even/odd slots +(define_reservation "DU_even_power9" "x0_power9+x1_power9|x2_power9+x3_power9") + +; Slice plus 3rd slot +(define_reservation "DU_slice_3_power9" + "x0_power9+xa0_power9|x1_power9+xa1_power9| + x2_power9+xb0_power9|x3_power9+xb1_power9") + +; Superslice +(define_reservation "DU_super_power9" + "x0_power9+x1_power9|x2_power9+x3_power9") + +; 2-way cracked +(define_reservation "DU_C2_power9" "x0_power9+x1_power9| + x1_power9+DU_xa_power9| + x1_power9+x2_power9| + DU_xa_power9+x2_power9| + x2_power9+x3_power9| + x3_power9+DU_xb_power9") + +; 2-way cracked plus 3rd slot +(define_reservation "DU_C2_3_power9" "x0_power9+x1_power9+xa0_power9| + x1_power9+x2_power9+xa0_power9| + x1_power9+x2_power9+xb0_power9| + x2_power9+x3_power9+xb0_power9") + +; 3-way cracked (consumes whole decode/dispatch cycle) +(define_reservation "DU_C3_power9" + "x0_power9+x1_power9+xa0_power9+xa1_power9+x2_power9+ + x3_power9+xb0_power9+xb1_power9+br0_power9+br1_power9") + +; Branch ports +(define_reservation "DU_branch_power9" "br0_power9|br1_power9") + + +; Execution unit reservations +(define_reservation "LSU_power9" + "lsu0_power9|lsu1_power9|lsu2_power9|lsu3_power9") + +(define_reservation "LSU_pair_power9" + "lsu0_power9+lsu1_power9|lsu1_power9+lsu2_power9| + lsu2_power9+lsu3_power9|lsu3_power9+lsu0_power9") + +(define_reservation "VSU_power9" + "vsu0_power9|vsu1_power9|vsu2_power9|vsu3_power9") + +(define_reservation "VSU_super_power9" + "vsu0_power9+vsu1_power9|vsu2_power9+vsu3_power9") + +(define_reservation "VSU_PRM_power9" "prm0_power9|prm1_power9") + + +; LS Unit +(define_insn_reservation "power9-load" 4 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "no") + (eq_attr "update" "no") + (eq_attr "cpu" "power9")) + "DU_any_power9,LSU_power9") + +(define_insn_reservation "power9-load-update" 4 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "no") + (eq_attr "update" "yes") + (eq_attr "cpu" "power9")) + "DU_C2_power9,LSU_power9+VSU_power9") + +(define_insn_reservation "power9-load-ext" 6 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "yes") + (eq_attr "update" "no") + (eq_attr "cpu" "power9")) + "DU_C2_power9,LSU_power9") + +(define_insn_reservation "power9-load-ext-update" 6 + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "yes") + (eq_attr "update" "yes") + (eq_attr "cpu" "power9")) + "DU_C3_power9,LSU_power9+VSU_power9") + +(define_insn_reservation "power9-fpload-double" 4 + (and (eq_attr "type" "fpload") + (eq_attr "update" "no") + (eq_attr "size" "64") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,LSU_power9") + +(define_insn_reservation "power9-fpload-update-double" 4 + (and (eq_attr "type" "fpload") + (eq_attr "update" "yes") + (eq_attr "size" "64") + (eq_attr "cpu" "power9")) + "DU_C2_3_power9,LSU_power9+VSU_power9") + +; SFmode loads are cracked and have additional 2 cycles over DFmode +(define_insn_reservation "power9-fpload-single" 6 + (and (eq_attr "type" "fpload") + (eq_attr "update" "no") + (eq_attr "size" "32") + (eq_attr "cpu" "power9")) + "DU_C2_3_power9,LSU_power9") + +(define_insn_reservation "power9-fpload-update-single" 6 + (and (eq_attr "type" "fpload") + (eq_attr "update" "yes") + (eq_attr "size" "32") + (eq_attr "cpu" "power9")) + "DU_C3_power9,LSU_power9+VSU_power9") + +(define_insn_reservation "power9-vecload" 5 + (and (eq_attr "type" "vecload") + (eq_attr "cpu" "power9")) + "DU_any_power9,LSU_pair_power9") + +; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store +(define_insn_reservation "power9-store" 0 + (and (eq_attr "type" "store") + (eq_attr "update" "no") + (eq_attr "indexed" "no") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,LSU_power9") + +(define_insn_reservation "power9-store-indexed" 0 + (and (eq_attr "type" "store") + (eq_attr "update" "no") + (eq_attr "indexed" "yes") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,LSU_power9") + +; Update forms have 2 cycle latency for updated addr reg +(define_insn_reservation "power9-store-update" 2 + (and (eq_attr "type" "store") + (eq_attr "update" "yes") + (eq_attr "indexed" "no") + (eq_attr "cpu" "power9")) + "DU_C2_3_power9,LSU_power9+VSU_power9") + +; Update forms have 2 cycle latency for updated addr reg +(define_insn_reservation "power9-store-update-indexed" 2 + (and (eq_attr "type" "store") + (eq_attr "update" "yes") + (eq_attr "indexed" "yes") + (eq_attr "cpu" "power9")) + "DU_C2_3_power9,LSU_power9+VSU_power9") + +(define_insn_reservation "power9-fpstore" 0 + (and (eq_attr "type" "fpstore") + (eq_attr "update" "no") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,LSU_power9") + +; Update forms have 2 cycle latency for updated addr reg +(define_insn_reservation "power9-fpstore-update" 2 + (and (eq_attr "type" "fpstore") + (eq_attr "update" "yes") + (eq_attr "cpu" "power9")) + "DU_C2_3_power9,LSU_power9+VSU_power9") + +(define_insn_reservation "power9-vecstore" 0 + (and (eq_attr "type" "vecstore") + (eq_attr "cpu" "power9")) + "DU_super_power9,LSU_pair_power9") + +(define_insn_reservation "power9-larx" 4 + (and (eq_attr "type" "load_l") + (eq_attr "cpu" "power9")) + "DU_any_power9,LSU_power9") + +(define_insn_reservation "power9-stcx" 2 + (and (eq_attr "type" "store_c") + (eq_attr "cpu" "power9")) + "DU_C2_3_power9,LSU_power9+VSU_power9") + +(define_insn_reservation "power9-sync" 4 + (and (eq_attr "type" "sync,isync") + (eq_attr "cpu" "power9")) + "DU_any_power9,LSU_power9") + + +; VSU Execution Unit + +; Fixed point ops + +; Most ALU insns are simple 2 cycle, including record form +(define_insn_reservation "power9-alu" 2 + (and (ior (eq_attr "type" "add,cmp,exts,integer,logical,isel") + (and (eq_attr "type" "insert,shift") + (eq_attr "dot" "no"))) + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + +; Record form rotate/shift are cracked +(define_insn_reservation "power9-cracked-alu" 2 + (and (eq_attr "type" "insert,shift") + (eq_attr "dot" "yes") + (eq_attr "cpu" "power9")) + "DU_C2_power9,VSU_power9") +; 4 cycle CR latency +(define_bypass 4 "power9-cracked-alu" + "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch") + +(define_insn_reservation "power9-alu2" 3 + (and (eq_attr "type" "cntlz,popcnt,trap") + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + +; Treat 'two' and 'three' types as 2 or 3 way cracked +(define_insn_reservation "power9-two" 4 + (and (eq_attr "type" "two") + (eq_attr "cpu" "power9")) + "DU_C2_power9,VSU_power9") + +(define_insn_reservation "power9-three" 6 + (and (eq_attr "type" "three") + (eq_attr "cpu" "power9")) + "DU_C3_power9,VSU_power9") + +(define_insn_reservation "power9-mul" 4 + (and (eq_attr "type" "mul") + (eq_attr "dot" "no") + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + +(define_insn_reservation "power9-mul-compare" 4 + (and (eq_attr "type" "mul") + (eq_attr "dot" "yes") + (eq_attr "cpu" "power9")) + "DU_C2_power9,VSU_power9") +; 6 cycle CR latency +(define_bypass 6 "power9-mul-compare" + "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch") + +; Fixed point divides reserve the divide units for a minimum of 8 cycles +(define_insn_reservation "power9-idiv" 16 + (and (eq_attr "type" "div") + (eq_attr "size" "32") + (eq_attr "cpu" "power9")) + "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8") + +(define_insn_reservation "power9-ldiv" 24 + (and (eq_attr "type" "div") + (eq_attr "size" "64") + (eq_attr "cpu" "power9")) + "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8") + +(define_insn_reservation "power9-crlogical" 2 + (and (eq_attr "type" "cr_logical,delayed_cr") + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + +(define_insn_reservation "power9-mfcrf" 2 + (and (eq_attr "type" "mfcrf") + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + +(define_insn_reservation "power9-mfcr" 6 + (and (eq_attr "type" "mfcr") + (eq_attr "cpu" "power9")) + "DU_C3_power9,VSU_power9") + +; Should differentiate between 1 cr field and > 1 since target of > 1 cr +; is cracked +(define_insn_reservation "power9-mtcr" 2 + (and (eq_attr "type" "mtcr") + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + +; Move to LR/CTR are executed in VSU +(define_insn_reservation "power9-mtjmpr" 5 + (and (eq_attr "type" "mtjmpr") + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + +; Floating point/Vector ops +(define_insn_reservation "power9-fpsimple" 2 + (and (eq_attr "type" "fpsimple") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +(define_insn_reservation "power9-fp" 7 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +(define_insn_reservation "power9-fpcompare" 3 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other +; divide insns, but for the most part do not block pipelined ops. +(define_insn_reservation "power9-sdiv" 22 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +(define_insn_reservation "power9-ddiv" 33 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +(define_insn_reservation "power9-sqrt" 26 + (and (eq_attr "type" "ssqrt") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +(define_insn_reservation "power9-dsqrt" 36 + (and (eq_attr "type" "dsqrt") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +(define_insn_reservation "power9-vec-2cyc" 2 + (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_super_power9") + +(define_insn_reservation "power9-veccmp" 3 + (and (eq_attr "type" "veccmp") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_super_power9") + +(define_insn_reservation "power9-vecsimple" 3 + (and (eq_attr "type" "vecsimple") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_super_power9") + +(define_insn_reservation "power9-vecnormal" 7 + (and (eq_attr "type" "vecfloat,vecdouble") + (eq_attr "size" "!128") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_super_power9") + +; Quad-precision FP ops, execute in DFU +(define_insn_reservation "power9-qp" 12 + (and (eq_attr "type" "vecfloat,vecdouble") + (eq_attr "size" "128") + (eq_attr "cpu" "power9")) + "DU_super_power9,dfu_power9") + +(define_insn_reservation "power9-vecperm" 3 + (and (eq_attr "type" "vecperm") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_PRM_power9") + +(define_insn_reservation "power9-veccomplex" 7 + (and (eq_attr "type" "veccomplex") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_super_power9") + +(define_insn_reservation "power9-vecfdiv" 28 + (and (eq_attr "type" "vecfdiv") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_super_power9") + +(define_insn_reservation "power9-vecdiv" 32 + (and (eq_attr "type" "vecdiv") + (eq_attr "size" "!128") + (eq_attr "cpu" "power9")) + "DU_super_power9,VSU_super_power9") + +(define_insn_reservation "power9-qpdiv" 56 + (and (eq_attr "type" "vecdiv") + (eq_attr "size" "128") + (eq_attr "cpu" "power9")) + "DU_super_power9,dfu_power9") + +(define_insn_reservation "power9-mffgpr" 2 + (and (eq_attr "type" "mffgpr") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + +(define_insn_reservation "power9-mftgpr" 2 + (and (eq_attr "type" "mftgpr") + (eq_attr "cpu" "power9")) + "DU_slice_3_power9,VSU_power9") + + +; Branch Unit +; Move from LR/CTR are executed in BRU but consume a writeback port from an +; execution slice. +(define_insn_reservation "power9-mfjmpr" 6 + (and (eq_attr "type" "mfjmpr") + (eq_attr "cpu" "power9")) + "DU_branch_power9,bru_power9+VSU_power9") + +; Branch is 2 cycles +(define_insn_reservation "power9-branch" 2 + (and (eq_attr "type" "jmpreg,branch") + (eq_attr "cpu" "power9")) + "DU_branch_power9,bru_power9") + + +; Crypto Unit +(define_insn_reservation "power9-crypto" 6 + (and (eq_attr "type" "crypto") + (eq_attr "cpu" "power9")) + "DU_super_power9,cryptu_power9") + + +; HTM Unit +(define_insn_reservation "power9-htm" 4 + (and (eq_attr "type" "htm") + (eq_attr "cpu" "power9")) + "DU_C2_power9,LSU_power9") + +(define_insn_reservation "power9-htm-simple" 2 + (and (eq_attr "type" "htmsimple") + (eq_attr "cpu" "power9")) + "DU_any_power9,VSU_power9") + + +; DFP Unit +(define_insn_reservation "power9-dfp" 12 + (and (eq_attr "type" "dfp") + (eq_attr "cpu" "power9")) + "DU_even_power9,dfu_power9") + diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index a279874d20f..41694a51f1c 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -572,6 +572,38 @@ } }) +;; Return 1 if the operand is a CONST_VECTOR or VEC_DUPLICATE of a constant +;; that can loaded with a XXSPLTIB instruction and then a VUPKHSB, VECSB2W or +;; VECSB2D instruction. + +(define_predicate "xxspltib_constant_split" + (match_code "const_vector,vec_duplicate,const_int") +{ + int value = 256; + int num_insns = -1; + + if (!xxspltib_constant_p (op, mode, &num_insns, &value)) + return false; + + return num_insns > 1; +}) + + +;; Return 1 if the operand is a CONST_VECTOR that can loaded directly with a +;; XXSPLTIB instruction. + +(define_predicate "xxspltib_constant_nosplit" + (match_code "const_vector,vec_duplicate,const_int") +{ + int value = 256; + int num_insns = -1; + + if (!xxspltib_constant_p (op, mode, &num_insns, &value)) + return false; + + return num_insns == 1; +}) + ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a ;; vector register without using memory. (define_predicate "easy_vector_constant" @@ -590,7 +622,14 @@ if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) { - if (zero_constant (op, mode)) + int value = 256; + int num_insns = -1; + + if (zero_constant (op, mode) || all_ones_constant (op, mode)) + return true; + + if (TARGET_P9_VECTOR + && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; return easy_altivec_constant (op, mode); @@ -709,7 +748,7 @@ if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128) return false; - return quad_address_p (XEXP (op, 0), mode, true); + return quad_address_p (XEXP (op, 0), mode, false); }) ;; Return 1 if the operand is suitable for load/store to vector registers with @@ -1036,6 +1075,10 @@ mode = V2DFmode; else if (mode == DImode) mode = V2DImode; + else if (mode == SImode && TARGET_P9_VECTOR) + mode = V4SImode; + else if (mode == SFmode && TARGET_P9_VECTOR) + mode = V4SFmode; else gcc_unreachable (); return memory_address_addr_space_p (mode, XEXP (op, 0), diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index e0dac7ccee7..a33faa6e5bc 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -645,10 +645,18 @@ /* Miscellaneous builtins for instructions added in ISA 3.0. These instructions don't require either the DFP or VSX options, just the basic ISA 3.0 enablement since they operate on general purpose registers. */ +#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_SPECIAL), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO, /* MASK */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -660,69 +668,92 @@ #define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO \ + RS6000_BTM_P9_MISC \ | RS6000_BTM_64BIT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_ ## ICODE) /* ICODE */ -/* Miscellaneous builtins for instructions added in ISA 3.0. These - instructions don't require either the DFP or VSX options, just the basic - ISA 3.0 enablement since they operate on general purpose registers. */ -#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ +/* Miscellaneous builtins for decimal floating point instructions + added in ISA 3.0. These instructions don't require the VSX + options, just the basic ISA 3.0 enablement since they operate on + general purpose registers. */ +#define BU_P9_DFP_MISC_0(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO, /* MASK */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_ ## ICODE) /* ICODE */ -/* 128-bit long double floating point builtins. */ -#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - (RS6000_BTM_HARD_FLOAT /* MASK */ \ - | RS6000_BTM_LDBL128), \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - - -/* Miscellaneous builtins for instructions added in ISA 3.0. These - instructions don't require either the DFP or VSX options, just the basic - ISA 3.0 enablement since they operate on general purpose registers. */ -#define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \ +#define BU_P9_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO, /* MASK */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ + | RS6000_BTC_SPECIAL), \ CODE_FOR_ ## ICODE) /* ICODE */ -/* Miscellaneous builtins for instructions added in ISA 3.0. These - instructions don't require either the DFP or VSX options, just the basic - ISA 3.0 enablement since they operate on general purpose registers, - and they require 64-bit addressing. */ -#define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ +#define BU_P9_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO \ - | RS6000_BTM_64BIT, /* MASK */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_ ## ICODE) /* ICODE */ -/* Miscellaneous builtins for instructions added in ISA 3.0. These - instructions don't require either the DFP or VSX options, just the basic - ISA 3.0 enablement since they operate on general purpose registers. */ -#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ +/* Decimal floating point overloaded functions added in ISA 3.0 */ +#define BU_P9_DFP_OVERLOAD_1(ENUM, NAME) \ + RS6000_BUILTIN_1 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ + "__builtin_dfp_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P9_DFP_OVERLOAD_2(ENUM, NAME) \ + RS6000_BUILTIN_2 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ + "__builtin_dfp_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_nothing) /* ICODE */ + +#define BU_P9_DFP_OVERLOAD_3(ENUM, NAME) \ + RS6000_BUILTIN_3 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ + "__builtin_dfp_" NAME, /* NAME */ \ + RS6000_BTM_P9_MISC, /* MASK */ \ + (RS6000_BTC_OVERLOADED /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_nothing) /* ICODE */ + +/* 128-bit long double floating point builtins. */ +#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_MODULO, /* MASK */ \ + (RS6000_BTM_HARD_FLOAT /* MASK */ \ + | RS6000_BTM_LDBL128), \ (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ + | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +/* IEEE 128-bit floating-point builtins. */ +#define BU_FLOAT128_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_FLOAT128, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_FLOAT128_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_FLOAT128, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + /* ISA 3.0 (power9) vector convenience macros. */ /* For the instructions that are encoded as altivec instructions use __builtin_altivec_ as the builtin name. */ @@ -1748,6 +1779,25 @@ BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm") BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq") BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm") +/* ISA 3.0 vector overloaded 2-argument functions. */ +BU_P9V_AV_2 (VSLV, "vslv", CONST, vslv) +BU_P9V_AV_2 (VSRV, "vsrv", CONST, vsrv) + +/* ISA 3.0 vector overloaded 2-argument functions. */ +BU_P9V_OVERLOAD_2 (VSLV, "vslv") +BU_P9V_OVERLOAD_2 (VSRV, "vsrv") + +/* 2 argument vector functions added in ISA 3.0 (power9). */ +BU_P9V_AV_2 (VADUB, "vadub", CONST, vaduv16qi3) +BU_P9V_AV_2 (VADUH, "vaduh", CONST, vaduv8hi3) +BU_P9V_AV_2 (VADUW, "vaduw", CONST, vaduv4si3) + +/* ISA 3.0 vector overloaded 2 argument functions. */ +BU_P9V_OVERLOAD_2 (VADU, "vadu") +BU_P9V_OVERLOAD_2 (VADUB, "vadub") +BU_P9V_OVERLOAD_2 (VADUH, "vaduh") +BU_P9V_OVERLOAD_2 (VADUW, "vaduw") + /* 2 argument extended divide functions added in ISA 2.06. */ BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) @@ -1809,6 +1859,36 @@ BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) +/* 2 argument DFP (Decimal Floating Point) functions added in ISA 3.0. */ +BU_P9_DFP_MISC_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd", CONST, dfptstsfi_lt_dd) +BU_P9_DFP_MISC_2 (TSTSFI_LT_TD, "dtstsfi_lt_td", CONST, dfptstsfi_lt_td) + +BU_P9_DFP_MISC_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd", CONST, dfptstsfi_eq_dd) +BU_P9_DFP_MISC_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td", CONST, dfptstsfi_eq_td) + +BU_P9_DFP_MISC_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd", CONST, dfptstsfi_gt_dd) +BU_P9_DFP_MISC_2 (TSTSFI_GT_TD, "dtstsfi_gt_td", CONST, dfptstsfi_gt_td) + +BU_P9_DFP_MISC_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd", CONST, dfptstsfi_unordered_dd) +BU_P9_DFP_MISC_2 (TSTSFI_OV_TD, "dtstsfi_ov_td", CONST, dfptstsfi_unordered_td) + +/* 2 argument overloaded DFP functions added in ISA 3.0. */ +BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT, "dtstsfi_lt") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_TD, "dtstsfi_lt_td") + +BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ, "dtstsfi_eq") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td") + +BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT, "dtstsfi_gt") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_TD, "dtstsfi_gt_td") + +BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV, "dtstsfi_ov") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd") +BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_TD, "dtstsfi_ov_td") + /* 1 argument vector functions added in ISA 3.0 (power9). */ BU_P9V_AV_1 (VCTZB, "vctzb", CONST, ctzv16qi2) BU_P9V_AV_1 (VCTZH, "vctzh", CONST, ctzv8hi2) @@ -1829,6 +1909,11 @@ BU_P9V_OVERLOAD_1 (VPRTYBD, "vprtybd") BU_P9V_OVERLOAD_1 (VPRTYBQ, "vprtybq") BU_P9V_OVERLOAD_1 (VPRTYBW, "vprtybw") +/* 1 argument IEEE 128-bit floating-point functions. */ +BU_FLOAT128_1 (FABSQ, "fabsq", CONST, abskf2) + +/* 2 argument IEEE 128-bit floating-point functions. */ +BU_FLOAT128_2 (COPYSIGNQ, "copysignq", CONST, copysignkf3) /* 1 argument crypto functions. */ BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) @@ -2206,6 +2291,18 @@ BU_SPECIAL_X (RS6000_BUILTIN_CPU_IS, "__builtin_cpu_is", BU_SPECIAL_X (RS6000_BUILTIN_CPU_SUPPORTS, "__builtin_cpu_supports", RS6000_BTM_ALWAYS, RS6000_BTC_MISC) +BU_SPECIAL_X (RS6000_BUILTIN_NANQ, "__builtin_nanq", + RS6000_BTM_FLOAT128, RS6000_BTC_CONST) + +BU_SPECIAL_X (RS6000_BUILTIN_NANSQ, "__builtin_nansq", + RS6000_BTM_FLOAT128, RS6000_BTC_CONST) + +BU_SPECIAL_X (RS6000_BUILTIN_INFQ, "__builtin_infq", + RS6000_BTM_FLOAT128, RS6000_BTC_CONST) + +BU_SPECIAL_X (RS6000_BUILTIN_HUGE_VALQ, "__builtin_huge_valq", + RS6000_BTM_FLOAT128, RS6000_BTC_CONST) + /* Darwin CfString builtin. */ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, RS6000_BTC_MISC) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 5b4ccf1f047..9eb6d545c5c 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -4215,6 +4215,46 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + + { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, + { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD, + RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, + { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, @@ -4252,6 +4292,28 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + + { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + + { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, + RS6000_BTI_unsigned_V8HI, 0 }, + + { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, @@ -4493,6 +4555,13 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, RS6000_BTI_unsigned_V16QI, 0, 0, 0 }, + { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + /* Crypto builtins. */ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 27239f1d371..7d97f7f84eb 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -60,16 +60,26 @@ | OPTION_MASK_UPPER_REGS_SF) /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add - P9_MINMAX until the hardware that supports it is available. Do not add - P9_DFORM_VECTOR until LRA is the default register allocator. */ + P9_MINMAX until the hardware that supports it is available. Do not add + FLOAT128_HW here until we are ready to make -mfloat128 on by default. */ #define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \ - | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_ISEL \ | OPTION_MASK_MODULO \ | OPTION_MASK_P9_FUSION \ | OPTION_MASK_P9_DFORM_SCALAR \ + | OPTION_MASK_P9_DFORM_VECTOR \ + | OPTION_MASK_P9_MISC \ | OPTION_MASK_P9_VECTOR) +/* Support for the IEEE 128-bit floating point hardware requires a lot of the + VSX instructions that are part of ISA 3.0. */ +#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \ + | OPTION_MASK_P8_VECTOR \ + | OPTION_MASK_P9_VECTOR \ + | OPTION_MASK_DIRECT_MOVE \ + | OPTION_MASK_UPPER_REGS_DF \ + | OPTION_MASK_UPPER_REGS_SF) + #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) /* Deal with ports that do not have -mstrict-align. */ @@ -107,6 +117,7 @@ | OPTION_MASK_P9_DFORM_VECTOR \ | OPTION_MASK_P9_FUSION \ | OPTION_MASK_P9_MINMAX \ + | OPTION_MASK_P9_MISC \ | OPTION_MASK_P9_VECTOR \ | OPTION_MASK_POPCNTB \ | OPTION_MASK_POPCNTD \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index f75624f70d8..0a47075d6bf 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -31,6 +31,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, #endif /* TREE_CODE */ extern bool easy_altivec_constant (rtx, machine_mode); +extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); @@ -134,6 +135,7 @@ extern bool rs6000_emit_set_const (rtx, rtx); extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx); extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx); extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx); +extern void rs6000_split_signbit (rtx, rtx); extern void rs6000_expand_atomic_compare_and_swap (rtx op[]); extern void rs6000_expand_atomic_exchange (rtx op[]); extern void rs6000_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index e954a78577e..9d048cc4074 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1104,16 +1104,16 @@ struct processor_costs power9_cost = { COSTS_N_INSNS (3), /* mulsi_const */ COSTS_N_INSNS (3), /* mulsi_const9 */ COSTS_N_INSNS (3), /* muldi */ - COSTS_N_INSNS (19), /* divsi */ - COSTS_N_INSNS (35), /* divdi */ + COSTS_N_INSNS (8), /* divsi */ + COSTS_N_INSNS (12), /* divdi */ COSTS_N_INSNS (3), /* fp */ COSTS_N_INSNS (3), /* dmul */ - COSTS_N_INSNS (14), /* sdiv */ - COSTS_N_INSNS (17), /* ddiv */ + COSTS_N_INSNS (13), /* sdiv */ + COSTS_N_INSNS (18), /* ddiv */ 128, /* cache line size */ 32, /* l1 cache */ - 256, /* l2 cache */ - 12, /* prefetch streams */ + 512, /* l2 cache */ + 8, /* prefetch streams */ COSTS_N_INSNS (3), /* SF->DF convert */ }; @@ -1328,6 +1328,7 @@ static bool rs6000_secondary_reload_move (enum rs6000_reg_type, bool); rtl_opt_pass *make_pass_analyze_swaps (gcc::context*); static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused)); +static tree rs6000_fold_builtin (tree, int, tree *, bool); /* Hash table stuff for keeping track of TOC entries. */ @@ -1602,6 +1603,9 @@ static const struct attribute_spec rs6000_attribute_table[] = #undef TARGET_BUILTIN_DECL #define TARGET_BUILTIN_DECL rs6000_builtin_decl +#undef TARGET_FOLD_BUILTIN +#define TARGET_FOLD_BUILTIN rs6000_fold_builtin + #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin @@ -1882,7 +1886,7 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode) 128-bit floating point that can go in vector registers, which has VSX memory addressing. */ if (FP_REGNO_P (regno)) - reg_size = (VECTOR_MEM_VSX_P (mode) + reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD); @@ -1914,6 +1918,9 @@ rs6000_hard_regno_mode_ok (int regno, machine_mode mode) { int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1; + if (COMPLEX_MODE_P (mode)) + mode = GET_MODE_INNER (mode); + /* PTImode can only go in GPRs. Quad word memory operations require even/odd register combinations, and use PTImode where we need to deal with quad word memory operations. Don't allow quad words in the argument or frame @@ -2716,8 +2723,17 @@ rs6000_setup_reg_addr_masks (void) for (m = 0; m < NUM_MACHINE_MODES; ++m) { - machine_mode m2 = (machine_mode)m; - unsigned short msize = GET_MODE_SIZE (m2); + machine_mode m2 = (machine_mode) m; + bool complex_p = false; + size_t msize; + + if (COMPLEX_MODE_P (m2)) + { + complex_p = true; + m2 = GET_MODE_INNER (m2); + } + + msize = GET_MODE_SIZE (m2); /* SDmode is special in that we want to access it only via REG+REG addressing on power7 and above, since we want to use the LFIWZX and @@ -2739,7 +2755,7 @@ rs6000_setup_reg_addr_masks (void) /* Indicate if the mode takes more than 1 physical register. If it takes a single register, indicate it can do REG+REG addressing. */ - if (nregs > 1 || m == BLKmode) + if (nregs > 1 || m == BLKmode || complex_p) addr_mask |= RELOAD_REG_MULTIPLE; else addr_mask |= RELOAD_REG_INDEXED; @@ -2755,7 +2771,7 @@ rs6000_setup_reg_addr_masks (void) && msize <= 8 && !VECTOR_MODE_P (m2) && !FLOAT128_VECTOR_P (m2) - && !COMPLEX_MODE_P (m2) + && !complex_p && (m2 != DFmode || !TARGET_UPPER_REGS_DF) && (m2 != SFmode || !TARGET_UPPER_REGS_SF) && !(TARGET_E500_DOUBLE && msize == 8)) @@ -3653,13 +3669,15 @@ rs6000_builtin_mask_calculate (void) | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0) + | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0) | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0) | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0) - | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)); + | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0) + | ((TARGET_FLOAT128) ? RS6000_BTM_FLOAT128 : 0)); } /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered @@ -3818,22 +3836,7 @@ rs6000_option_override_internal (bool global_init_p) if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; else if (have_cpu) - { - /* Until power9 tuning is available, use power8 tuning if -mcpu=power9. */ - if (processor_target_table[cpu_index].processor != PROCESSOR_POWER9) - rs6000_tune_index = tune_index = cpu_index; - else - { - size_t i; - tune_index = -1; - for (i = 0; i < ARRAY_SIZE (processor_target_table); i++) - if (processor_target_table[i].processor == PROCESSOR_POWER8) - { - rs6000_tune_index = tune_index = i; - break; - } - } - } + rs6000_tune_index = tune_index = cpu_index; else { size_t i; @@ -4223,14 +4226,19 @@ rs6000_option_override_internal (bool global_init_p) && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION)) rs6000_isa_flags |= OPTION_MASK_TOC_FUSION; + /* ISA 3.0 vector instructions include ISA 2.07. */ + if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR) + { + if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) + error ("-mpower9-vector requires -mpower8-vector"); + rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR; + } + /* -mpower9-dform turns on both -mpower9-dform-scalar and - -mpower9-dform-vector. There are currently problems if - -mpower9-dform-vector instructions are enabled when we use the RELOAD - register allocator. */ + -mpower9-dform-vector. */ if (TARGET_P9_DFORM_BOTH > 0) { - if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) - && TARGET_LRA) + if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR)) rs6000_isa_flags |= OPTION_MASK_P9_DFORM_VECTOR; if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_SCALAR)) @@ -4268,19 +4276,10 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR; } - /* ISA 3.0 vector instructions include ISA 2.07. */ - if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR) - { - if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) - error ("-mpower9-vector requires -mpower8-vector"); - rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR; - } - - /* There have been bugs with both -mvsx-timode and -mpower9-dform-vector that - don't show up with -mlra, but do show up with -mno-lra. Given -mlra will - become the default once PR 69847 is fixed, turn off the options with - problems by default if -mno-lra was used, and warn if the user explicitly - asked for the option. + /* There have been bugs with -mvsx-timode that don't show up with -mlra, + but do show up with -mno-lra. Given -mlra will become the default once + PR 69847 is fixed, turn off the options with problems by default if + -mno-lra was used, and warn if the user explicitly asked for the option. Enable -mpower9-dform-vector by default if LRA and other power9 options. Enable -mvsx-timode by default if LRA and VSX. */ @@ -4294,15 +4293,6 @@ rs6000_option_override_internal (bool global_init_p) else rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE; } - - if (TARGET_P9_DFORM_VECTOR) - { - if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) != 0) - warning (0, "-mpower9-dform-vector might need -mlra"); - - else - rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_VECTOR; - } } else @@ -4310,11 +4300,6 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_VSX && !TARGET_VSX_TIMODE && (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0) rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE; - - if (TARGET_VSX && TARGET_P9_VECTOR && !TARGET_P9_DFORM_VECTOR - && TARGET_P9_DFORM_SCALAR && TARGET_P9_DFORM_BOTH < 0 - && (rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) == 0) - rs6000_isa_flags |= OPTION_MASK_P9_DFORM_VECTOR; } /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07 @@ -4366,13 +4351,21 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128 | OPTION_MASK_FLOAT128_HW); } + /* If we have -mfloat128 and full ISA 3.0 support, enable -mfloat128-hardware + by default. */ + if (TARGET_FLOAT128 && !TARGET_FLOAT128_HW + && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE + && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW)) + { + rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW; + if ((rs6000_isa_flags & OPTION_MASK_FLOAT128) != 0) + rs6000_isa_flags_explicit |= OPTION_MASK_FLOAT128_HW; + } + /* IEEE 128-bit floating point hardware instructions imply enabling __float128. */ if (TARGET_FLOAT128_HW - && (rs6000_isa_flags & (OPTION_MASK_P9_VECTOR - | OPTION_MASK_DIRECT_MOVE - | OPTION_MASK_UPPER_REGS_DF - | OPTION_MASK_UPPER_REGS_SF)) == 0) + && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE) { if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0) error ("-mfloat128-hardware requires full ISA 3.0 support"); @@ -4380,10 +4373,6 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW; } - else if (TARGET_P9_VECTOR && !TARGET_FLOAT128_HW - && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) == 0) - rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW; - if (TARGET_FLOAT128_HW && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128) == 0) rs6000_isa_flags |= OPTION_MASK_FLOAT128; @@ -4593,8 +4582,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER7 - || rs6000_cpu == PROCESSOR_POWER8 - || rs6000_cpu == PROCESSOR_POWER9); + || rs6000_cpu == PROCESSOR_POWER8); rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 @@ -6233,6 +6221,128 @@ gen_easy_altivec_constant (rtx op) gcc_unreachable (); } +/* Return true if OP is of the given MODE and can be synthesized with ISA 3.0 + instructions (xxspltib, vupkhsb/vextsb2w/vextb2d). + + Return the number of instructions needed (1 or 2) into the address pointed + via NUM_INSNS_PTR. + + If NOSPLIT_P, only return true for constants that only generate the XXSPLTIB + instruction and can go in any VSX register. If !NOSPLIT_P, only return true + for constants that generate XXSPLTIB and need a sign extend operation, which + restricts us to the Altivec registers. + + Allow either (vec_const [...]) or (vec_duplicate <const>). If OP is a valid + XXSPLTIB constant, return the constant being set via the CONST_PTR + pointer. */ + +bool +xxspltib_constant_p (rtx op, + machine_mode mode, + int *num_insns_ptr, + int *constant_ptr) +{ + size_t nunits = GET_MODE_NUNITS (mode); + size_t i; + HOST_WIDE_INT value; + rtx element; + + /* Set the returned values to out of bound values. */ + *num_insns_ptr = -1; + *constant_ptr = 256; + + if (!TARGET_P9_VECTOR) + return false; + + if (mode == VOIDmode) + mode = GET_MODE (op); + + else if (mode != GET_MODE (op)) + return false; + + /* Handle (vec_duplicate <constant>). */ + if (GET_CODE (op) == VEC_DUPLICATE) + { + if (mode != V16QImode && mode != V8HImode && mode != V4SImode + && mode != V2DImode) + return false; + + element = XEXP (op, 0); + if (!CONST_INT_P (element)) + return false; + + value = INTVAL (element); + if (!IN_RANGE (value, -128, 127)) + return false; + } + + /* Handle (const_vector [...]). */ + else if (GET_CODE (op) == CONST_VECTOR) + { + if (mode != V16QImode && mode != V8HImode && mode != V4SImode + && mode != V2DImode) + return false; + + element = CONST_VECTOR_ELT (op, 0); + if (!CONST_INT_P (element)) + return false; + + value = INTVAL (element); + if (!IN_RANGE (value, -128, 127)) + return false; + + for (i = 1; i < nunits; i++) + { + element = CONST_VECTOR_ELT (op, i); + if (!CONST_INT_P (element)) + return false; + + if (value != INTVAL (element)) + return false; + } + + /* See if we could generate vspltisw/vspltish directly instead of + xxspltib + sign extend. Special case 0/-1 to allow getting + any VSX register instead of an Altivec register. */ + if (!IN_RANGE (value, -1, 0) && EASY_VECTOR_15 (value) + && (mode == V4SImode || mode == V8HImode)) + return false; + } + + /* Handle integer constants being loaded into the upper part of the VSX + register as a scalar. If the value isn't 0/-1, only allow it if + the mode can go in Altivec registers. */ + else if (CONST_INT_P (op)) + { + if (!SCALAR_INT_MODE_P (mode)) + return false; + + value = INTVAL (op); + if (!IN_RANGE (value, -128, 127)) + return false; + + if (!IN_RANGE (value, -1, 0) + && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0) + return false; + } + + else + return false; + + /* Return # of instructions and the constant byte for XXSPLTIB. */ + if (mode == V16QImode) + *num_insns_ptr = 1; + + else if (IN_RANGE (value, -1, 0)) + *num_insns_ptr = 1; + + else + *num_insns_ptr = 2; + + *constant_ptr = (int) value; + return true; +} + const char * output_vec_const_move (rtx *operands) { @@ -6246,23 +6356,60 @@ output_vec_const_move (rtx *operands) if (TARGET_VSX) { + bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest)); + int xxspltib_value = 256; + int num_insns = -1; + if (zero_constant (vec, mode)) - return "xxlxor %x0,%x0,%x0"; + { + if (TARGET_P9_VECTOR) + return "xxspltib %x0,0"; + + else if (dest_vmx_p) + return "vspltisw %0,0"; + + else + return "xxlxor %x0,%x0,%x0"; + } + + if (all_ones_constant (vec, mode)) + { + if (TARGET_P9_VECTOR) + return "xxspltib %x0,255"; - if (TARGET_P8_VECTOR && vec == CONSTM1_RTX (mode)) - return "xxlorc %x0,%x0,%x0"; + else if (dest_vmx_p) + return "vspltisw %0,-1"; - if ((mode == V2DImode || mode == V1TImode) - && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1 - && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1) - return (TARGET_P8_VECTOR) ? "xxlorc %x0,%x0,%x0" : "vspltisw %0,-1"; + else if (TARGET_P8_VECTOR) + return "xxlorc %x0,%x0,%x0"; + + else + gcc_unreachable (); + } + + if (TARGET_P9_VECTOR + && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) + { + if (num_insns == 1) + { + operands[2] = GEN_INT (xxspltib_value & 0xff); + return "xxspltib %x0,%2"; + } + + return "#"; + } } if (TARGET_ALTIVEC) { rtx splat_vec; + + gcc_assert (ALTIVEC_REGNO_P (REGNO (dest))); if (zero_constant (vec, mode)) - return "vxor %0,%0,%0"; + return "vspltisw %0,0"; + + if (all_ones_constant (vec, mode)) + return "vspltisw %0,-1"; /* Do we need to construct a value using VSLDOI? */ shift = vspltis_shifted (vec); @@ -6535,6 +6682,15 @@ rs6000_expand_vector_init (rtx target, rtx vals) return; } + /* Word values on ISA 3.0 can use mtvsrws, lxvwsx, or vspltisw. V4SF is + complicated since scalars are stored as doubles in the registers. */ + if (TARGET_P9_VECTOR && mode == V4SImode && all_same + && VECTOR_MEM_VSX_P (mode)) + { + emit_insn (gen_vsx_splat_v4si (target, XVECEXP (vals, 0, 0))); + return; + } + /* With single precision floating point on VSX, know that internally single precision is actually represented as a double, and either make 2 V2DF vectors, and convert these vectors to single precision, or do one @@ -6543,14 +6699,23 @@ rs6000_expand_vector_init (rtx target, rtx vals) { if (all_same) { - rtx freg = gen_reg_rtx (V4SFmode); - rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0)); - rtx cvt = ((TARGET_XSCVDPSPN) - ? gen_vsx_xscvdpspn_scalar (freg, sreg) - : gen_vsx_xscvdpsp_scalar (freg, sreg)); + rtx op0 = XVECEXP (vals, 0, 0); - emit_insn (cvt); - emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg, const0_rtx)); + if (TARGET_P9_VECTOR) + emit_insn (gen_vsx_splat_v4sf (target, op0)); + + else + { + rtx freg = gen_reg_rtx (V4SFmode); + rtx sreg = force_reg (SFmode, op0); + rtx cvt = (TARGET_XSCVDPSPN + ? gen_vsx_xscvdpspn_scalar (freg, sreg) + : gen_vsx_xscvdpsp_scalar (freg, sreg)); + + emit_insn (cvt); + emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg, + const0_rtx)); + } } else { @@ -7025,34 +7190,24 @@ quad_address_offset_p (HOST_WIDE_INT offset) 3.0 LXV/STXV instruction. */ bool -quad_address_p (rtx addr, machine_mode mode, bool gpr_p) +quad_address_p (rtx addr, machine_mode mode, bool strict) { rtx op0, op1; if (GET_MODE_SIZE (mode) != 16) return false; - if (gpr_p) - { - if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) - return false; - - /* LQ/STQ can handle indirect addresses. */ - if (base_reg_operand (addr, Pmode)) - return true; - } + if (legitimate_indirect_address_p (addr, strict)) + return true; - else - { - if (!mode_supports_vsx_dform_quad (mode)) - return false; - } + if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode)) + return false; if (GET_CODE (addr) != PLUS) return false; op0 = XEXP (addr, 0); - if (!base_reg_operand (op0, Pmode)) + if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict)) return false; op1 = XEXP (addr, 1); @@ -7421,8 +7576,7 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x, if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) return false; if (mode_supports_vsx_dform_quad (mode)) - return (virtual_stack_registers_memory_p (x) - || quad_address_p (x, mode, false)); + return quad_address_p (x, mode, strict); if (!reg_offset_addressing_ok_p (mode)) return virtual_stack_registers_memory_p (x); if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress)) @@ -8325,13 +8479,18 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, int ind_levels ATTRIBUTE_UNUSED, int *win) { bool reg_offset_p = reg_offset_addressing_ok_p (mode); + bool quad_offset_p = mode_supports_vsx_dform_quad (mode); - /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a - DFmode/DImode MEM. */ + /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a + DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */ if (reg_offset_p && opnum == 1 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode) - || (mode == DImode && recog_data.operand_mode[0] == V2DImode))) + || (mode == DImode && recog_data.operand_mode[0] == V2DImode) + || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode + && TARGET_P9_VECTOR) + || (mode == SImode && recog_data.operand_mode[0] == V4SImode + && TARGET_P9_VECTOR))) reg_offset_p = false; /* We must recognize output that we have already generated ourselves. */ @@ -8390,6 +8549,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, if (TARGET_CMODEL != CMODEL_SMALL && reg_offset_p + && !quad_offset_p && small_toc_ref (x, VOIDmode)) { rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x)); @@ -8407,22 +8567,24 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, } if (GET_CODE (x) == PLUS - && GET_CODE (XEXP (x, 0)) == REG + && REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1) - && GET_CODE (XEXP (x, 1)) == CONST_INT + && CONST_INT_P (XEXP (x, 1)) && reg_offset_p && !SPE_VECTOR_MODE (mode) && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD) - && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))) + && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))) { HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; HOST_WIDE_INT high = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; - /* Check for 32-bit overflow. */ - if (high + low != val) + /* Check for 32-bit overflow or quad addresses with one of the + four least significant bits set. */ + if (high + low != val + || (quad_offset_p && (low & 0xf))) { *win = 0; return x; @@ -8450,6 +8612,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, if (GET_CODE (x) == SYMBOL_REF && reg_offset_p + && !quad_offset_p && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)) && !SPE_VECTOR_MODE (mode) #if TARGET_MACHO @@ -8534,6 +8697,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode, if (TARGET_TOC && reg_offset_p + && !quad_offset_p && GET_CODE (x) == SYMBOL_REF && use_toc_relative_ref (x, mode)) { @@ -8622,15 +8786,14 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) && mode_supports_pre_incdec_p (mode) && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) return 1; - if (virtual_stack_registers_memory_p (x)) - return 1; - /* Handle restricted vector d-form offsets in ISA 3.0. */ if (quad_offset_p) { - if (quad_address_p (x, mode, false)) + if (quad_address_p (x, mode, reg_ok_strict)) return 1; } + else if (virtual_stack_registers_memory_p (x)) + return 1; else if (reg_offset_p) { @@ -10275,6 +10438,35 @@ rs6000_must_pass_in_stack (machine_mode mode, const_tree type) return must_pass_in_stack_var_size_or_pad (mode, type); } +static inline bool +is_complex_IBM_long_double (machine_mode mode) +{ + return mode == ICmode || (!TARGET_IEEEQUAD && mode == TCmode); +} + +/* Whether ABI_V4 passes MODE args to a function in floating point + registers. */ + +static bool +abi_v4_pass_in_fpr (machine_mode mode) +{ + if (!TARGET_FPRS || !TARGET_HARD_FLOAT) + return false; + if (TARGET_SINGLE_FLOAT && mode == SFmode) + return true; + if (TARGET_DOUBLE_FLOAT && mode == DFmode) + return true; + /* ABI_V4 passes complex IBM long double in 8 gprs. + Stupid, but we can't change the ABI now. */ + if (is_complex_IBM_long_double (mode)) + return false; + if (FLOAT128_2REG_P (mode)) + return true; + if (DECIMAL_FLOAT_MODE_P (mode)) + return true; + return false; +} + /* If defined, a C expression which determines whether, and in which direction, to pad out an argument with extra space. The value should be of type `enum direction': either `upward' to pad above @@ -10359,6 +10551,7 @@ rs6000_function_arg_boundary (machine_mode mode, const_tree type) && (GET_MODE_SIZE (mode) == 8 || (TARGET_HARD_FLOAT && TARGET_FPRS + && !is_complex_IBM_long_double (mode) && FLOAT128_2REG_P (mode)))) return 64; else if (FLOAT128_VECTOR_P (mode)) @@ -10750,11 +10943,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode, } else if (DEFAULT_ABI == ABI_V4) { - if (TARGET_HARD_FLOAT && TARGET_FPRS - && ((TARGET_SINGLE_FLOAT && mode == SFmode) - || (TARGET_DOUBLE_FLOAT && mode == DFmode) - || FLOAT128_2REG_P (mode) - || DECIMAL_FLOAT_MODE_P (mode))) + if (abi_v4_pass_in_fpr (mode)) { /* _Decimal128 must use an even/odd register pair. This assumes that the register number is odd when fregno is odd. */ @@ -11411,11 +11600,7 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode, else if (abi == ABI_V4) { - if (TARGET_HARD_FLOAT && TARGET_FPRS - && ((TARGET_SINGLE_FLOAT && mode == SFmode) - || (TARGET_DOUBLE_FLOAT && mode == DFmode) - || FLOAT128_2REG_P (mode) - || DECIMAL_FLOAT_MODE_P (mode))) + if (abi_v4_pass_in_fpr (mode)) { /* _Decimal128 must use an even/odd register pair. This assumes that the register number is odd when fregno is odd. */ @@ -12345,19 +12530,15 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, rsize = (size + 3) / 4; align = 1; - if (TARGET_HARD_FLOAT && TARGET_FPRS - && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode) - || (TARGET_DOUBLE_FLOAT - && (TYPE_MODE (type) == DFmode - || FLOAT128_2REG_P (TYPE_MODE (type)) - || DECIMAL_FLOAT_MODE_P (TYPE_MODE (type)))))) + machine_mode mode = TYPE_MODE (type); + if (abi_v4_pass_in_fpr (mode)) { /* FP args go in FP registers, if present. */ reg = fpr; n_reg = (size + 7) / 8; sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4; sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4); - if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode) + if (mode != SFmode && mode != SDmode) align = 8; } else @@ -12377,7 +12558,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, addr = create_tmp_var (ptr_type_node, "addr"); /* AltiVec vectors never go in registers when -mabi=altivec. */ - if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) + if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) align = 16; else { @@ -12398,7 +12579,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, } /* _Decimal128 is passed in even/odd fpr pairs; the stored reg number is 0 for f1, so we want to make it odd. */ - else if (reg == fpr && TYPE_MODE (type) == TDmode) + else if (reg == fpr && mode == TDmode) { t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg), build_int_cst (TREE_TYPE (reg), 1)); @@ -12425,7 +12606,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, FP register for 32-bit binaries. */ if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPRS - && TYPE_MODE (type) == SDmode) + && mode == SDmode) t = fold_build_pointer_plus_hwi (t, size); gimplify_assign (addr, t, pre_p); @@ -13153,6 +13334,24 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) return const0_rtx; } } + else if (icode == CODE_FOR_dfptstsfi_eq_dd + || icode == CODE_FOR_dfptstsfi_lt_dd + || icode == CODE_FOR_dfptstsfi_gt_dd + || icode == CODE_FOR_dfptstsfi_unordered_dd + || icode == CODE_FOR_dfptstsfi_eq_td + || icode == CODE_FOR_dfptstsfi_lt_td + || icode == CODE_FOR_dfptstsfi_gt_td + || icode == CODE_FOR_dfptstsfi_unordered_td) + { + /* Only allow 6-bit unsigned literals. */ + STRIP_NOPS (arg0); + if (TREE_CODE (arg0) != INTEGER_CST + || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63)) + { + error ("argument 1 must be a 6-bit unsigned literal"); + return CONST0_RTX (tmode); + } + } if (target == 0 || GET_MODE (target) != tmode @@ -15183,17 +15382,69 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode) error ("Builtin function %s requires the -mpower8-vector option", name); else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0) error ("Builtin function %s requires the -mpower9-vector option", name); + else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) + == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) + error ("Builtin function %s requires the -mpower9-misc and" + " -m64 options", name); + else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC) + error ("Builtin function %s requires the -mpower9-misc option", name); else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128)) == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128)) error ("Builtin function %s requires the -mhard-float and" " -mlong-double-128 options", name); else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0) error ("Builtin function %s requires the -mhard-float option", name); + else if ((fnmask & RS6000_BTM_FLOAT128) != 0) + error ("Builtin function %s requires the -mfloat128 option", name); else error ("Builtin function %s is not supported with the current options", name); } +/* Target hook for early folding of built-ins, shamelessly stolen + from ia64.c. */ + +static tree +rs6000_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, + tree *args, bool ignore ATTRIBUTE_UNUSED) +{ + if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD) + { + enum rs6000_builtins fn_code + = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); + switch (fn_code) + { + case RS6000_BUILTIN_NANQ: + case RS6000_BUILTIN_NANSQ: + { + tree type = TREE_TYPE (TREE_TYPE (fndecl)); + const char *str = c_getstr (*args); + int quiet = fn_code == RS6000_BUILTIN_NANQ; + REAL_VALUE_TYPE real; + + if (str && real_nan (&real, str, quiet, TYPE_MODE (type))) + return build_real (type, real); + return NULL_TREE; + } + case RS6000_BUILTIN_INFQ: + case RS6000_BUILTIN_HUGE_VALQ: + { + tree type = TREE_TYPE (TREE_TYPE (fndecl)); + REAL_VALUE_TYPE inf; + real_inf (&inf); + return build_real (type, inf); + } + default: + break; + } + } +#ifdef SUBTARGET_FOLD_BUILTIN + return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore); +#else + return NULL_TREE; +#endif +} + /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). @@ -15448,6 +15699,10 @@ rs6000_init_builtins (void) opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4); + const_str_type_node + = build_pointer_type (build_qualified_type (char_type_node, + TYPE_QUAL_CONST)); + /* We use V1TI mode as a special container to hold __int128_t items that must live in VSX registers. */ if (intTI_type_node) @@ -15510,6 +15765,12 @@ rs6000_init_builtins (void) lang_hooks.types.register_builtin_type (ibm128_float_type_node, "__ibm128"); } + else + { + /* All types must be nonzero, or self-test barfs during bootstrap. */ + ieee128_float_type_node = long_double_type_node; + ibm128_float_type_node = long_double_type_node; + } /* Initialize the modes for builtin_function_type, mapping a machine mode to tree type node. */ @@ -15651,6 +15912,15 @@ rs6000_init_builtins (void) if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT) rs6000_common_init_builtins (); + ftype = build_function_type_list (ieee128_float_type_node, + const_str_type_node, NULL_TREE); + def_builtin ("__builtin_nanq", ftype, RS6000_BUILTIN_NANQ); + def_builtin ("__builtin_nansq", ftype, RS6000_BUILTIN_NANSQ); + + ftype = build_function_type_list (ieee128_float_type_node, NULL_TREE); + def_builtin ("__builtin_infq", ftype, RS6000_BUILTIN_INFQ); + def_builtin ("__builtin_huge_valq", ftype, RS6000_BUILTIN_HUGE_VALQ); + ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode, RS6000_BUILTIN_RECIP, "__builtin_recipdiv"); def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP); @@ -18494,25 +18764,33 @@ rs6000_secondary_reload_memory (rtx addr, addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & ~RELOAD_REG_AND_M16); - else + /* If the register allocator hasn't made up its mind yet on the register + class to use, settle on defaults to use. */ + else if (rclass == NO_REGS) { - if (TARGET_DEBUG_ADDR) - fprintf (stderr, - "rs6000_secondary_reload_memory: mode = %s, class = %s, " - "class is not GPR, FPR, VMX\n", - GET_MODE_NAME (mode), reg_class_names[rclass]); + addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY] + & ~RELOAD_REG_AND_M16); - return -1; + if ((addr_mask & RELOAD_REG_MULTIPLE) != 0) + addr_mask &= ~(RELOAD_REG_INDEXED + | RELOAD_REG_PRE_INCDEC + | RELOAD_REG_PRE_MODIFY); } + else + addr_mask = 0; + /* If the register isn't valid in this register class, just return now. */ if ((addr_mask & RELOAD_REG_VALID) == 0) { if (TARGET_DEBUG_ADDR) - fprintf (stderr, - "rs6000_secondary_reload_memory: mode = %s, class = %s, " - "not valid in class\n", - GET_MODE_NAME (mode), reg_class_names[rclass]); + { + fprintf (stderr, + "rs6000_secondary_reload_memory: mode = %s, class = %s, " + "not valid in class\n", + GET_MODE_NAME (mode), reg_class_names[rclass]); + debug_rtx (addr); + } return -1; } @@ -18776,7 +19054,8 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, simple move insns are issued. At present, 32-bit integers are not allowed in FPR/VSX registers. Single precision binary floating is not a simple move because we need to convert to the single precision memory layout. - The 4-byte SDmode can be moved. */ + The 4-byte SDmode can be moved. TDmode values are disallowed since they + need special direct move handling, which we do not support yet. */ size = GET_MODE_SIZE (mode); if (TARGET_DIRECT_MOVE && ((mode == SDmode) || (TARGET_POWERPC64 && size == 8)) @@ -18784,7 +19063,7 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE))) return true; - else if (TARGET_DIRECT_MOVE_128 && size == 16 + else if (TARGET_DIRECT_MOVE_128 && size == 16 && mode != TDmode && ((to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE) || (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE))) return true; @@ -19173,6 +19452,9 @@ rs6000_secondary_reload (bool in_p, fprintf (stderr, ", reload func = %s, extra cost = %d", insn_data[sri->icode].name, sri->extra_cost); + else if (sri->extra_cost > 0) + fprintf (stderr, ", extra cost = %d", sri->extra_cost); + fputs ("\n", stderr); debug_rtx (x); } @@ -19583,6 +19865,16 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) machine_mode mode = GET_MODE (x); bool is_constant = CONSTANT_P (x); + /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred + reload class for it. */ + if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS) + && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0) + return NO_REGS; + + if ((rclass == FLOAT_REGS || rclass == VSX_REGS) + && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0) + return NO_REGS; + /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow the reloading of address expressions using PLUS into floating point registers. */ @@ -19633,6 +19925,25 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) return NO_REGS; } + /* If we haven't picked a register class, and the type is a vector or + floating point type, prefer to use the VSX, FPR, or Altivec register + classes. */ + if (rclass == NO_REGS) + { + if (TARGET_VSX && VECTOR_MEM_VSX_OR_P8_VECTOR_P (mode)) + return VSX_REGS; + + if (TARGET_ALTIVEC && VECTOR_MEM_ALTIVEC_P (mode)) + return ALTIVEC_REGS; + + if (DECIMAL_FLOAT_MODE_P (mode)) + return TARGET_DFP ? FLOAT_REGS : NO_REGS; + + if (TARGET_FPRS && TARGET_HARD_FLOAT && FLOAT_MODE_P (mode) + && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0) + return FLOAT_REGS; + } + if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS) return GENERAL_REGS; @@ -20022,7 +20333,7 @@ rs6000_output_move_128bit (rtx operands[]) else if (TARGET_VSX && dest_vsx_p) { if (mode_supports_vsx_dform_quad (mode) - && quad_address_p (XEXP (src, 0), mode, false)) + && quad_address_p (XEXP (src, 0), mode, true)) return "lxv %x0,%1"; else if (TARGET_P9_VECTOR) @@ -20060,7 +20371,7 @@ rs6000_output_move_128bit (rtx operands[]) else if (TARGET_VSX && src_vsx_p) { if (mode_supports_vsx_dform_quad (mode) - && quad_address_p (XEXP (dest, 0), mode, false)) + && quad_address_p (XEXP (dest, 0), mode, true)) return "stxv %x1,%0"; else if (TARGET_P9_VECTOR) @@ -20090,10 +20401,8 @@ rs6000_output_move_128bit (rtx operands[]) if (dest_gpr_p) return "#"; - else if (TARGET_VSX && dest_vsx_p && zero_constant (src, mode)) - return "xxlxor %x0,%x0,%x0"; - - else if (TARGET_ALTIVEC && dest_vmx_p) + else if ((dest_vmx_p && TARGET_ALTIVEC) + || (dest_vsx_p && TARGET_VSX)) return output_vec_const_move (operands); } @@ -22695,6 +23004,48 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) emit_move_insn (dest, target); } +/* Split a signbit operation on 64-bit machines with direct move. Also allow + for the value to come from memory or if it is already loaded into a GPR. */ + +void +rs6000_split_signbit (rtx dest, rtx src) +{ + machine_mode d_mode = GET_MODE (dest); + machine_mode s_mode = GET_MODE (src); + rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest); + rtx shift_reg = dest_di; + + gcc_assert (REG_P (dest)); + gcc_assert (REG_P (src) || MEM_P (src)); + gcc_assert (s_mode == KFmode || s_mode == TFmode); + + if (MEM_P (src)) + { + rtx mem = (WORDS_BIG_ENDIAN + ? adjust_address (src, DImode, 0) + : adjust_address (src, DImode, 8)); + emit_insn (gen_rtx_SET (dest_di, mem)); + } + + else + { + unsigned int r = REGNO (src); + + /* If this is a VSX register, generate the special mfvsrd instruction + to get it in a GPR. Until we support SF and DF modes, that will + always be true. */ + gcc_assert (VSX_REGNO_P (r)); + + if (s_mode == KFmode) + emit_insn (gen_signbitkf2_dm2 (dest_di, src)); + else + emit_insn (gen_signbittf2_dm2 (dest_di, src)); + } + + emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63))); + return; +} + /* A subroutine of the atomic operation splitters. Jump to LABEL if COND is true. Mark the jump as unlikely to be taken. */ @@ -29465,13 +29816,20 @@ output_function_profiler (FILE *file, int labelno) /* The following variable value is the last issued insn. */ -static rtx last_scheduled_insn; +static rtx_insn *last_scheduled_insn; /* The following variable helps to balance issuing of load and store instructions */ static int load_store_pendulum; +/* The following variable helps pair divide insns during scheduling. */ +static int divide_cnt; +/* The following variable helps pair and alternate vector and vector load + insns during scheduling. */ +static int vec_load_pendulum; + + /* Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle. Branches have their own dispatch slot which does not count against the @@ -29546,7 +29904,7 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost) some cycles later. */ /* Separate a load from a narrower, dependent store. */ - if (rs6000_sched_groups + if ((rs6000_sched_groups || rs6000_cpu_attr == CPU_POWER9) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM @@ -29772,7 +30130,9 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost) switch (attr_type) { case TYPE_FP: - if (get_attr_type (dep_insn) == TYPE_FP) + case TYPE_FPSIMPLE: + if (get_attr_type (dep_insn) == TYPE_FP + || get_attr_type (dep_insn) == TYPE_FPSIMPLE) return 1; break; case TYPE_FPLOAD: @@ -29784,6 +30144,8 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost) break; } } + /* Fall through, no cost for output dependency. */ + case REG_DEP_ANTI: /* Anti dependency; DEP_INSN reads a register that INSN writes some cycles later. */ @@ -30156,8 +30518,9 @@ rs6000_issue_rate (void) case CPU_POWER7: return 5; case CPU_POWER8: - case CPU_POWER9: return 7; + case CPU_POWER9: + return 6; default: return 1; } @@ -30315,6 +30678,28 @@ is_store_insn (rtx insn, rtx *str_mem) return is_store_insn1 (PATTERN (insn), str_mem); } +/* Return whether TYPE is a Power9 pairable vector instruction type. */ + +static bool +is_power9_pairable_vec_type (enum attr_type type) +{ + switch (type) + { + case TYPE_VECSIMPLE: + case TYPE_VECCOMPLEX: + case TYPE_VECDIV: + case TYPE_VECCMP: + case TYPE_VECPERM: + case TYPE_VECFLOAT: + case TYPE_VECFDIV: + case TYPE_VECDOUBLE: + return true; + default: + break; + } + return false; +} + /* Returns whether the dependence between INSN and NEXT is considered costly by the given target. */ @@ -30391,6 +30776,229 @@ get_next_active_insn (rtx_insn *insn, rtx_insn *tail) return insn; } +/* Do Power9 specific sched_reorder2 reordering of ready list. */ + +static int +power9_sched_reorder2 (rtx_insn **ready, int lastpos) +{ + int pos; + int i; + rtx_insn *tmp; + enum attr_type type; + + type = get_attr_type (last_scheduled_insn); + + /* Try to issue fixed point divides back-to-back in pairs so they will be + routed to separate execution units and execute in parallel. */ + if (type == TYPE_DIV && divide_cnt == 0) + { + /* First divide has been scheduled. */ + divide_cnt = 1; + + /* Scan the ready list looking for another divide, if found move it + to the end of the list so it is chosen next. */ + pos = lastpos; + while (pos >= 0) + { + if (recog_memoized (ready[pos]) >= 0 + && get_attr_type (ready[pos]) == TYPE_DIV) + { + tmp = ready[pos]; + for (i = pos; i < lastpos; i++) + ready[i] = ready[i + 1]; + ready[lastpos] = tmp; + break; + } + pos--; + } + } + else + { + /* Last insn was the 2nd divide or not a divide, reset the counter. */ + divide_cnt = 0; + + /* Power9 can execute 2 vector operations and 2 vector loads in a single + cycle. So try to pair up and alternate groups of vector and vector + load instructions. + + To aid this formation, a counter is maintained to keep track of + vec/vecload insns issued. The value of vec_load_pendulum maintains + the current state with the following values: + + 0 : Initial state, no vec/vecload group has been started. + + -1 : 1 vector load has been issued and another has been found on + the ready list and moved to the end. + + -2 : 2 vector loads have been issued and a vector operation has + been found and moved to the end of the ready list. + + -3 : 2 vector loads and a vector insn have been issued and a + vector operation has been found and moved to the end of the + ready list. + + 1 : 1 vector insn has been issued and another has been found and + moved to the end of the ready list. + + 2 : 2 vector insns have been issued and a vector load has been + found and moved to the end of the ready list. + + 3 : 2 vector insns and a vector load have been issued and another + vector load has been found and moved to the end of the ready + list. */ + if (type == TYPE_VECLOAD) + { + /* Issued a vecload. */ + if (vec_load_pendulum == 0) + { + /* We issued a single vecload, look for another and move it to + the end of the ready list so it will be scheduled next. + Set pendulum if found. */ + pos = lastpos; + while (pos >= 0) + { + if (recog_memoized (ready[pos]) >= 0 + && get_attr_type (ready[pos]) == TYPE_VECLOAD) + { + tmp = ready[pos]; + for (i = pos; i < lastpos; i++) + ready[i] = ready[i + 1]; + ready[lastpos] = tmp; + vec_load_pendulum = -1; + return cached_can_issue_more; + } + pos--; + } + } + else if (vec_load_pendulum == -1) + { + /* This is the second vecload we've issued, search the ready + list for a vector operation so we can try to schedule a + pair of those next. If found move to the end of the ready + list so it is scheduled next and set the pendulum. */ + pos = lastpos; + while (pos >= 0) + { + if (recog_memoized (ready[pos]) >= 0 + && is_power9_pairable_vec_type ( + get_attr_type (ready[pos]))) + { + tmp = ready[pos]; + for (i = pos; i < lastpos; i++) + ready[i] = ready[i + 1]; + ready[lastpos] = tmp; + vec_load_pendulum = -2; + return cached_can_issue_more; + } + pos--; + } + } + else if (vec_load_pendulum == 2) + { + /* Two vector ops have been issued and we've just issued a + vecload, look for another vecload and move to end of ready + list if found. */ + pos = lastpos; + while (pos >= 0) + { + if (recog_memoized (ready[pos]) >= 0 + && get_attr_type (ready[pos]) == TYPE_VECLOAD) + { + tmp = ready[pos]; + for (i = pos; i < lastpos; i++) + ready[i] = ready[i + 1]; + ready[lastpos] = tmp; + /* Set pendulum so that next vecload will be seen as + finishing a group, not start of one. */ + vec_load_pendulum = 3; + return cached_can_issue_more; + } + pos--; + } + } + } + else if (is_power9_pairable_vec_type (type)) + { + /* Issued a vector operation. */ + if (vec_load_pendulum == 0) + /* We issued a single vec op, look for another and move it + to the end of the ready list so it will be scheduled next. + Set pendulum if found. */ + { + pos = lastpos; + while (pos >= 0) + { + if (recog_memoized (ready[pos]) >= 0 + && is_power9_pairable_vec_type ( + get_attr_type (ready[pos]))) + { + tmp = ready[pos]; + for (i = pos; i < lastpos; i++) + ready[i] = ready[i + 1]; + ready[lastpos] = tmp; + vec_load_pendulum = 1; + return cached_can_issue_more; + } + pos--; + } + } + else if (vec_load_pendulum == 1) + { + /* This is the second vec op we've issued, search the ready + list for a vecload operation so we can try to schedule a + pair of those next. If found move to the end of the ready + list so it is scheduled next and set the pendulum. */ + pos = lastpos; + while (pos >= 0) + { + if (recog_memoized (ready[pos]) >= 0 + && get_attr_type (ready[pos]) == TYPE_VECLOAD) + { + tmp = ready[pos]; + for (i = pos; i < lastpos; i++) + ready[i] = ready[i + 1]; + ready[lastpos] = tmp; + vec_load_pendulum = 2; + return cached_can_issue_more; + } + pos--; + } + } + else if (vec_load_pendulum == -2) + { + /* Two vecload ops have been issued and we've just issued a + vec op, look for another vec op and move to end of ready + list if found. */ + pos = lastpos; + while (pos >= 0) + { + if (recog_memoized (ready[pos]) >= 0 + && is_power9_pairable_vec_type ( + get_attr_type (ready[pos]))) + { + tmp = ready[pos]; + for (i = pos; i < lastpos; i++) + ready[i] = ready[i + 1]; + ready[lastpos] = tmp; + /* Set pendulum so that next vec op will be seen as + finishing a group, not start of one. */ + vec_load_pendulum = -3; + return cached_can_issue_more; + } + pos--; + } + } + } + + /* We've either finished a vec/vecload group, couldn't find an insn to + continue the current group, or the last insn had nothing to do with + with a group. In any case, reset the pendulum. */ + vec_load_pendulum = 0; + } + + return cached_can_issue_more; +} + /* We are about to begin issuing insns for this clock cycle. */ static int @@ -30622,6 +31230,11 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, } } + /* Do Power9 dependent reordering if necessary. */ + if (rs6000_cpu == PROCESSOR_POWER9 && last_scheduled_insn + && recog_memoized (last_scheduled_insn) >= 0) + return power9_sched_reorder2 (ready, *pn_ready - 1); + return cached_can_issue_more; } @@ -30790,7 +31403,6 @@ insn_must_be_first_in_group (rtx_insn *insn) } break; case PROCESSOR_POWER8: - case PROCESSOR_POWER9: type = get_attr_type (insn); switch (type) @@ -30921,7 +31533,6 @@ insn_must_be_last_in_group (rtx_insn *insn) } break; case PROCESSOR_POWER8: - case PROCESSOR_POWER9: type = get_attr_type (insn); switch (type) @@ -31040,7 +31651,7 @@ force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, /* Do we have a special group ending nop? */ if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7 - || rs6000_cpu_attr == CPU_POWER8 || rs6000_cpu_attr == CPU_POWER9) + || rs6000_cpu_attr == CPU_POWER8) { nop = gen_group_ending_nop (); emit_insn_before (nop, next_insn); @@ -31294,8 +31905,10 @@ rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int max_ready ATTRIBUTE_UNUSED) { - last_scheduled_insn = NULL_RTX; + last_scheduled_insn = NULL; load_store_pendulum = 0; + divide_cnt = 0; + vec_load_pendulum = 0; } /* The following function is called at the end of scheduling BB. @@ -31336,14 +31949,16 @@ rs6000_sched_finish (FILE *dump, int sched_verbose) } } -struct _rs6000_sched_context +struct rs6000_sched_context { short cached_can_issue_more; - rtx last_scheduled_insn; + rtx_insn *last_scheduled_insn; int load_store_pendulum; + int divide_cnt; + int vec_load_pendulum; }; -typedef struct _rs6000_sched_context rs6000_sched_context_def; +typedef struct rs6000_sched_context rs6000_sched_context_def; typedef rs6000_sched_context_def *rs6000_sched_context_t; /* Allocate store for new scheduling context. */ @@ -31363,14 +31978,18 @@ rs6000_init_sched_context (void *_sc, bool clean_p) if (clean_p) { sc->cached_can_issue_more = 0; - sc->last_scheduled_insn = NULL_RTX; + sc->last_scheduled_insn = NULL; sc->load_store_pendulum = 0; + sc->divide_cnt = 0; + sc->vec_load_pendulum = 0; } else { sc->cached_can_issue_more = cached_can_issue_more; sc->last_scheduled_insn = last_scheduled_insn; sc->load_store_pendulum = load_store_pendulum; + sc->divide_cnt = divide_cnt; + sc->vec_load_pendulum = vec_load_pendulum; } } @@ -31385,6 +32004,8 @@ rs6000_set_sched_context (void *_sc) cached_can_issue_more = sc->cached_can_issue_more; last_scheduled_insn = sc->last_scheduled_insn; load_store_pendulum = sc->load_store_pendulum; + divide_cnt = sc->divide_cnt; + vec_load_pendulum = sc->vec_load_pendulum; } /* Free _SC. */ @@ -34579,8 +35200,14 @@ rs6000_complex_function_value (machine_mode mode) machine_mode inner = GET_MODE_INNER (mode); unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode); - if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) + if (TARGET_FLOAT128 + && (mode == KCmode + || (mode == TCmode && TARGET_IEEEQUAD))) + regno = ALTIVEC_ARG_RETURN; + + else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) regno = FP_ARG_RETURN; + else { regno = GP_ARG_RETURN; @@ -35132,6 +35759,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "power9-dform-vector", OPTION_MASK_P9_DFORM_VECTOR, false, true }, { "power9-fusion", OPTION_MASK_P9_FUSION, false, true }, { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true }, + { "power9-misc", OPTION_MASK_P9_MISC, false, true }, { "power9-vector", OPTION_MASK_P9_VECTOR, false, true }, { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, @@ -35187,11 +35815,13 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { "cell", RS6000_BTM_CELL, false, false }, { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, { "power9-vector", RS6000_BTM_P9_VECTOR, false, false }, + { "power9-misc", RS6000_BTM_P9_MISC, false, false }, { "crypto", RS6000_BTM_CRYPTO, false, false }, { "htm", RS6000_BTM_HTM, false, false }, { "hard-dfp", RS6000_BTM_DFP, false, false }, { "hard-float", RS6000_BTM_HARD_FLOAT, false, false }, { "long-double-128", RS6000_BTM_LDBL128, false, false }, + { "float128", RS6000_BTM_FLOAT128, false, false }, }; /* Option variables that we want to support inside attribute((target)) and diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 827b7c9579c..62854783920 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -302,6 +302,28 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define TARGET_P8_VECTOR 0 #endif +/* Define the ISA 3.0 flags as 0 if the target assembler does not support + Power9 instructions. Allow -mpower9-fusion, since it does not add new + instructions. Allow -misel, since it predates ISA 3.0 and does + not require any Power9 features. */ + +#ifndef HAVE_AS_POWER9 +#undef TARGET_FLOAT128_HW +#undef TARGET_MODULO +#undef TARGET_P9_VECTOR +#undef TARGET_P9_MINMAX +#undef TARGET_P9_DFORM_SCALAR +#undef TARGET_P9_DFORM_VECTOR +#undef TARGET_P9_MISC +#define TARGET_FLOAT128_HW 0 +#define TARGET_MODULO 0 +#define TARGET_P9_VECTOR 0 +#define TARGET_P9_MINMAX 0 +#define TARGET_P9_DFORM_SCALAR 0 +#define TARGET_P9_DFORM_VECTOR 0 +#define TARGET_P9_MISC 0 +#endif + /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If not, generate the lwsync code as an integer constant. */ #ifdef HAVE_AS_LWSYNC @@ -418,12 +440,12 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); Similarly IFmode is the IBM long double format even if the default is IEEE 128-bit. */ #define FLOAT128_IEEE_P(MODE) \ - (((MODE) == TFmode && TARGET_IEEEQUAD) \ - || ((MODE) == KFmode)) + ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ + || ((MODE) == KFmode) || ((MODE) == KCmode)) #define FLOAT128_IBM_P(MODE) \ - (((MODE) == TFmode && !TARGET_IEEEQUAD) \ - || ((MODE) == IFmode)) + ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ + || ((MODE) == IFmode) || ((MODE) == ICmode)) /* Helper macros to say whether a 128-bit floating point type can go in a single vector register, or whether it needs paired scalar values. */ @@ -625,6 +647,7 @@ extern int rs6000_vector_align[]; #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR +#define MASK_P9_MISC OPTION_MASK_P9_MISC #define MASK_POPCNTB OPTION_MASK_POPCNTB #define MASK_POPCNTD OPTION_MASK_POPCNTD #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT @@ -1789,7 +1812,9 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) -#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \ +#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ + ? (ALTIVEC_ARG_RETURN \ + + (TARGET_FLOAT128 ? 1 : 0)) \ : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) /* Flags for the call/call_value rtl operations set up by function_arg */ @@ -2678,6 +2703,7 @@ extern int frame_pointer_needed; #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.00 vector. */ +#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector. */ #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ #define RS6000_BTM_SPE MASK_STRING /* E500 */ @@ -2692,11 +2718,14 @@ extern int frame_pointer_needed; #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ +#define RS6000_BTM_FLOAT128 MASK_P9_VECTOR /* IEEE 128-bit float. */ #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ | RS6000_BTM_P8_VECTOR \ | RS6000_BTM_P9_VECTOR \ + | RS6000_BTM_P9_MISC \ + | RS6000_BTM_MODULO \ | RS6000_BTM_CRYPTO \ | RS6000_BTM_FRE \ | RS6000_BTM_FRES \ @@ -2707,7 +2736,8 @@ extern int frame_pointer_needed; | RS6000_BTM_CELL \ | RS6000_BTM_DFP \ | RS6000_BTM_HARD_FLOAT \ - | RS6000_BTM_LDBL128) + | RS6000_BTM_LDBL128 \ + | RS6000_BTM_FLOAT128) /* Define builtin enum index. */ @@ -2811,6 +2841,7 @@ enum rs6000_builtin_type_index RS6000_BTI_void, /* void_type_node */ RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ + RS6000_BTI_const_str, /* pointer to const char * */ RS6000_BTI_MAX }; @@ -2867,6 +2898,7 @@ enum rs6000_builtin_type_index #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) +#define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index cc5ef2e5d8d..ab9202e0b03 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -147,6 +147,8 @@ UNSPEC_ROUND_TO_ODD UNSPEC_IEEE128_MOVE UNSPEC_IEEE128_CONVERT + UNSPEC_SIGNBIT + UNSPEC_DOLOOP ]) ;; @@ -183,12 +185,13 @@ brinc, vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm, vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto, - htm" + veclogical,veccmpfx,vecexts,vecmove, + htm,htmsimple,dfp" (const_string "integer")) ;; What data size does this instruction work on? -;; This is used for insert, mul. -(define_attr "size" "8,16,32,64" (const_string "32")) +;; This is used for insert, mul and others as necessary. +(define_attr "size" "8,16,32,64,128" (const_string "32")) ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)? ;; This is used for add, logical, shift, exts, mul. @@ -298,6 +301,7 @@ (include "power6.md") (include "power7.md") (include "power8.md") +(include "power9.md") (include "cell.md") (include "xfpu.md") (include "a2.md") @@ -506,6 +510,13 @@ (IF "TARGET_FLOAT128") (TF "TARGET_LONG_DOUBLE_128")]) +; Iterator for signbit on 64-bit machines with direct move +(define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)") + (TF "FLOAT128_VECTOR_P (TFmode)")]) + +(define_mode_attr Fsignbit [(KF "wa") + (TF "wa")]) + ; SF/DF suffix for traditional floating instructions (define_mode_attr Ftrad [(SF "s") (DF "")]) @@ -4059,7 +4070,7 @@ if (REGNO (cr) == CR0_REGNO) { - emit_insn (gen_ashdi3_extswsli_dot (dest, src2, shift, cr)); + emit_insn (gen_ashdi3_extswsli_dot2 (dest, src2, shift, cr)); DONE; } @@ -4320,7 +4331,7 @@ "@ fabs %0,%1 xsabsdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_insn "*nabs<mode>2_fpr" @@ -4332,7 +4343,7 @@ "@ fnabs %0,%1 xsnabsdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "neg<mode>2" @@ -4348,7 +4359,7 @@ "@ fneg %0,%1 xsnegdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "add<mode>3" @@ -4509,7 +4520,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "fp,fp,fpload,fp,fp,fpload,fpload")]) + [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")]) (define_expand "truncdfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") @@ -4531,7 +4542,7 @@ ;; when little-endian. (define_expand "signbit<mode>2" [(set (match_dup 2) - (float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" ""))) + (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" ""))) (set (match_dup 3) (subreg:DI (match_dup 2) 0)) (set (match_dup 4) @@ -4539,8 +4550,20 @@ (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 6))] "TARGET_HARD_FLOAT - && (TARGET_FPRS || TARGET_E500_DOUBLE)" + && (TARGET_FPRS || TARGET_E500_DOUBLE) + && (!FLOAT128_IEEE_P (<MODE>mode) + || (TARGET_POWERPC64 && TARGET_DIRECT_MOVE))" { + if (FLOAT128_IEEE_P (<MODE>mode)) + { + if (<MODE>mode == KFmode) + emit_insn (gen_signbitkf2_dm (operands[0], operands[1])); + else if (<MODE>mode == TFmode) + emit_insn (gen_signbittf2_dm (operands[0], operands[1])); + else + gcc_unreachable (); + DONE; + } operands[2] = gen_reg_rtx (DFmode); operands[3] = gen_reg_rtx (DImode); if (TARGET_POWERPC64) @@ -4588,6 +4611,37 @@ operands[5] = CONST0_RTX (<MODE>mode); }) +;; Optimize signbit on 64-bit systems with direct move to avoid doing the store +;; and load. +(define_insn_and_split "signbit<mode>2_dm" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") + (unspec:SI + [(match_operand:SIGNBIT 1 "input_operand" "<Fsignbit>,m,r")] + UNSPEC_SIGNBIT))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rs6000_split_signbit (operands[0], operands[1]); + DONE; +} + [(set_attr "length" "8,8,12") + (set_attr "type" "mftgpr,load,integer")]) + +;; MODES_TIEABLE_P doesn't allow DImode to be tied with the various floating +;; point types, which makes normal SUBREG's problematical. Instead use a +;; special pattern to avoid using a normal movdi. +(define_insn "signbit<mode>2_dm2" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "<Fsignbit>") + (const_int 0)] + UNSPEC_SIGNBIT))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mfvsrd %0,%x1" + [(set_attr "type" "mftgpr")]) + + ;; Use an unspec rather providing an if-then-else in RTL, to prevent the ;; compiler from optimizing -0.0 (define_insn "copysign<mode>3_fcpsgn" @@ -4599,7 +4653,7 @@ "@ fcpsgn %0,%2,%1 xscpsgndp %x0,%x2,%x1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a ;; fsel instruction and some auxiliary computations. Then we just have a @@ -4812,7 +4866,7 @@ (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))] "TARGET_P9_MINMAX" "xxsel %x0,%x1,%x3,%x4" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) ;; Conversions to and from floating-point. @@ -5923,7 +5977,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -5959,7 +6013,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -5997,7 +6051,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6057,7 +6111,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6115,7 +6169,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6171,7 +6225,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6486,7 +6540,7 @@ mt%0 %1 mf%1 %0 nop" - [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*") + [(set_attr "type" "*,load,store,fpsimple,fpsimple,veclogical,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*") (set_attr "length" "4")]) (define_insn "*mov<mode>_softfloat" @@ -6621,7 +6675,8 @@ # # #" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,two,store,load,two") + [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two") + (set_attr "size" "64") (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")]) (define_insn "*mov<mode>_softfloat32" @@ -6666,7 +6721,8 @@ mffgpr %0,%1 mfvsrd %0,%x1 mtvsrd %x0,%1" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr") + [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr") + (set_attr "size" "64") (set_attr "length" "4")]) (define_insn "*mov<mode>_softfloat64" @@ -6877,7 +6933,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_insn "trunc<mode>df2_internal2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") @@ -7110,7 +7166,7 @@ else return \"fneg %0,%1\;fneg %L0,%L1\"; }" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "8")]) (define_expand "abs<mode>2" @@ -7245,7 +7301,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlxor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; IEEE 128-bit absolute value (define_insn_and_split "ieee_128bit_vsx_abs<mode>2" @@ -7274,7 +7330,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlandc %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; IEEE 128-bit negative absolute value (define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2" @@ -7307,7 +7363,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; Float128 conversion functions. These expand to library function calls. ;; We use expand to convert from IBM double double to IEEE 128-bit @@ -7463,7 +7519,7 @@ UNSPEC_P8V_FMRGOW))] "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "fmrgow %0,%1,%2" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "fpsimple")]) (define_insn "p8_mtvsrwz" [(set (match_operand:DF 0 "register_operand" "=d") @@ -7686,7 +7742,8 @@ lfd%U1%X1 %0,%1 fmr %0,%1 #" - [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")]) + [(set_attr "type" "store,load,*,fpstore,fpload,fpsimple,*") + (set_attr "size" "64")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -7740,7 +7797,8 @@ mfvsrd %0,%x1 mtvsrd %x0,%1 xxlxor %x0,%x0,%x0" - [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple") + [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fpsimple,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,veclogical") + (set_attr "size" "64") (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")]) ; Some DImode loads are best done as a load of -1 followed by a mask @@ -8748,7 +8806,8 @@ lfdu %3,%2(%0)" [(set_attr "type" "fpload") (set_attr "update" "yes") - (set_attr "indexed" "yes,no")]) + (set_attr "indexed" "yes,no") + (set_attr "size" "64")]) (define_insn "*movdf_update2" [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") @@ -11883,6 +11942,7 @@ (set (match_dup 0) (plus:P (match_dup 0) (const_int -1))) + (unspec [(const_int 0)] UNSPEC_DOLOOP) (clobber (match_scratch:CC 2 "")) (clobber (match_scratch:P 3 ""))])] "" @@ -11893,6 +11953,7 @@ ;; JUMP_INSNs. ;; For the length attribute to be calculated correctly, the ;; label MUST be operand 0. +;; The UNSPEC is present to prevent combine creating this pattern. (define_insn "*ctr<mode>_internal1" [(set (pc) @@ -11900,9 +11961,10 @@ (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l") (plus:P (match_dup 1) (const_int -1))) + (unspec [(const_int 0)] UNSPEC_DOLOOP) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:P 4 "=X,X,&r,r"))] "" @@ -11924,9 +11986,10 @@ (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l") (plus:P (match_dup 1) (const_int -1))) + (unspec [(const_int 0)] UNSPEC_DOLOOP) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:P 4 "=X,X,&r,r"))] "" @@ -11950,9 +12013,10 @@ (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l") (plus:P (match_dup 1) (const_int -1))) + (unspec [(const_int 0)] UNSPEC_DOLOOP) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:P 4 "=X,X,&r,r"))] "" @@ -11974,9 +12038,10 @@ (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l") (plus:P (match_dup 1) (const_int -1))) + (unspec [(const_int 0)] UNSPEC_DOLOOP) (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) (clobber (match_scratch:P 4 "=X,X,&r,r"))] "" @@ -12003,6 +12068,7 @@ (match_operand 6 "" ""))) (set (match_operand:P 0 "int_reg_operand" "") (plus:P (match_dup 1) (const_int -1))) + (unspec [(const_int 0)] UNSPEC_DOLOOP) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:P 4 ""))] "reload_completed" @@ -12028,6 +12094,7 @@ (match_operand 6 "" ""))) (set (match_operand:P 0 "nonimmediate_operand" "") (plus:P (match_dup 1) (const_int -1))) + (unspec [(const_int 0)] UNSPEC_DOLOOP) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:P 4 ""))] "reload_completed && ! gpc_reg_operand (operands[0], SImode)" @@ -13149,7 +13216,7 @@ operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi); operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo); } - [(set_attr "type" "fp,fp") + [(set_attr "type" "fpsimple,fp") (set_attr "length" "4,8")]) (define_insn "unpack<mode>" @@ -13188,7 +13255,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsaddqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "sub<mode>3" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13197,7 +13265,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xssubqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "mul<mode>3" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13206,7 +13275,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmulqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "div<mode>3" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13215,7 +13285,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsdivqp %0,%1,%2" - [(set_attr "type" "vecdiv")]) + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) (define_insn "sqrt<mode>2" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13223,9 +13294,28 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xssqrtqp %0,%1" - [(set_attr "type" "vecdiv")]) + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) + +(define_expand "copysign<mode>3" + [(use (match_operand:IEEE128 0 "altivec_register_operand")) + (use (match_operand:IEEE128 1 "altivec_register_operand")) + (use (match_operand:IEEE128 2 "altivec_register_operand"))] + "FLOAT128_IEEE_P (<MODE>mode)" +{ + if (TARGET_FLOAT128_HW) + emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1], + operands[2])); + else + { + rtx tmp = gen_reg_rtx (<MODE>mode); + emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1], + operands[2], tmp)); + } + DONE; +}) -(define_insn "copysign<mode>3" +(define_insn "copysign<mode>3_hard" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v") @@ -13233,7 +13323,20 @@ UNSPEC_COPYSIGN))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscpsgnqp %0,%2,%1" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) + +(define_insn "copysign<mode>3_soft" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + (unspec:IEEE128 + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") + (match_operand:IEEE128 3 "altivec_register_operand" "+v")] + UNSPEC_COPYSIGN))] + "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1" + [(set_attr "type" "veccomplex") + (set_attr "length" "8")]) (define_insn "neg<mode>2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13241,7 +13344,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnegqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) (define_insn "abs<mode>2_hw" @@ -13250,7 +13354,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsabsqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) (define_insn "*nabs<mode>2_hw" @@ -13260,7 +13365,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnabsqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove") + (set_attr "size" "128")]) ;; Initially don't worry about doing fusion (define_insn "*fma<mode>4_hw" @@ -13271,7 +13377,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmaddqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*fms<mode>4_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13282,7 +13389,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmsubqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*nfma<mode>4_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13293,7 +13401,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnmaddqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*nfms<mode>4_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13305,7 +13414,8 @@ (match_operand:IEEE128 3 "altivec_register_operand" "0")))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnmsubqp %0,%1,%2" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "extend<SFDF:mode><IEEE128:mode>2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13313,7 +13423,8 @@ (match_operand:SFDF 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)" "xscvdpqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) ;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating ;; point is a simple copy. @@ -13330,7 +13441,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "*,vecsimple") + [(set_attr "type" "*,veclogical") (set_attr "length" "0,4")]) (define_insn_and_split "trunctfkf2" @@ -13346,7 +13457,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "*,vecsimple") + [(set_attr "type" "*,veclogical") (set_attr "length" "0,4")]) (define_insn "trunc<mode>df2_hw" @@ -13355,7 +13466,8 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqpdp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) ;; There is no KFmode -> SFmode instruction. Preserve the accuracy by doing ;; the KFmode -> DFmode conversion using round to odd rather than the normal @@ -13452,7 +13564,8 @@ UNSPEC_IEEE128_CONVERT))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqp<su>wz %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*xscvqp<su>dz_<mode>" [(set (match_operand:V2DI 0 "altivec_register_operand" "=v") @@ -13462,7 +13575,8 @@ UNSPEC_IEEE128_CONVERT))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqp<su>dz %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*xscv<su>dqp_<mode>" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13471,7 +13585,8 @@ UNSPEC_IEEE128_CONVERT)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscv<su>dqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) (define_insn "*ieee128_mfvsrd_64bit" [(set (match_operand:DI 0 "reg_or_indexed_operand" "=wr,Z,wi") @@ -13482,7 +13597,7 @@ mfvsrd %0,%x1 stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "mftgpr,fpstore,vecsimple")]) + [(set_attr "type" "mftgpr,fpstore,veclogical")]) (define_insn "*ieee128_mfvsrd_32bit" @@ -13493,7 +13608,7 @@ "@ stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "fpstore,vecsimple")]) + [(set_attr "type" "fpstore,veclogical")]) (define_insn "*ieee128_mfvsrwz" [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z") @@ -13529,7 +13644,7 @@ mtvsrd %x0,%1 lxsdx %x0,%y1 xxlor %x0,%x1,%x1" - [(set_attr "type" "mffgpr,fpload,vecsimple")]) + [(set_attr "type" "mffgpr,fpload,veclogical")]) (define_insn "*ieee128_mtvsrd_32bit" [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v") @@ -13539,7 +13654,7 @@ "@ lxsdx %x0,%y1 xxlor %x0,%x1,%x1" - [(set_attr "type" "fpload,vecsimple")]) + [(set_attr "type" "fpload,veclogical")]) ;; IEEE 128-bit instructions with round to odd semantics (define_insn "*trunc<mode>df2_odd" @@ -13548,7 +13663,8 @@ UNSPEC_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqpdpo %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) ;; IEEE 128-bit comparisons (define_insn "*cmp<mode>_hw" @@ -13557,7 +13673,8 @@ (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscmpuqp %0,%1,%2" - [(set_attr "type" "fpcompare")]) + [(set_attr "type" "veccmp") + (set_attr "size" "128")]) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 92c5396c47e..611ed01b2a0 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -605,9 +605,13 @@ mpower9-fusion Target Report Mask(P9_FUSION) Var(rs6000_isa_flags) Fuse certain operations together for better performance on power9. +mpower9-misc +Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) +Use/do not use certain scalar instructions added in ISA 3.0. + mpower9-vector Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags) -Use/do not use vector and scalar instructions added in ISA 3.0. +Use/do not use vector instructions added in ISA 3.0. mpower9-dform-scalar Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags) diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md index b730aa82ec4..e33cb785595 100644 --- a/gcc/config/rs6000/rs64.md +++ b/gcc/config/rs6000/rs64.md @@ -111,7 +111,7 @@ "mciu_rs64,fpu_rs64,bpu_rs64") (define_insn_reservation "rs64a-fp" 4 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "rs64a")) "mciu_rs64,fpu_rs64") diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index 0ba0af0666c..f72f729d3a6 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -50,6 +50,7 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \ $(srcdir)/config/rs6000/power6.md \ $(srcdir)/config/rs6000/power7.md \ $(srcdir)/config/rs6000/power8.md \ + $(srcdir)/config/rs6000/power9.md \ $(srcdir)/config/rs6000/cell.md \ $(srcdir)/config/rs6000/xfpu.md \ $(srcdir)/config/rs6000/a2.md \ diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md index 74389534b45..e6658d67bd3 100644 --- a/gcc/config/rs6000/titan.md +++ b/gcc/config/rs6000/titan.md @@ -156,7 +156,7 @@ ;; Make sure the "titan_fp" rule stays last, as it's a catch all for ;; double-precision and unclassified (e.g. fsel) FP-instructions (define_insn_reservation "titan_fp" 10 - (and (eq_attr "type" "fpcompare,fp,dmul") + (and (eq_attr "type" "fpcompare,fp,fpsimple,dmul") (eq_attr "cpu" "titan")) "titan_issue,titan_fp0*2,nothing*8,titan_fpwb") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 57cee7934ba..09cc23229c2 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -55,8 +55,7 @@ (KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)")]) -;; Iterator for memory move. Handle TImode specially to allow -;; it to use gprs as well as vsx registers. +;; Iterator for memory moves. (define_mode_iterator VSX_M [V16QI V8HI V4SI @@ -65,18 +64,8 @@ V2DF V1TI (KF "FLOAT128_VECTOR_P (KFmode)") - (TF "FLOAT128_VECTOR_P (TFmode)")]) - -(define_mode_iterator VSX_M2 [V16QI - V8HI - V4SI - V2DI - V4SF - V2DF - V1TI - (KF "FLOAT128_VECTOR_P (KFmode)") - (TF "FLOAT128_VECTOR_P (TFmode)") - (TI "TARGET_VSX_TIMODE")]) + (TF "FLOAT128_VECTOR_P (TFmode)") + (TI "TARGET_VSX_TIMODE")]) ;; Map into the appropriate load/store name based on the type (define_mode_attr VSm [(V16QI "vw4") @@ -270,6 +259,10 @@ (define_mode_attr VS_64reg [(V2DF "ws") (V2DI "wi")]) +;; Iterators for loading constants with xxspltib +(define_mode_iterator VSINT_84 [V4SI V2DI]) +(define_mode_iterator VSINT_842 [V8HI V4SI V2DI]) + ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT @@ -299,6 +292,7 @@ UNSPEC_VSX_XVCVUXDDP UNSPEC_VSX_XVCVDPSXDS UNSPEC_VSX_XVCVDPUXDS + UNSPEC_VSX_SIGN_EXTEND ]) ;; VSX moves @@ -691,7 +685,7 @@ } } [(set_attr "length" "0,4") - (set_attr "type" "vecsimple")]) + (set_attr "type" "veclogical")]) (define_insn_and_split "*vsx_le_perm_load_<mode>" [(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=<VSa>") @@ -769,92 +763,141 @@ (const_int 64)))] "") -(define_insn "*vsx_mov<mode>" - [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO,<VSr>,<VSr>,?ZwO,?<VSa>,?<VSa>,r,we,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ,v") - (match_operand:VSX_M 1 "input_operand" "<VSr>,ZwO,<VSr>,<VSa>,ZwO,<VSa>,we,b,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] - "VECTOR_MEM_VSX_P (<MODE>mode) - && (register_operand (operands[0], <MODE>mode) - || register_operand (operands[1], <MODE>mode))" +;; Vector constants that can be generated with XXSPLTIB that was added in ISA +;; 3.0. Both (const_vector [..]) and (vec_duplicate ...) forms are recognized. +(define_insn "xxspltib_v16qi" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") + (vec_duplicate:V16QI (match_operand:SI 1 "s8bit_cint_operand" "n")))] + "TARGET_P9_VECTOR" { - return rs6000_output_move_128bit (operands); + operands[2] = GEN_INT (INTVAL (operands[1]) & 0xff); + return "xxspltib %x0,%2"; } - [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,mffgpr,mftgpr,load,store,store,load, *,vecsimple,vecsimple,*, *,vecstore,vecload") - (set_attr "length" "4,4,4,4,4,4,8,4,12,12,12,12,16,4,4,*,16,4,4")]) - -;; Unlike other VSX moves, allow the GPRs even for reloading, since a normal -;; use of TImode is for unions. However for plain data movement, slightly -;; favor the vector loads -(define_insn "*vsx_movti_64bit" - [(set (match_operand:TI 0 "nonimmediate_operand" "=ZwO,wa,wa,wa,r,we,v,v,wZ,wQ,&r,Y,r,r,?r") - (match_operand:TI 1 "input_operand" "wa,ZwO,wa,O,we,b,W,wZ,v,r,wQ,r,Y,r,n"))] - "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode) - && (register_operand (operands[0], TImode) - || register_operand (operands[1], TImode))" + [(set_attr "type" "vecperm")]) + +(define_insn "xxspltib_<mode>_nosplit" + [(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa,wa") + (match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "jwM,wE"))] + "TARGET_P9_VECTOR" { - return rs6000_output_move_128bit (operands); + rtx op1 = operands[1]; + int value = 256; + int num_insns = -1; + + if (!xxspltib_constant_p (op1, <MODE>mode, &num_insns, &value) + || num_insns != 1) + gcc_unreachable (); + + operands[2] = GEN_INT (value & 0xff); + return "xxspltib %x0,%2"; } - [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,mffgpr,mftgpr,vecsimple,vecstore,vecload,store,load,store,load,*,*") - (set_attr "length" "4,4,4,4,8,4,16,4,4,8,8,8,8,8,8")]) - -(define_insn "*vsx_movti_32bit" - [(set (match_operand:TI 0 "nonimmediate_operand" "=ZwO,wa,wa,wa,v,v,wZ,Q,Y,????r,????r,????r,r") - (match_operand:TI 1 "input_operand" "wa,ZwO,wa,O,W,wZ,v,r,r,Q,Y,r,n"))] - "! TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode) - && (register_operand (operands[0], TImode) - || register_operand (operands[1], TImode))" + [(set_attr "type" "vecperm")]) + +(define_insn_and_split "*xxspltib_<mode>_split" + [(set (match_operand:VSINT_842 0 "altivec_register_operand" "=v") + (match_operand:VSINT_842 1 "xxspltib_constant_split" "wS"))] + "TARGET_P9_VECTOR" + "#" + "&& 1" + [(const_int 0)] { - switch (which_alternative) - { - case 0: - return "stxvd2x %x1,%y0"; + int value = 256; + int num_insns = -1; + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = ((can_create_pseudo_p ()) + ? gen_reg_rtx (V16QImode) + : gen_lowpart (V16QImode, op0)); - case 1: - return "lxvd2x %x0,%y1"; + if (!xxspltib_constant_p (op1, <MODE>mode, &num_insns, &value) + || num_insns != 2) + gcc_unreachable (); - case 2: - return "xxlor %x0,%x1,%x1"; + emit_insn (gen_xxspltib_v16qi (tmp, GEN_INT (value))); - case 3: - return "xxlxor %x0,%x0,%x0"; + if (<MODE>mode == V2DImode) + emit_insn (gen_vsx_sign_extend_qi_v2di (op0, tmp)); - case 4: - return output_vec_const_move (operands); + else if (<MODE>mode == V4SImode) + emit_insn (gen_vsx_sign_extend_qi_v4si (op0, tmp)); - case 5: - return "stvx %1,%y0"; + else if (<MODE>mode == V8HImode) + emit_insn (gen_altivec_vupkhsb (op0, tmp)); - case 6: - return "lvx %0,%y1"; + else + gcc_unreachable (); - case 7: - if (TARGET_STRING) - return \"stswi %1,%P0,16\"; + DONE; +} + [(set_attr "type" "vecperm") + (set_attr "length" "8")]) - case 8: - return \"#\"; - case 9: - /* If the address is not used in the output, we can use lsi. Otherwise, - fall through to generating four loads. */ - if (TARGET_STRING - && ! reg_overlap_mentioned_p (operands[0], operands[1])) - return \"lswi %0,%P1,16\"; - /* ... fall through ... */ +;; Prefer using vector registers over GPRs. Prefer using ISA 3.0's XXSPLTISB +;; or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC to set a register to all 0's or +;; all 1's, since the machine does not have to wait for the previous +;; instruction using the register being set (such as a store waiting on a slow +;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move. - case 10: - case 11: - case 12: - return \"#\"; - default: - gcc_unreachable (); - } +;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) +;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW +;; VSX 0/-1 GPR 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) +(define_insn "*vsx_mov<mode>_64bit" + [(set (match_operand:VSX_M 0 "nonimmediate_operand" + "=ZwO, <VSa>, <VSa>, r, we, ?wQ, + ?&r, ??r, ??Y, ??r, wo, v, + ?<VSa>, *r, v, ??r, wZ, v") + + (match_operand:VSX_M 1 "input_operand" + "<VSa>, ZwO, <VSa>, we, r, r, + wQ, Y, r, r, wE, jwM, + ?jwM, jwM, W, W, v, wZ"))] + + "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode) + && (register_operand (operands[0], <MODE>mode) + || register_operand (operands[1], <MODE>mode))" +{ + return rs6000_output_move_128bit (operands); } - [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,store,load,load, *, *") - (set_attr "update" " *, *, *, *, *, *, *, yes, yes, yes, yes, *, *") - (set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16") - (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") - (const_string "always") - (const_string "conditional")))]) + [(set_attr "type" + "vecstore, vecload, vecsimple, mffgpr, mftgpr, load, + store, load, store, *, vecsimple, vecsimple, + vecsimple, *, *, *, vecstore, vecload") + + (set_attr "length" + "4, 4, 4, 8, 4, 8, + 8, 8, 8, 8, 4, 4, + 4, 8, 20, 20, 4, 4")]) + +;; VSX store VSX load VSX move GPR load GPR store GPR move +;; XXSPLTIB VSPLTISW VSX 0/-1 GPR 0/-1 VMX const GPR const +;; LVX (VMX) STVX (VMX) +(define_insn "*vsx_mov<mode>_32bit" + [(set (match_operand:VSX_M 0 "nonimmediate_operand" + "=ZwO, <VSa>, <VSa>, ??r, ??Y, ??r, + wo, v, ?<VSa>, *r, v, ??r, + wZ, v") + + (match_operand:VSX_M 1 "input_operand" + "<VSa>, ZwO, <VSa>, Y, r, r, + wE, jwM, ?jwM, jwM, W, W, + v, wZ"))] + + "!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode) + && (register_operand (operands[0], <MODE>mode) + || register_operand (operands[1], <MODE>mode))" +{ + return rs6000_output_move_128bit (operands); +} + [(set_attr "type" + "vecstore, vecload, vecsimple, load, store, *, + vecsimple, vecsimple, vecsimple, *, *, *, + vecstore, vecload") + + (set_attr "length" + "4, 4, 4, 16, 16, 16, + 4, 4, 4, 16, 20, 32, + 4, 4")]) ;; Explicit load/store expanders for the builtin functions (define_expand "vsx_load_<mode>" @@ -1449,7 +1492,7 @@ (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "xxsel %x0,%x3,%x2,%x1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) (define_insn "*vsx_xxsel<mode>_uns" [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>") @@ -1460,7 +1503,7 @@ (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "xxsel %x0,%x3,%x2,%x1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) ;; Copy sign (define_insn "vsx_copysign<mode>3" @@ -2086,7 +2129,7 @@ return "xxlor %x0,%x1,%x1"; } - [(set_attr "type" "fp,vecsimple,mftgpr,mftgpr") + [(set_attr "type" "fpsimple,veclogical,mftgpr,mftgpr") (set_attr "length" "4")]) (define_insn "*vsx_extract_<mode>_internal2" @@ -2121,7 +2164,7 @@ operands[3] = GEN_INT (fldDM); return "xxpermdi %x0,%x1,%x1,%3"; } - [(set_attr "type" "fp,vecsimple,vecperm") + [(set_attr "type" "fpsimple,veclogical,vecperm") (set_attr "length" "4")]) ;; Optimize extracting a single scalar element from memory if the scalar is in @@ -2341,20 +2384,61 @@ ;; V2DF/V2DI splat (define_insn "vsx_splat_<mode>" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>,<VSa>,we") (vec_duplicate:VSX_D - (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))] + (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,Z,b")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ xxpermdi %x0,%x1,%x1,0 - xxpermdi %x0,%x1,%x1,0 lxvdsx %x0,%y1 - xxpermdi %x0,%x1,%x1,0 - xxpermdi %x0,%x1,%x1,0 - lxvdsx %x0,%y1" - [(set_attr "type" "vecperm,vecperm,vecload,vecperm,vecperm,vecload")]) + mtvsrdd %x0,%1,%1" + [(set_attr "type" "vecperm,vecload,mftgpr")]) + +;; V4SI splat (ISA 3.0) +;; When SI's are allowed in VSX registers, add XXSPLTW support +(define_expand "vsx_splat_<mode>" + [(set (match_operand:VSX_W 0 "vsx_register_operand" "") + (vec_duplicate:VSX_W + (match_operand:<VS_scalar> 1 "splat_input_operand" "")))] + "TARGET_P9_VECTOR" +{ + if (MEM_P (operands[1])) + operands[1] = rs6000_address_for_fpconvert (operands[1]); + else if (!REG_P (operands[1])) + operands[1] = force_reg (<VS_scalar>mode, operands[1]); +}) + +(define_insn "*vsx_splat_v4si_internal" + [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa") + (vec_duplicate:V4SI + (match_operand:SI 1 "splat_input_operand" "r,Z")))] + "TARGET_P9_VECTOR" + "@ + mtvsrws %x0,%1 + lxvwsx %x0,%y1" + [(set_attr "type" "mftgpr,vecload")]) + +;; V4SF splat (ISA 3.0) +(define_insn_and_split "*vsx_splat_v4sf_internal" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,wa") + (vec_duplicate:V4SF + (match_operand:SF 1 "splat_input_operand" "Z,wy,r")))] + "TARGET_P9_VECTOR" + "@ + lxvwsx %x0,%y1 + # + mtvsrws %x0,%1" + "&& reload_completed && vsx_register_operand (operands[1], SFmode)" + [(set (match_dup 0) + (unspec:V4SF [(match_dup 1)] UNSPEC_VSX_CVDPSPN)) + (set (match_dup 0) + (unspec:V4SF [(match_dup 0) + (const_int 0)] UNSPEC_VSX_XXSPLTW))] + "" + [(set_attr "type" "vecload,vecperm,mftgpr") + (set_attr "length" "4,8,4")]) -;; V4SF/V4SI splat +;; V4SF/V4SI splat from a vector element (define_insn "vsx_xxspltw_<mode>" [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") (vec_duplicate:VSX_W @@ -2597,21 +2681,50 @@ (define_peephole [(set (match_operand:P 0 "base_reg_operand" "") (match_operand:P 1 "short_cint_operand" "")) - (set (match_operand:VSX_M2 2 "vsx_register_operand" "") - (mem:VSX_M2 (plus:P (match_dup 0) - (match_operand:P 3 "int_reg_operand" ""))))] + (set (match_operand:VSX_M 2 "vsx_register_operand" "") + (mem:VSX_M (plus:P (match_dup 0) + (match_operand:P 3 "int_reg_operand" ""))))] "TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR" - "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3" + "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M:VSm>x %x2,%0,%3" [(set_attr "length" "8") (set_attr "type" "vecload")]) (define_peephole [(set (match_operand:P 0 "base_reg_operand" "") (match_operand:P 1 "short_cint_operand" "")) - (set (match_operand:VSX_M2 2 "vsx_register_operand" "") - (mem:VSX_M2 (plus:P (match_operand:P 3 "int_reg_operand" "") - (match_dup 0))))] + (set (match_operand:VSX_M 2 "vsx_register_operand" "") + (mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand" "") + (match_dup 0))))] "TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR" - "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3" + "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M:VSm>x %x2,%0,%3" [(set_attr "length" "8") (set_attr "type" "vecload")]) + + +;; ISA 3.0 vector extend sign support + +(define_insn "vsx_sign_extend_qi_<mode>" + [(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v") + (unspec:VSINT_84 + [(match_operand:V16QI 1 "vsx_register_operand" "v")] + UNSPEC_VSX_SIGN_EXTEND))] + "TARGET_P9_VECTOR" + "vextsb2<wd> %0,%1" + [(set_attr "type" "vecexts")]) + +(define_insn "*vsx_sign_extend_hi_<mode>" + [(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v") + (unspec:VSINT_84 + [(match_operand:V8HI 1 "vsx_register_operand" "v")] + UNSPEC_VSX_SIGN_EXTEND))] + "TARGET_P9_VECTOR" + "vextsh2<wd> %0,%1" + [(set_attr "type" "vecexts")]) + +(define_insn "*vsx_sign_extend_si_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=v") + (unspec:V2DI [(match_operand:V4SI 1 "vsx_register_operand" "v")] + UNSPEC_VSX_SIGN_EXTEND))] + "TARGET_P9_VECTOR" + "vextsw2d %0,%1" + [(set_attr "type" "vecexts")]) diff --git a/gcc/config/rs6000/xfpu.md b/gcc/config/rs6000/xfpu.md index 14557eb81b7..963a1b5e751 100644 --- a/gcc/config/rs6000/xfpu.md +++ b/gcc/config/rs6000/xfpu.md @@ -55,7 +55,7 @@ (define_insn_reservation "fp-default" 2 (and (and - (eq_attr "type" "fp") + (eq_attr "type" "fp,fpsimple") (eq_attr "fp_type" "fp_default")) (eq_attr "cpu" "ppc405")) "Xfpu_issue*2") @@ -67,14 +67,14 @@ (define_insn_reservation "fp-addsub-s" 14 (and (and - (eq_attr "type" "fp") + (eq_attr "type" "fp,fpsimple") (eq_attr "fp_type" "fp_addsub_s")) (eq_attr "cpu" "ppc405")) "Xfpu_issue*2,Xfpu_addsub") (define_insn_reservation "fp-addsub-d" 18 (and (and - (eq_attr "type" "fp") + (eq_attr "type" "fp,fpsimple") (eq_attr "fp_type" "fp_addsub_d")) (eq_attr "cpu" "ppc405")) "Xfpu_issue*2,Xfpu_addsub") diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index a1d0930c071..50fee7cf0d4 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -791,7 +791,7 @@ s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED) { -#define MAX_ARGS 5 +#define MAX_ARGS 6 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); unsigned int fcode = DECL_FUNCTION_CODE (fndecl); diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c index 7e9ee24ac24..ea174bf3dc5 100644 --- a/gcc/config/sparc/driver-sparc.c +++ b/gcc/config/sparc/driver-sparc.c @@ -75,6 +75,8 @@ static const struct cpu_names { { "UltraSparc T4", "niagara4" }, { "LEON", "leon3" }, #endif + { "SPARC-M7", "niagara7" }, + { "SPARC-S7", "niagara7" }, { NULL, NULL } }; diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index a1ef3259469..9d53c29ede1 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -164,22 +164,42 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #endif /* Support for a compile-time default CPU, et cetera. The rules are: - --with-cpu is ignored if -mcpu is specified. - --with-tune is ignored if -mtune is specified. + --with-cpu is ignored if -mcpu is specified; likewise --with-cpu-32 + and --with-cpu-64. + --with-tune is ignored if -mtune is specified; likewise --with-tune-32 + and --with-tune-64. --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu are specified. In the SPARC_BI_ARCH compiler we cannot pass %{!mcpu=*:-mcpu=%(VALUE)} here, otherwise say -mcpu=v7 would be passed even when -m64. - CC1_SPEC above takes care of this instead. */ + CC1_SPEC above takes care of this instead. + + Note that the order of the cpu* and tune* options matters: the + config.gcc file always sets with_cpu to some value, even if the + user didn't use --with-cpu when invoking the configure script. + This value is based on the target name. Therefore we have to make + sure that --with-cpu-32 takes precedence to --with-cpu in < v9 + systems, and that --with-cpu-64 takes precedence to --with-cpu in + >= v9 systems. As for the tune* options, in some platforms + config.gcc also sets a default value for it if the user didn't use + --with-tune when invoking the configure script. */ #undef OPTION_DEFAULT_SPECS #if DEFAULT_ARCH32_P #define OPTION_DEFAULT_SPECS \ + {"cpu_32", "%{!m64:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"cpu_64", "%{m64:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ {"cpu", "%{!m64:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"tune_32", "%{!m64:%{!mtune=*:-mtune=%(VALUE)}}" }, \ + {"tune_64", "%{m64:%{!mtune=*:-mtune=%(VALUE)}}" }, \ {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } #else #define OPTION_DEFAULT_SPECS \ + {"cpu_32", "%{m32:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"cpu_64", "%{!m32:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ {"cpu", "%{!m32:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"tune_32", "%{m32:%{!mtune=*:-mtune=%(VALUE)}}" }, \ + {"tune_64", "%{!m32:%{!mtune=*:-mtune=%(VALUE)}}" }, \ {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } #endif diff --git a/gcc/config/sparc/niagara4.md b/gcc/config/sparc/niagara4.md index a826fb458b4..925fc6c800b 100644 --- a/gcc/config/sparc/niagara4.md +++ b/gcc/config/sparc/niagara4.md @@ -75,6 +75,13 @@ (eq_attr "fptype" "double"))) "n4_slot1") +;; The latency numbers for VIS instructions in the reservations below +;; reflect empirical results, and don't match with the documented +;; latency numbers in the T4 Processor Supplement. This is because +;; the HW chaps didn't feel it necessary to document the complexity in +;; the PRM, and just assigned a latency of 11 to all/most of the VIS +;; instructions. + (define_insn_reservation "n4_vis_move_11cycle" 11 (and (eq_attr "cpu" "niagara4") (and (eq_attr "type" "vismv") diff --git a/gcc/config/sparc/niagara7.md b/gcc/config/sparc/niagara7.md new file mode 100644 index 00000000000..56a4edb80c6 --- /dev/null +++ b/gcc/config/sparc/niagara7.md @@ -0,0 +1,136 @@ +;; Scheduling description for Niagara-7 +;; Copyright (C) 2016 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_automaton "niagara7_0") + +(define_cpu_unit "n7_slot0,n7_slot1,n7_slot2" "niagara7_0") +(define_reservation "n7_single_issue" "n7_slot0 + n7_slot1 + n7_slot2") + +(define_cpu_unit "n7_load_store" "niagara7_0") + +(define_insn_reservation "n7_single" 1 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "multi,savew,flushw,trap")) + "n7_single_issue") + +(define_insn_reservation "n7_iflush" 27 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "iflush")) + "(n7_slot0 | n7_slot1), nothing*26") + +(define_insn_reservation "n7_integer" 1 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "ialu,ialuX,shift,cmove,compare")) + "(n7_slot0 | n7_slot1)") + +(define_insn_reservation "n7_imul" 12 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "imul")) + "n7_slot1, nothing*11") + +(define_insn_reservation "n7_idiv" 35 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "idiv")) + "n7_slot1, nothing*34") + +(define_insn_reservation "n7_load" 5 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "load,fpload,sload")) + "(n7_slot0 + n7_load_store), nothing*4") + +(define_insn_reservation "n7_store" 1 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "store,fpstore")) + "(n7_slot0 | n7_slot2) + n7_load_store") + +(define_insn_reservation "n7_cti" 1 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return")) + "n7_slot1") + +(define_insn_reservation "n7_fp" 11 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul")) + "n7_slot1, nothing*10") + +(define_insn_reservation "n7_array" 12 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "array,edge,edgen")) + "n7_slot1, nothing*11") + +(define_insn_reservation "n7_fpdivs" 24 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "fpdivs,fpsqrts")) + "n7_slot1, nothing*23") + +(define_insn_reservation "n7_fpdivd" 37 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "fpdivd,fpsqrtd")) + "n7_slot1, nothing*36") + +(define_insn_reservation "n7_lzd" 12 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "lzd")) + "(n7_slot0 | n7_slot1), nothing*11") + +;; There is an internal unit called the "V3 pipe", that was originally +;; intended to process some of the short cryptographic instructions. +;; However, as soon as in the T4 several of the VIS instructions +;; (notably non-FP instructions) have been moved to the V3 pipe. +;; Consequently, these instructions feature a latency of 3 instead of +;; 11 or 12 cycles, provided their consumers also execute in the V3 +;; pipe. +;; +;; This is modelled here with a bypass. + +(define_insn_reservation "n7_vis_fga" 11 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "fga,gsr")) + "n7_slot1, nothing*10") + +(define_insn_reservation "n7_vis_fgm" 11 + (and (eq_attr "cpu" "niagara7") + (eq_attr "type" "fgm_pack,fgm_mul,pdist")) + "n7_slot1, nothing*10") + +(define_insn_reservation "n7_vis_move_v3pipe" 11 + (and (eq_attr "cpu" "niagara7") + (and (eq_attr "type" "vismv") + (eq_attr "v3pipe" "true"))) + "n7_slot1") + +(define_insn_reservation "n7_vis_move_11cycle" 11 + (and (eq_attr "cpu" "niagara7") + (and (eq_attr "type" "vismv") + (eq_attr "v3pipe" "false"))) + "n7_slot1, nothing*10") + +(define_insn_reservation "n7_vis_logical_v3pipe" 11 + (and (eq_attr "cpu" "niagara7") + (and (eq_attr "type" "visl,pdistn") + (eq_attr "v3pipe" "true"))) + "n7_slot1, nothing*2") + +(define_insn_reservation "n7_vis_logical_11cycle" 11 + (and (eq_attr "cpu" "niagara7") + (and (eq_attr "type" "visl") + (eq_attr "v3pipe" "false"))) + "n7_slot1, nothing*10") + +(define_bypass 3 "*_v3pipe" "*_v3pipe") diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index 07e6368caea..2a843c5c262 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -165,13 +165,22 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA4_FLAG #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 +#undef CPP_CPU64_DEFAULT_SPEC +#define CPP_CPU64_DEFAULT_SPEC "" +#undef ASM_CPU32_DEFAULT_SPEC +#define ASM_CPU32_DEFAUILT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG +#undef ASM_CPU64_DEFAULT_SPEC +#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG +#endif + #undef CPP_CPU_SPEC #define CPP_CPU_SPEC "\ %{mcpu=sparclet|mcpu=tsc701:-D__sparclet__} \ %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \ %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ -%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2|mcpu=niagara3|mcpu=niagara4:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2|mcpu=niagara3|mcpu=niagara4|mcpu=niagara7:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{!mcpu*:%(cpp_cpu_default)} \ " @@ -231,22 +240,42 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #endif /* Support for a compile-time default CPU, et cetera. The rules are: - --with-cpu is ignored if -mcpu is specified. - --with-tune is ignored if -mtune is specified. + --with-cpu is ignored if -mcpu is specified; likewise --with-cpu-32 + and --with-cpu-64. + --with-tune is ignored if -mtune is specified; likewise --with-tune-32 + and --with-tune-64. --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu are specified. In the SPARC_BI_ARCH compiler we cannot pass %{!mcpu=*:-mcpu=%(VALUE)} here, otherwise say -mcpu=v7 would be passed even when -m64. - CC1_SPEC above takes care of this instead. */ + CC1_SPEC above takes care of this instead. + + Note that the order of the cpu* and tune* options matters: the + config.gcc file always sets with_cpu to some value, even if the + user didn't use --with-cpu when invoking the configure script. + This value is based on the target name. Therefore we have to make + sure that --with-cpu-32 takes precedence to --with-cpu in < v9 + systems, and that --with-cpu-64 takes precedence to --with-cpu in + >= v9 systems. As for the tune* options, in some platforms + config.gcc also sets a default value for it if the user didn't use + --with-tune when invoking the configure script. */ #undef OPTION_DEFAULT_SPECS #if DEFAULT_ARCH32_P #define OPTION_DEFAULT_SPECS \ + {"cpu_32", "%{!m64:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"cpu_64", "%{m64:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ {"cpu", "%{!m64:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"tune_32", "%{!m64:%{!mtune=*:-mtune=%(VALUE)}}" }, \ + {"tune_64", "%{m64:%{!mtune=*:-mtune=%(VALUE)}}" }, \ {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } #else #define OPTION_DEFAULT_SPECS \ + {"cpu_32", "%{m32:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"cpu_64", "%{!m32:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ {"cpu", "%{!m32:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"tune_32", "%{m32:%{!mtune=*:-mtune=%(VALUE)}}" }, \ + {"tune_64", "%{!m32:%{!mtune=*:-mtune=%(VALUE)}}" }, \ {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } #endif @@ -260,7 +289,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); %{mcpu=niagara2:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC("-xarch=v9b") "} \ %{mcpu=niagara3:" DEF_ARCH32_SPEC("-xarch=v8plus" AS_NIAGARA3_FLAG) DEF_ARCH64_SPEC("-xarch=v9" AS_NIAGARA3_FLAG) "} \ %{mcpu=niagara4:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA4_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA4_FLAG) "} \ -%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}}}}}}} \ +%{mcpu=niagara7:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA7_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA7_FLAG) "} \ +%{!mcpu=niagara7:%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}}}}}}}} \ %{!mcpu*:%(asm_cpu_default)} \ " diff --git a/gcc/config/sparc/sparc-c.c b/gcc/config/sparc/sparc-c.c index d3fd60e403d..d9f9c15d2e3 100644 --- a/gcc/config/sparc/sparc-c.c +++ b/gcc/config/sparc/sparc-c.c @@ -40,7 +40,12 @@ sparc_target_macros (void) cpp_assert (parse_in, "machine=sparc"); } - if (TARGET_VIS3) + if (TARGET_VIS4) + { + cpp_define (parse_in, "__VIS__=0x400"); + cpp_define (parse_in, "__VIS__=0x400"); + } + else if (TARGET_VIS3) { cpp_define (parse_in, "__VIS__=0x300"); cpp_define (parse_in, "__VIS=0x300"); diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h index ce48f182c3c..40d23a223e3 100644 --- a/gcc/config/sparc/sparc-opts.h +++ b/gcc/config/sparc/sparc-opts.h @@ -45,6 +45,7 @@ enum processor_type { PROCESSOR_NIAGARA2, PROCESSOR_NIAGARA3, PROCESSOR_NIAGARA4, + PROCESSOR_NIAGARA7, PROCESSOR_NATIVE }; diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 082af3cc9b1..1d2ecaaf3dc 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -423,6 +423,30 @@ struct processor_costs niagara4_costs = { 0, /* shift penalty */ }; +static const +struct processor_costs niagara7_costs = { + COSTS_N_INSNS (5), /* int load */ + COSTS_N_INSNS (5), /* int signed load */ + COSTS_N_INSNS (5), /* int zeroed load */ + COSTS_N_INSNS (5), /* float load */ + COSTS_N_INSNS (11), /* fmov, fneg, fabs */ + COSTS_N_INSNS (11), /* fadd, fsub */ + COSTS_N_INSNS (11), /* fcmp */ + COSTS_N_INSNS (11), /* fmov, fmovr */ + COSTS_N_INSNS (11), /* fmul */ + COSTS_N_INSNS (24), /* fdivs */ + COSTS_N_INSNS (37), /* fdivd */ + COSTS_N_INSNS (24), /* fsqrts */ + COSTS_N_INSNS (37), /* fsqrtd */ + COSTS_N_INSNS (12), /* imul */ + COSTS_N_INSNS (12), /* imulX */ + 0, /* imul bit factor */ + COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */ + COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */ + COSTS_N_INSNS (1), /* movcc/movr */ + 0, /* shift penalty */ +}; + static const struct processor_costs *sparc_costs = &cypress_costs; #ifdef HAVE_AS_RELAX_OPTION @@ -1175,6 +1199,8 @@ dump_target_flag_bits (const int flags) fprintf (stderr, "VIS2 "); if (flags & MASK_VIS3) fprintf (stderr, "VIS3 "); + if (flags & MASK_VIS4) + fprintf (stderr, "VIS4 "); if (flags & MASK_CBCOND) fprintf (stderr, "CBCOND "); if (flags & MASK_DEPRECATED_V8_INSNS) @@ -1238,6 +1264,7 @@ sparc_option_override (void) { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 }, { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 }, { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 }, + { TARGET_CPU_niagara7, PROCESSOR_NIAGARA7 }, { -1, PROCESSOR_V7 } }; const struct cpu_default *def; @@ -1287,6 +1314,9 @@ sparc_option_override (void) /* UltraSPARC T4 */ { "niagara4", MASK_ISA, MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF|MASK_CBCOND }, + /* UltraSPARC M7 */ + { "niagara7", MASK_ISA, + MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_VIS4|MASK_FMAF|MASK_CBCOND }, }; const struct cpu_table *cpu; unsigned int i; @@ -1416,6 +1446,9 @@ sparc_option_override (void) #ifndef HAVE_AS_SPARC4 & ~MASK_CBCOND #endif +#ifndef HAVE_AS_SPARC5_VIS4 + & ~MASK_VIS4 +#endif #ifndef HAVE_AS_LEON & ~(MASK_LEON | MASK_LEON3) #endif @@ -1434,10 +1467,15 @@ sparc_option_override (void) if (TARGET_VIS3) target_flags |= MASK_VIS2 | MASK_VIS; - /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is + /* -mvis4 implies -mvis3, -mvis2 and -mvis */ + if (TARGET_VIS4) + target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS; + + /* Don't allow -mvis, -mvis2, -mvis3, -mvis4 or -mfmaf if FPU is disabled. */ if (! TARGET_FPU) - target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_FMAF); + target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4 + | MASK_FMAF); /* -mvis assumes UltraSPARC+, so we are sure v9 instructions are available. @@ -1471,7 +1509,8 @@ sparc_option_override (void) || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 - || sparc_cpu == PROCESSOR_NIAGARA4)) + || sparc_cpu == PROCESSOR_NIAGARA4 + || sparc_cpu == PROCESSOR_NIAGARA7)) align_functions = 32; /* Validate PCC_STRUCT_RETURN. */ @@ -1535,6 +1574,9 @@ sparc_option_override (void) case PROCESSOR_NIAGARA4: sparc_costs = &niagara4_costs; break; + case PROCESSOR_NIAGARA7: + sparc_costs = &niagara7_costs; + break; case PROCESSOR_NATIVE: gcc_unreachable (); }; @@ -1566,6 +1608,29 @@ sparc_option_override (void) if (TARGET_DEBUG_OPTIONS) dump_target_flags ("Final target_flags", target_flags); + /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that + can run at the same time. More important, it is the threshold + defining when additional prefetches will be dropped by the + hardware. + + The UltraSPARC-III features a documented prefetch queue with a + size of 8. Additional prefetches issued in the cpu are + dropped. + + Niagara processors are different. In these processors prefetches + are handled much like regular loads. The L1 miss buffer is 32 + entries, but prefetches start getting affected when 30 entries + become occupied. That occupation could be a mix of regular loads + and prefetches though. And that buffer is shared by all threads. + Once the threshold is reached, if the core is running a single + thread the prefetch will retry. If more than one thread is + running, the prefetch will be dropped. + + All this makes it very difficult to determine how many + simultaneous prefetches can be issued simultaneously, even in a + single-threaded program. Experimental results show that setting + this parameter to 32 works well when the number of threads is not + high. */ maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, ((sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_NIAGARA @@ -1574,20 +1639,55 @@ sparc_option_override (void) || sparc_cpu == PROCESSOR_NIAGARA4) ? 2 : (sparc_cpu == PROCESSOR_ULTRASPARC3 - ? 8 : 3)), + ? 8 : (sparc_cpu == PROCESSOR_NIAGARA7 + ? 32 : 3))), global_options.x_param_values, global_options_set.x_param_values); - maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, + + /* For PARAM_L1_CACHE_LINE_SIZE we use the default 32 bytes (see + params.def), so no maybe_set_param_value is needed. + + The Oracle SPARC Architecture (previously the UltraSPARC + Architecture) specification states that when a PREFETCH[A] + instruction is executed an implementation-specific amount of data + is prefetched, and that it is at least 64 bytes long (aligned to + at least 64 bytes). + + However, this is not correct. The M7 (and implementations prior + to that) does not guarantee a 64B prefetch into a cache if the + line size is smaller. A single cache line is all that is ever + prefetched. So for the M7, where the L1D$ has 32B lines and the + L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the + L2 and L3, but only 32B are brought into the L1D$. (Assuming it + is a read_n prefetch, which is the only type which allocates to + the L1.) */ + + /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use + Hardvard level-1 caches) in kilobytes. Both UltraSPARC and + Niagara processors feature a L1D$ of 16KB. */ + maybe_set_param_value (PARAM_L1_CACHE_SIZE, ((sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 - || sparc_cpu == PROCESSOR_NIAGARA4) - ? 64 : 32), + || sparc_cpu == PROCESSOR_NIAGARA4 + || sparc_cpu == PROCESSOR_NIAGARA7) + ? 16 : 64), global_options.x_param_values, global_options_set.x_param_values); + + /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note + that 512 is the default in params.def. */ + maybe_set_param_value (PARAM_L2_CACHE_SIZE, + (sparc_cpu == PROCESSOR_NIAGARA4 + ? 128 : (sparc_cpu == PROCESSOR_NIAGARA7 + ? 256 : 512)), + global_options.x_param_values, + global_options_set.x_param_values); + + /* Disable save slot sharing for call-clobbered registers by default. The IRA sharing algorithm works on single registers only and this pessimizes for double floating-point registers. */ @@ -9178,7 +9278,8 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 - && sparc_cpu != PROCESSOR_NIAGARA4) + && sparc_cpu != PROCESSOR_NIAGARA4 + && sparc_cpu != PROCESSOR_NIAGARA7) emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8)))); /* Call __enable_execute_stack after writing onto the stack to make sure @@ -9223,7 +9324,8 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 - && sparc_cpu != PROCESSOR_NIAGARA4) + && sparc_cpu != PROCESSOR_NIAGARA4 + && sparc_cpu != PROCESSOR_NIAGARA7) emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8)))); /* Call __enable_execute_stack after writing onto the stack to make sure @@ -9419,7 +9521,8 @@ sparc_use_sched_lookahead (void) || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3) return 0; - if (sparc_cpu == PROCESSOR_NIAGARA4) + if (sparc_cpu == PROCESSOR_NIAGARA4 + || sparc_cpu == PROCESSOR_NIAGARA7) return 2; if (sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3) @@ -9442,6 +9545,7 @@ sparc_issue_rate (void) default: return 1; case PROCESSOR_NIAGARA4: + case PROCESSOR_NIAGARA7: case PROCESSOR_V9: /* Assume V9 processors are capable of at least dual-issue. */ return 2; @@ -10007,6 +10111,34 @@ enum sparc_builtins SPARC_BUILTIN_XMULX, SPARC_BUILTIN_XMULXHI, + /* VIS 4.0 builtins. */ + SPARC_BUILTIN_FPADD8, + SPARC_BUILTIN_FPADDS8, + SPARC_BUILTIN_FPADDUS8, + SPARC_BUILTIN_FPADDUS16, + SPARC_BUILTIN_FPCMPLE8, + SPARC_BUILTIN_FPCMPGT8, + SPARC_BUILTIN_FPCMPULE16, + SPARC_BUILTIN_FPCMPUGT16, + SPARC_BUILTIN_FPCMPULE32, + SPARC_BUILTIN_FPCMPUGT32, + SPARC_BUILTIN_FPMAX8, + SPARC_BUILTIN_FPMAX16, + SPARC_BUILTIN_FPMAX32, + SPARC_BUILTIN_FPMAXU8, + SPARC_BUILTIN_FPMAXU16, + SPARC_BUILTIN_FPMAXU32, + SPARC_BUILTIN_FPMIN8, + SPARC_BUILTIN_FPMIN16, + SPARC_BUILTIN_FPMIN32, + SPARC_BUILTIN_FPMINU8, + SPARC_BUILTIN_FPMINU16, + SPARC_BUILTIN_FPMINU32, + SPARC_BUILTIN_FPSUB8, + SPARC_BUILTIN_FPSUBS8, + SPARC_BUILTIN_FPSUBUS8, + SPARC_BUILTIN_FPSUBUS16, + SPARC_BUILTIN_MAX }; @@ -10483,6 +10615,83 @@ sparc_vis_init_builtins (void) def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis, SPARC_BUILTIN_XMULXHI, di_ftype_di_di); } + + if (TARGET_VIS4) + { + def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3, + SPARC_BUILTIN_FPADD8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3, + SPARC_BUILTIN_FPADDS8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3, + SPARC_BUILTIN_FPADDUS8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3, + SPARC_BUILTIN_FPADDUS16, v4hi_ftype_v4hi_v4hi); + + + if (TARGET_ARCH64) + { + def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis, + SPARC_BUILTIN_FPCMPLE8, di_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis, + SPARC_BUILTIN_FPCMPGT8, di_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis, + SPARC_BUILTIN_FPCMPULE16, di_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis, + SPARC_BUILTIN_FPCMPUGT16, di_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis, + SPARC_BUILTIN_FPCMPULE32, di_ftype_v2si_v2si); + def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis, + SPARC_BUILTIN_FPCMPUGT32, di_ftype_v2si_v2si); + } + else + { + def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis, + SPARC_BUILTIN_FPCMPLE8, si_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis, + SPARC_BUILTIN_FPCMPGT8, si_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis, + SPARC_BUILTIN_FPCMPULE16, si_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis, + SPARC_BUILTIN_FPCMPUGT16, si_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis, + SPARC_BUILTIN_FPCMPULE32, di_ftype_v2si_v2si); + def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis, + SPARC_BUILTIN_FPCMPUGT32, di_ftype_v2si_v2si); + } + + def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3, + SPARC_BUILTIN_FPMAX8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3, + SPARC_BUILTIN_FPMAX16, v4hi_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3, + SPARC_BUILTIN_FPMAX32, v2si_ftype_v2si_v2si); + def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3, + SPARC_BUILTIN_FPMAXU8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3, + SPARC_BUILTIN_FPMAXU16, v4hi_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3, + SPARC_BUILTIN_FPMAXU32, v2si_ftype_v2si_v2si); + def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3, + SPARC_BUILTIN_FPMIN8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3, + SPARC_BUILTIN_FPMIN16, v4hi_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3, + SPARC_BUILTIN_FPMIN32, v2si_ftype_v2si_v2si); + def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3, + SPARC_BUILTIN_FPMINU8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3, + SPARC_BUILTIN_FPMINU16, v4hi_ftype_v4hi_v4hi); + def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3, + SPARC_BUILTIN_FPMINU32, v2si_ftype_v2si_v2si); + def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3, + SPARC_BUILTIN_FPSUB8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3, + SPARC_BUILTIN_FPSUBS8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3, + SPARC_BUILTIN_FPSUBUS8, v8qi_ftype_v8qi_v8qi); + def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3, + SPARC_BUILTIN_FPSUBUS16, v4hi_ftype_v4hi_v4hi); + } } /* Implement TARGET_BUILTIN_DECL hook. */ @@ -11042,7 +11251,8 @@ sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 - || sparc_cpu == PROCESSOR_NIAGARA4) + || sparc_cpu == PROCESSOR_NIAGARA4 + || sparc_cpu == PROCESSOR_NIAGARA7) return 12; return 6; diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index ebfe87db046..d91496ab6ab 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -142,6 +142,7 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_niagara2 14 #define TARGET_CPU_niagara3 15 #define TARGET_CPU_niagara4 16 +#define TARGET_CPU_niagara7 19 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ @@ -149,7 +150,8 @@ extern enum cmodel sparc_cmodel; || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ - || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 #define CPP_CPU32_DEFAULT_SPEC "" #define ASM_CPU32_DEFAULT_SPEC "" @@ -186,6 +188,10 @@ extern enum cmodel sparc_cmodel; #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 +#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" +#define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG +#endif #else @@ -288,6 +294,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=niagara2:-D__sparc_v9__} \ %{mcpu=niagara3:-D__sparc_v9__} \ %{mcpu=niagara4:-D__sparc_v9__} \ +%{mcpu=niagara7:-D__sparc_v9__} \ %{!mcpu*:%(cpp_cpu_default)} \ " #define CPP_ARCH32_SPEC "" @@ -339,6 +346,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ +%{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \ %{!mcpu*:%(asm_cpu_default)} \ " @@ -1777,6 +1785,12 @@ extern int sparc_indent_opcode; #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG #endif +#ifdef HAVE_AS_SPARC5_VIS4 +#define AS_NIAGARA7_FLAG "-xarch=sparc5" +#else +#define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG +#endif + #ifdef HAVE_AS_LEON #define AS_LEON_FLAG "-Aleon" #define AS_LEONV7_FLAG "-Aleon" diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 56d4f63017d..29e4966fccb 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -234,7 +234,8 @@ niagara, niagara2, niagara3, - niagara4" + niagara4, + niagara7" (const (symbol_ref "sparc_cpu_attr"))) ;; Attribute for the instruction set. @@ -247,7 +248,7 @@ (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")] (const_string "v7")))) -(define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3" (const_string "none")) +(define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4" (const_string "none")) (define_attr "enabled" "" (cond [(eq_attr "cpu_feature" "none") (const_int 1) @@ -255,7 +256,8 @@ (eq_attr "cpu_feature" "fpunotv9") (symbol_ref "TARGET_FPU && ! TARGET_V9") (eq_attr "cpu_feature" "v9") (symbol_ref "TARGET_V9") (eq_attr "cpu_feature" "vis") (symbol_ref "TARGET_VIS") - (eq_attr "cpu_feature" "vis3") (symbol_ref "TARGET_VIS3")] + (eq_attr "cpu_feature" "vis3") (symbol_ref "TARGET_VIS3") + (eq_attr "cpu_feature" "vis4") (symbol_ref "TARGET_VIS4")] (const_int 0))) ;; Insn type. @@ -274,7 +276,7 @@ fga,visl,vismv,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array, cmove, ialuX, - multi,savew,flushw,iflush,trap" + multi,savew,flushw,iflush,trap,lzd" (const_string "ialu")) ;; True if branch/call has empty delay slot and will emit a nop in it @@ -476,6 +478,10 @@ (const_string "true") ] (const_string "false"))) +;; True if the instruction executes in the V3 pipeline, in M7 and +;; later processors. +(define_attr "v3pipe" "false,true" (const_string "false")) + (define_delay (eq_attr "type" "call") [(eq_attr "in_call_delay" "true") (nil) (nil)]) @@ -504,6 +510,7 @@ (include "niagara.md") (include "niagara2.md") (include "niagara4.md") +(include "niagara7.md") ;; Operand and operator predicates and constraints @@ -1457,6 +1464,7 @@ fzeros\t%0 fones\t%0" [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl") + (set_attr "v3pipe" "*,*,*,*,true,true,*,*,*,true,true") (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")]) (define_insn "*movsi_lo_sum" @@ -1622,6 +1630,7 @@ fzero\t%0 fone\t%0" [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,*,*,*,fpload,fpstore,visl,visl") + (set_attr "v3pipe" "false, false, false, false,false,false,false,false,false,false,false,false,false,false,false,false,false,false, true, true") (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,2,2,2,*,*,*,*") (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double") (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")]) @@ -1645,6 +1654,7 @@ fzero\t%0 fone\t%0" [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl") + (set_attr "v3pipe" "*, *, *, *, *, *, *, *, *, true, true") (set_attr "fptype" "*,*,*,*,*,*,double,*,*,double,double") (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")]) @@ -2208,6 +2218,7 @@ } } [(set_attr "type" "visl,visl,fpmove,*,*,*,vismv,vismv,fpload,load,fpstore,store") + (set_attr "v3pipe" "true, true, *, *, *, *, true, true, *, *, *, *") (set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*")]) ;; The following 3 patterns build SFmode constants in integer registers. @@ -2276,6 +2287,7 @@ # #" [(set_attr "type" "visl,visl,fpmove,*,*,*,fpload,store,fpstore,load,store,*,*,*,*") + (set_attr "v3pipe" "true, true, *, *, *, *, *, *, *, *, *, *, *, *, *") (set_attr "length" "*,*,*,2,2,2,*,*,*,*,*,2,2,2,2") (set_attr "fptype" "double,double,double,*,*,*,*,*,*,*,*,*,*,*,*") (set_attr "cpu_feature" "vis,vis,v9,fpunotv9,vis3,vis3,fpu,v9,fpu,*,*,fpu,*,*,fpu")]) @@ -2299,6 +2311,7 @@ stx\t%r1, %0 #" [(set_attr "type" "visl,visl,fpmove,vismv,vismv,load,store,*,load,store,*") + (set_attr "v3pipe" "true, true, *, *, *, *, *, *, *, *, *") (set_attr "length" "*,*,*,*,*,*,*,*,*,*,2") (set_attr "fptype" "double,double,double,double,double,*,*,*,*,*,*") (set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*")]) @@ -2980,6 +2993,7 @@ lduw\t%1, %0 movstouw\t%1, %0" [(set_attr "type" "shift,load,*") + (set_attr "v3pipe" "*,*,true") (set_attr "cpu_feature" "*,*,vis3")]) (define_insn_and_split "*zero_extendsidi2_insn_sp32" @@ -3294,6 +3308,7 @@ ldsw\t%1, %0 movstosw\t%1, %0" [(set_attr "type" "shift,sload,*") + (set_attr "v3pipe" "*,*,true") (set_attr "us3load_type" "*,3cycle,*") (set_attr "cpu_feature" "*,*,vis3")]) @@ -6770,7 +6785,8 @@ [(set (match_operand:DI 0 "register_operand" "=r") (clz:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_VIS3 && TARGET_ARCH64" - "lzd\t%1, %0") + "lzd\t%1, %0" + [(set_attr "type" "lzd")]) (define_insn "clzdi_v8plus" [(set (match_operand:DI 0 "register_operand" "=r") @@ -6811,7 +6827,8 @@ (truncate:SI (clz:DI (match_operand:DI 1 "register_operand" "r"))))] "TARGET_VIS3 && TARGET_ARCH64" - "lzd\t%1, %0") + "lzd\t%1, %0" + [(set_attr "type" "lzd")]) (define_insn "clzsi_v8plus" [(set (match_operand:SI 0 "register_operand" "=r") @@ -7777,7 +7794,7 @@ (define_mode_iterator VM64 [V1DI V2SI V4HI V8QI]) (define_mode_iterator VMALL [V1SI V2HI V4QI V1DI V2SI V4HI V8QI]) -(define_mode_attr vbits [(V2SI "32") (V4HI "16") (V1SI "32s") (V2HI "16s")]) +(define_mode_attr vbits [(V2SI "32") (V4HI "16") (V1SI "32s") (V2HI "16s") (V8QI "8")]) (define_mode_attr vconstr [(V1SI "f") (V2HI "f") (V4QI "f") (V1DI "e") (V2SI "e") (V4HI "e") (V8QI "e")]) (define_mode_attr vfptype [(V1SI "single") (V2HI "single") (V4QI "single") @@ -7812,6 +7829,7 @@ movstouw\t%1, %0 movwtos\t%1, %0" [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,*,vismv,vismv") + (set_attr "v3pipe" "true,true,true,false,false,false,false,false,false,true,true") (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")]) (define_insn "*mov<VM64:mode>_insn_sp64" @@ -7834,6 +7852,7 @@ movxtod\t%1, %0 mov\t%1, %0" [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,vismv,vismv,*") + (set_attr "v3pipe" "true, true, true, false, false, false, false, false, false, false, false") (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")]) (define_insn "*mov<VM64:mode>_insn_sp32" @@ -7857,6 +7876,7 @@ # #" [(set_attr "type" "visl,visl,vismv,*,*,fpload,fpstore,store,load,store,*,*") + (set_attr "v3pipe" "true, true, true, false, false, false, false, false, false, false, false, false") (set_attr "length" "*,*,*,2,2,*,*,*,*,*,2,2") (set_attr "cpu_feature" "vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*")]) @@ -7936,7 +7956,8 @@ "TARGET_VIS" "fp<plusminus_insn><vbits>\t%1, %2, %0" [(set_attr "type" "fga") - (set_attr "fptype" "<vfptype>")]) + (set_attr "fptype" "<vfptype>") + (set_attr "v3pipe" "true")]) (define_mode_iterator VL [V1SI V2HI V4QI V1DI V2SI V4HI V8QI]) (define_mode_attr vlsuf [(V1SI "s") (V2HI "s") (V4QI "s") @@ -7952,6 +7973,7 @@ "TARGET_VIS" "f<vlinsn><vlsuf>\t%1, %2, %0" [(set_attr "type" "visl") + (set_attr "v3pipe" "true") (set_attr "fptype" "<vfptype>")]) (define_insn "*not_<code><mode>3" @@ -7961,6 +7983,7 @@ "TARGET_VIS" "f<vlninsn><vlsuf>\t%1, %2, %0" [(set_attr "type" "visl") + (set_attr "v3pipe" "true") (set_attr "fptype" "<vfptype>")]) ;; (ior (not (op1)) (not (op2))) is the canonical form of NAND. @@ -7971,6 +7994,7 @@ "TARGET_VIS" "fnand<vlsuf>\t%1, %2, %0" [(set_attr "type" "visl") + (set_attr "v3pipe" "true") (set_attr "fptype" "<vfptype>")]) (define_code_iterator vlnotop [ior and]) @@ -7982,6 +8006,7 @@ "TARGET_VIS" "f<vlinsn>not1<vlsuf>\t%1, %2, %0" [(set_attr "type" "visl") + (set_attr "v3pipe" "true") (set_attr "fptype" "<vfptype>")]) (define_insn "*<code>_not2<mode>_vis" @@ -7991,6 +8016,7 @@ "TARGET_VIS" "f<vlinsn>not2<vlsuf>\t%1, %2, %0" [(set_attr "type" "visl") + (set_attr "v3pipe" "true") (set_attr "fptype" "<vfptype>")]) (define_insn "one_cmpl<mode>2" @@ -7999,6 +8025,7 @@ "TARGET_VIS" "fnot1<vlsuf>\t%1, %0" [(set_attr "type" "visl") + (set_attr "v3pipe" "true") (set_attr "fptype" "<vfptype>")]) ;; Hard to generate VIS instructions. We have builtins for these. @@ -8225,7 +8252,8 @@ "TARGET_VIS" "faligndata\t%1, %2, %0" [(set_attr "type" "fga") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "v3pipe" "true")]) (define_insn "alignaddrsi_vis" [(set (match_operand:SI 0 "register_operand" "=r") @@ -8235,7 +8263,8 @@ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] "TARGET_VIS" "alignaddr\t%r1, %r2, %0" - [(set_attr "type" "gsr")]) + [(set_attr "type" "gsr") + (set_attr "v3pipe" "true")]) (define_insn "alignaddrdi_vis" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8245,7 +8274,8 @@ (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_VIS" "alignaddr\t%r1, %r2, %0" - [(set_attr "type" "gsr")]) + [(set_attr "type" "gsr") + (set_attr "v3pipe" "true")]) (define_insn "alignaddrlsi_vis" [(set (match_operand:SI 0 "register_operand" "=r") @@ -8256,7 +8286,8 @@ (const_int 7)))] "TARGET_VIS" "alignaddrl\t%r1, %r2, %0" - [(set_attr "type" "gsr")]) + [(set_attr "type" "gsr") + (set_attr "v3pipe" "true")]) (define_insn "alignaddrldi_vis" [(set (match_operand:DI 0 "register_operand" "=r") @@ -8267,7 +8298,8 @@ (const_int 7)))] "TARGET_VIS" "alignaddrl\t%r1, %r2, %0" - [(set_attr "type" "gsr")]) + [(set_attr "type" "gsr") + (set_attr "v3pipe" "true")]) (define_insn "pdist_vis" [(set (match_operand:DI 0 "register_operand" "=e") @@ -8360,6 +8392,17 @@ "TARGET_VIS" "fcmp<code><GCM:gcm_name>\t%1, %2, %0" [(set_attr "type" "visl") + (set_attr "v3pipe" "true") + (set_attr "fptype" "double")]) + +(define_insn "fpcmp<code>8<P:mode>_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") + (match_operand:V8QI 2 "register_operand" "e"))] + UNSPEC_FCMP))] + "TARGET_VIS4" + "fpcmp<code>8\t%1, %2, %0" + [(set_attr "type" "visl") (set_attr "fptype" "double")]) (define_expand "vcond<mode><mode>" @@ -8427,7 +8470,8 @@ (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_VIS2" "bmask\t%r1, %r2, %0" - [(set_attr "type" "array")]) + [(set_attr "type" "array") + (set_attr "v3pipe" "true")]) (define_insn "bmasksi_vis" [(set (match_operand:SI 0 "register_operand" "=r") @@ -8437,7 +8481,8 @@ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] "TARGET_VIS2" "bmask\t%r1, %r2, %0" - [(set_attr "type" "array")]) + [(set_attr "type" "array") + (set_attr "v3pipe" "true")]) (define_insn "bshuffle<VM64:mode>_vis" [(set (match_operand:VM64 0 "register_operand" "=e") @@ -8448,7 +8493,8 @@ "TARGET_VIS2" "bshuffle\t%1, %2, %0" [(set_attr "type" "fga") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "v3pipe" "true")]) ;; The rtl expanders will happily convert constant permutations on other ;; modes down to V8QI. Rely on this to avoid the complexity of the byte @@ -8550,7 +8596,8 @@ UNSPEC_CMASK8))] "TARGET_VIS3" "cmask8\t%r0" - [(set_attr "type" "fga")]) + [(set_attr "type" "fga") + (set_attr "v3pipe" "true")]) (define_insn "cmask16<P:mode>_vis" [(set (reg:DI GSR_REG) @@ -8559,7 +8606,8 @@ UNSPEC_CMASK16))] "TARGET_VIS3" "cmask16\t%r0" - [(set_attr "type" "fga")]) + [(set_attr "type" "fga") + (set_attr "v3pipe" "true")]) (define_insn "cmask32<P:mode>_vis" [(set (reg:DI GSR_REG) @@ -8568,7 +8616,8 @@ UNSPEC_CMASK32))] "TARGET_VIS3" "cmask32\t%r0" - [(set_attr "type" "fga")]) + [(set_attr "type" "fga") + (set_attr "v3pipe" "true")]) (define_insn "fchksm16_vis" [(set (match_operand:V4HI 0 "register_operand" "=e") @@ -8601,6 +8650,7 @@ "TARGET_VIS3" "pdistn\t%1, %2, %0" [(set_attr "type" "pdistn") + (set_attr "v3pipe" "true") (set_attr "fptype" "double")]) (define_insn "fmean16_vis" @@ -8628,6 +8678,14 @@ "fp<plusminus_insn>64\t%1, %2, %0" [(set_attr "type" "fga")]) +(define_insn "<plusminus_insn>v8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=e") + (plusminus:V8QI (match_operand:V8QI 1 "register_operand" "e") + (match_operand:V8QI 2 "register_operand" "e")))] + "TARGET_VIS4" + "fp<plusminus_insn>8\t%1, %2, %0" + [(set_attr "type" "fga")]) + (define_mode_iterator VASS [V4HI V2SI V2HI V1SI]) (define_code_iterator vis3_addsub_ss [ss_plus ss_minus]) (define_code_attr vis3_addsub_ss_insn @@ -8641,8 +8699,63 @@ (match_operand:VASS 2 "register_operand" "<vconstr>")))] "TARGET_VIS3" "<vis3_addsub_ss_insn><vbits>\t%1, %2, %0" + [(set_attr "type" "fga") + (set_attr "v3pipe" "true")]) + +(define_mode_iterator VMMAX [V8QI V4HI V2SI]) +(define_code_iterator vis4_minmax [smin smax]) +(define_code_attr vis4_minmax_insn + [(smin "fpmin") (smax "fpmax")]) +(define_code_attr vis4_minmax_patname + [(smin "min") (smax "max")]) + +(define_insn "<vis4_minmax_patname><mode>3" + [(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>") + (vis4_minmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>") + (match_operand:VMMAX 2 "register_operand" "<vconstr>")))] + "TARGET_VIS4" + "<vis4_minmax_insn><vbits>\t%1, %2, %0" + [(set_attr "type" "fga")]) + +(define_code_iterator vis4_uminmax [umin umax]) +(define_code_attr vis4_uminmax_insn + [(umin "fpminu") (umax "fpmaxu")]) +(define_code_attr vis4_uminmax_patname + [(umin "minu") (umax "maxu")]) + +(define_insn "<vis4_uminmax_patname><mode>3" + [(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>") + (vis4_uminmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>") + (match_operand:VMMAX 2 "register_operand" "<vconstr>")))] + "TARGET_VIS4" + "<vis4_uminmax_insn><vbits>\t%1, %2, %0" [(set_attr "type" "fga")]) +;; The use of vis3_addsub_ss_patname in the VIS4 instruction below is +;; intended. +(define_insn "<vis3_addsub_ss_patname>v8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=e") + (vis3_addsub_ss:V8QI (match_operand:V8QI 1 "register_operand" "e") + (match_operand:V8QI 2 "register_operand" "e")))] + "TARGET_VIS4" + "<vis3_addsub_ss_insn>8\t%1, %2, %0" + [(set_attr "type" "fga")]) + +(define_mode_iterator VAUS [V4HI V8QI]) +(define_code_iterator vis4_addsub_us [us_plus us_minus]) +(define_code_attr vis4_addsub_us_insn + [(us_plus "fpaddus") (us_minus "fpsubus")]) +(define_code_attr vis4_addsub_us_patname + [(us_plus "usadd") (us_minus "ussub")]) + +(define_insn "<vis4_addsub_us_patname><mode>3" + [(set (match_operand:VAUS 0 "register_operand" "=<vconstr>") + (vis4_addsub_us:VAUS (match_operand:VAUS 1 "register_operand" "<vconstr>") + (match_operand:VAUS 2 "register_operand" "<vconstr>")))] + "TARGET_VIS4" + "<vis4_addsub_us_insn><vbits>\t%1, %2, %0" + [(set_attr "type" "fga")]) + (define_insn "fucmp<code>8<P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") @@ -8650,7 +8763,18 @@ UNSPEC_FUCMP))] "TARGET_VIS3" "fucmp<code>8\t%1, %2, %0" - [(set_attr "type" "visl")]) + [(set_attr "type" "visl") + (set_attr "v3pipe" "true")]) + +(define_insn "fpcmpu<code><GCM:gcm_name><P:mode>_vis" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") + (match_operand:GCM 2 "register_operand" "e"))] + UNSPEC_FUCMP))] + "TARGET_VIS4" + "fpcmpu<code><GCM:gcm_name>\t%1, %2, %0" + [(set_attr "type" "visl") + (set_attr "fptype" "double")]) (define_insn "*naddsf3" [(set (match_operand:SF 0 "register_operand" "=f") diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index 25eaa1ae5f3..13d41515f00 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -73,6 +73,10 @@ mvis3 Target Report Mask(VIS3) Use UltraSPARC Visual Instruction Set version 3.0 extensions. +mvis4 +Target Report Mask(VIS4) +Use UltraSPARC Visual Instruction Set version 4.0 extensions. + mcbcond Target Report Mask(CBCOND) Use UltraSPARC Compare-and-Branch extensions. @@ -194,6 +198,9 @@ Enum(sparc_processor_type) String(niagara3) Value(PROCESSOR_NIAGARA3) EnumValue Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4) +EnumValue +Enum(sparc_processor_type) String(niagara7) Value(PROCESSOR_NIAGARA7) + mcmodel= Target RejectNegative Joined Var(sparc_cmodel_string) Use given SPARC-V9 code model. diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h index 51ef73906a8..8b80cc1e56b 100644 --- a/gcc/config/sparc/visintrin.h +++ b/gcc/config/sparc/visintrin.h @@ -704,6 +704,192 @@ __vis_xmulxhi (__i64 __A, __i64 __B) #endif /* __VIS__ >= 0x300 */ +#if __VIS__ >= 0x400 + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpadd8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpadd8 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpadds8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpadds8 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpaddus8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpaddus8 (__A, __B); +} + +extern __inline __v4hi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpaddus16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpaddus16 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpcmple8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpcmple8 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpcmpgt8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpcmpgt8 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpcmpule16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpcmpule16 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpcmpugt16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpcmpugt16 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpcmpule32 (__v2si __A, __v2si __B) +{ + return __builtin_vis_fpcmpule32 (__A, __B); +} + +extern __inline long +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpcmpugt32 (__v2si __A, __v2si __B) +{ + return __builtin_vis_fpcmpugt32 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmax8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpmax8 (__A, __B); +} + +extern __inline __v4hi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmax16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpmax16 (__A, __B); +} + +extern __inline __v2si +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmax32 (__v2si __A, __v2si __B) +{ + return __builtin_vis_fpmax32 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmaxu8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpmaxu8 (__A, __B); +} + +extern __inline __v4hi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmaxu16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpmaxu16 (__A, __B); +} + +extern __inline __v2si +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmaxu32 (__v2si __A, __v2si __B) +{ + return __builtin_vis_fpmaxu32 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmin8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpmin8 (__A, __B); +} + +extern __inline __v4hi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmin16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpmin16 (__A, __B); +} + +extern __inline __v2si +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpmin32 (__v2si __A, __v2si __B) +{ + return __builtin_vis_fpmin32 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpminu8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpminu8 (__A, __B); +} + +extern __inline __v4hi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpminu16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpminu16 (__A, __B); +} + +extern __inline __v2si +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpminu32 (__v2si __A, __v2si __B) +{ + return __builtin_vis_fpminu32 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpsub8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpsub8 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpsubs8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpsubs8 (__A, __B); +} + +extern __inline __v8qi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpsubus8 (__v8qi __A, __v8qi __B) +{ + return __builtin_vis_fpsubus8 (__A, __B); +} + +extern __inline __v4hi +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +__vis_fpsubus16 (__v4hi __A, __v4hi __B) +{ + return __builtin_vis_fpsubus16 (__A, __B); +} + +#endif /* __VIS__ >= 0x400 */ + #endif /* __VIS__ */ #endif /* _VISINTRIN_H_INCLUDED */ diff --git a/gcc/configure b/gcc/configure index 4bcf6d2f07c..f69aa90e8a9 100755 --- a/gcc/configure +++ b/gcc/configure @@ -25209,6 +25209,42 @@ $as_echo "#define HAVE_AS_SPARC4 1" >>confdefs.h fi + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for SPARC5 and VIS 4.0 instructions" >&5 +$as_echo_n "checking assembler for SPARC5 and VIS 4.0 instructions... " >&6; } +if test "${gcc_cv_as_sparc_sparc5+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_sparc_sparc5=no + if test x$gcc_cv_as != x; then + $as_echo '.text + .register %g2, #scratch + .register %g3, #scratch + .align 4 + subxc %g1, %g2, %g3 + fpadd8 %f0, %f2, %f4' > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags -xarch=sparc5 -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + gcc_cv_as_sparc_sparc5=yes + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_sparc5" >&5 +$as_echo "$gcc_cv_as_sparc_sparc5" >&6; } +if test $gcc_cv_as_sparc_sparc5 = yes; then + +$as_echo "#define HAVE_AS_SPARC5_VIS4 1" >>confdefs.h + +fi + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5 $as_echo_n "checking assembler for LEON instructions... " >&6; } if test "${gcc_cv_as_sparc_leon+set}" = set; then : diff --git a/gcc/configure.ac b/gcc/configure.ac index 9e0a2948ea5..0df24af5b87 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3978,6 +3978,18 @@ foo: [AC_DEFINE(HAVE_AS_SPARC4, 1, [Define if your assembler supports SPARC4 instructions.])]) + gcc_GAS_CHECK_FEATURE([SPARC5 and VIS 4.0 instructions], + gcc_cv_as_sparc_sparc5,, + [-xarch=sparc5], + [.text + .register %g2, #scratch + .register %g3, #scratch + .align 4 + subxc %g1, %g2, %g3 + fpadd8 %f0, %f2, %f4],, + [AC_DEFINE(HAVE_AS_SPARC5_VIS4, 1, + [Define if your assembler supports SPARC5 and VIS 4.0 instructions.])]) + gcc_GAS_CHECK_FEATURE([LEON instructions], gcc_cv_as_sparc_leon,, [-Aleon], diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 4e0074be74f..6215b0c0ed2 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,63 @@ +2016-06-21 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-06-17 Jakub Jelinek <jakub@redhat.com> + + * semantics.c (handle_omp_array_sections_1): Don't ICE when + processing_template_decl when checking for bitfields and unions. + Look through REFERENCE_REF_P as base of COMPONENT_REF. + (finish_omp_clauses): Look through REFERENCE_REF_P even for + array sections with COMPONENT_REF bases. + + 2016-06-16 Jakub Jelinek <jakub@redhat.com> + + * parser.c (cp_parser_omp_var_list_no_open): Call + convert_from_reference before cp_parser_postfix_dot_deref_expression. + * semantics.c (finish_omp_clauses): Don't ICE when + processing_template_decl when checking for bitfields and unions. + Look through REFERENCE_REF_P as base of COMPONENT_REF. + + 2016-06-14 Jakub Jelinek <jakub@redhat.com> + + PR c++/71528 + * decl.c (duplicate_decls): For DECL_INITIALIZED_P non-external + olddecl vars, preserve their TREE_READONLY bit. + +2016-06-14 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/70572 + * decl.c (cp_finish_decl): Check do_auto_deduction return value + and return immediately in case of erroneous code. + +2016-06-14 Jakub Jelinek <jakub@redhat.com> + + PR c++/71516 + * decl.c (complete_vars): Handle gracefully type == error_mark_node. + +2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + + PR c/71381 + Backport from trunk r237290: + * parser.c (cp_parser_omp_var_list_no_open) <OMP_CLAUSE__CACHE_>: + Loosen checking. + +2016-06-08 Jakub Jelinek <jakub@redhat.com> + + PR c++/71442 + * pt.c (tsubst_copy): Only set TREE_USED on DECLs. + +2016-06-06 Jakub Jelinek <jakub@redhat.com> + Patrick Palka <ppalka@gcc.gnu.org> + + PR c++/70847 + PR c++/71330 + PR c++/71393 + * cp-gimplify.c (cp_fold_r): Set *walk_subtrees = 0 and return NULL + right after cp_fold call if cp_fold has returned the same stmt + already in some earlier cp_fold_r call. + (cp_fold_function): Add pset automatic variable, pass its address + to cp_walk_tree. + 2016-06-02 Jakub Jelinek <jakub@redhat.com> PR c++/71372 diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index 7fd3b9c15c3..5c815d94fd8 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -939,6 +939,17 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void *data) *stmt_p = stmt = cp_fold (*stmt_p); + if (((hash_set<tree> *) data)->add (stmt)) + { + /* Don't walk subtrees of stmts we've already walked once, otherwise + we can have exponential complexity with e.g. lots of nested + SAVE_EXPRs or TARGET_EXPRs. cp_fold uses a cache and will return + always the same tree, which the first time cp_fold_r has been + called on it had the subtrees walked. */ + *walk_subtrees = 0; + return NULL; + } + code = TREE_CODE (stmt); if (code == OMP_FOR || code == OMP_SIMD || code == OMP_DISTRIBUTE || code == OMP_TASKLOOP || code == CILK_FOR || code == CILK_SIMD @@ -996,7 +1007,8 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void *data) void cp_fold_function (tree fndecl) { - cp_walk_tree (&DECL_SAVED_TREE (fndecl), cp_fold_r, NULL, NULL); + hash_set<tree> pset; + cp_walk_tree (&DECL_SAVED_TREE (fndecl), cp_fold_r, &pset, NULL); } /* Perform any pre-gimplification lowering of C++ front end trees to diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 7eebb721f09..aea92a4eac9 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -2090,6 +2090,14 @@ duplicate_decls (tree newdecl, tree olddecl, bool newdecl_is_friend) if (VAR_P (newdecl)) { DECL_THIS_EXTERN (newdecl) |= DECL_THIS_EXTERN (olddecl); + /* For already initialized vars, TREE_READONLY could have been + cleared in cp_finish_decl, because the var needs runtime + initialization or destruction. Make sure not to set + TREE_READONLY on it again. */ + if (DECL_INITIALIZED_P (olddecl) + && !DECL_EXTERNAL (olddecl) + && !TREE_READONLY (olddecl)) + TREE_READONLY (newdecl) = 0; DECL_INITIALIZED_P (newdecl) |= DECL_INITIALIZED_P (olddecl); DECL_NONTRIVIALLY_INITIALIZED_P (newdecl) |= DECL_NONTRIVIALLY_INITIALIZED_P (olddecl); @@ -6630,6 +6638,13 @@ cp_finish_decl (tree decl, tree init, bool init_const_expr_p, adc_variable_type); if (type == error_mark_node) return; + if (TREE_CODE (type) == FUNCTION_TYPE) + { + error ("initializer for %<decltype(auto) %D%> has function type " + "(did you forget the %<()%> ?)", decl); + TREE_TYPE (decl) = error_mark_node; + return; + } cp_apply_type_quals_to_decl (cp_type_quals (type), decl); } @@ -15008,8 +15023,9 @@ complete_vars (tree type) tree var = iv->decl; tree type = TREE_TYPE (var); - if (TYPE_MAIN_VARIANT (strip_array_types (type)) - == iv->incomplete_type) + if (type != error_mark_node + && (TYPE_MAIN_VARIANT (strip_array_types (type)) + == iv->incomplete_type)) { /* Complete the type of the variable. The VAR_DECL itself will be laid out in expand_expr. */ diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index f626a5ddcf6..48490163418 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -29964,6 +29964,8 @@ cp_parser_omp_var_list_no_open (cp_parser *parser, enum omp_clause_code kind, switch (kind) { case OMP_CLAUSE__CACHE_: + /* The OpenACC cache directive explicitly only allows "array + elements or subarrays". */ if (cp_lexer_peek_token (parser->lexer)->type != CPP_OPEN_SQUARE) { error_at (token->location, "expected %<[%>"); @@ -29980,6 +29982,7 @@ cp_parser_omp_var_list_no_open (cp_parser *parser, enum omp_clause_code kind, = cp_lexer_peek_token (parser->lexer)->location; cp_id_kind idk = CP_ID_KIND_NONE; cp_lexer_consume_token (parser->lexer); + decl = convert_from_reference (decl); decl = cp_parser_postfix_dot_deref_expression (parser, CPP_DOT, decl, false, @@ -30015,25 +30018,6 @@ cp_parser_omp_var_list_no_open (cp_parser *parser, enum omp_clause_code kind, RT_CLOSE_SQUARE)) goto skip_comma; - if (kind == OMP_CLAUSE__CACHE_) - { - if (TREE_CODE (low_bound) != INTEGER_CST - && !TREE_READONLY (low_bound)) - { - error_at (token->location, - "%qD is not a constant", low_bound); - decl = error_mark_node; - } - - if (TREE_CODE (length) != INTEGER_CST - && !TREE_READONLY (length)) - { - error_at (token->location, - "%qD is not a constant", length); - decl = error_mark_node; - } - } - decl = tree_cons (low_bound, length, decl); } break; diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index a5438d8492b..166aef268e5 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -14159,7 +14159,8 @@ tsubst_copy (tree t, tree args, tsubst_flags_t complain, tree in_decl) len = TREE_VEC_LENGTH (expanded); /* Set TREE_USED for the benefit of -Wunused. */ for (int i = 0; i < len; i++) - TREE_USED (TREE_VEC_ELT (expanded, i)) = true; + if (DECL_P (TREE_VEC_ELT (expanded, i))) + TREE_USED (TREE_VEC_ELT (expanded, i)) = true; } if (expanded == error_mark_node) diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index ae409e6cd3e..b6a9cc0a5e7 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -4507,7 +4507,8 @@ handle_omp_array_sections_1 (tree c, tree t, vec<tree> &types, || OMP_CLAUSE_CODE (c) == OMP_CLAUSE_FROM) && !type_dependent_expression_p (t)) { - if (DECL_BIT_FIELD (TREE_OPERAND (t, 1))) + if (TREE_CODE (TREE_OPERAND (t, 1)) == FIELD_DECL + && DECL_BIT_FIELD (TREE_OPERAND (t, 1))) { error_at (OMP_CLAUSE_LOCATION (c), "bit-field %qE in %qs clause", @@ -4516,7 +4517,8 @@ handle_omp_array_sections_1 (tree c, tree t, vec<tree> &types, } while (TREE_CODE (t) == COMPONENT_REF) { - if (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) == UNION_TYPE) + if (TREE_TYPE (TREE_OPERAND (t, 0)) + && TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) == UNION_TYPE) { error_at (OMP_CLAUSE_LOCATION (c), "%qE is a member of a union", t); @@ -4524,6 +4526,8 @@ handle_omp_array_sections_1 (tree c, tree t, vec<tree> &types, } t = TREE_OPERAND (t, 0); } + if (REFERENCE_REF_P (t)) + t = TREE_OPERAND (t, 0); } if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL) { @@ -6584,6 +6588,8 @@ finish_omp_clauses (tree clauses, bool allow_fields, bool declare_simd) { while (TREE_CODE (t) == COMPONENT_REF) t = TREE_OPERAND (t, 0); + if (REFERENCE_REF_P (t)) + t = TREE_OPERAND (t, 0); if (bitmap_bit_p (&map_field_head, DECL_UID (t))) break; if (bitmap_bit_p (&map_head, DECL_UID (t))) @@ -6622,7 +6628,8 @@ finish_omp_clauses (tree clauses, bool allow_fields, bool declare_simd) { if (type_dependent_expression_p (t)) break; - if (DECL_BIT_FIELD (TREE_OPERAND (t, 1))) + if (TREE_CODE (TREE_OPERAND (t, 1)) == FIELD_DECL + && DECL_BIT_FIELD (TREE_OPERAND (t, 1))) { error_at (OMP_CLAUSE_LOCATION (c), "bit-field %qE in %qs clause", @@ -6638,8 +6645,9 @@ finish_omp_clauses (tree clauses, bool allow_fields, bool declare_simd) } while (TREE_CODE (t) == COMPONENT_REF) { - if (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) - == UNION_TYPE) + if (TREE_TYPE (TREE_OPERAND (t, 0)) + && (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) + == UNION_TYPE)) { error_at (OMP_CLAUSE_LOCATION (c), "%qE is a member of a union", t); @@ -6650,6 +6658,8 @@ finish_omp_clauses (tree clauses, bool allow_fields, bool declare_simd) } if (remove) break; + if (REFERENCE_REF_P (t)) + t = TREE_OPERAND (t, 0); if (VAR_P (t) || TREE_CODE (t) == PARM_DECL) { if (bitmap_bit_p (&map_field_head, DECL_UID (t))) diff --git a/gcc/df-problems.c b/gcc/df-problems.c index f7bf3c8e488..1413ed9ab36 100644 --- a/gcc/df-problems.c +++ b/gcc/df-problems.c @@ -3498,13 +3498,13 @@ df_note_bb_compute (unsigned int bb_index, FOR_BB_INSNS_REVERSE (bb, insn) { + if (!INSN_P (insn)) + continue; + df_insn_info *insn_info = DF_INSN_INFO_GET (insn); df_mw_hardreg *mw; int debug_insn; - if (!INSN_P (insn)) - continue; - debug_insn = DEBUG_INSN_P (insn); bitmap_clear (do_not_gen); diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index f00f08c10d5..decae8a54f1 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -962,8 +962,13 @@ complex @code{__float128} type. When these problems are fixed, you would use the following syntax to declare @code{_Complex128} to be a complex @code{__float128} type: +On the PowerPC Linux VSX targets, you can declare complex types using +the corresponding internal complex type, @code{KCmode} for +@code{__float128} type and @code{ICmode} for @code{__ibm128} type: + @smallexample -typedef _Complex float __attribute__((mode(KC))) _Complex128; +typedef _Complex float __attribute__((mode(KC))) _Complex_float128; +typedef _Complex float __attribute__((mode(IC))) _Complex_ibm128; @end smallexample Not all targets support additional floating-point types. @@ -13840,6 +13845,40 @@ The @code{__builtin_ppc_mftb} function always generates one instruction and returns the Time Base Register value as an unsigned long, throwing away the most significant word on 32-bit environments. +Additional built-in functions are available for the 64-bit PowerPC +family of processors, for efficient use of 128-bit floating point +(@code{__float128}) values. + +The following floating-point built-in functions are available with +@code{-mfloat128} and Altivec support. All of them implement the +function that is part of the name. + +@smallexample +__float128 __builtin_fabsq (__float128) +__float128 __builtin_copysignq (__float128, __float128) +@end smallexample + +The following built-in functions are available with @code{-mfloat128} +and Altivec support. + +@table @code +@item __float128 __builtin_infq (void) +Similar to @code{__builtin_inf}, except the return type is @code{__float128}. +@findex __builtin_infq + +@item __float128 __builtin_huge_valq (void) +Similar to @code{__builtin_huge_val}, except the return type is @code{__float128}. +@findex __builtin_huge_valq + +@item __float128 __builtin_nanq (void) +Similar to @code{__builtin_nan}, except the return type is @code{__float128}. +@findex __builtin_nanq + +@item __float128 __builtin_nansq (void) +Similar to @code{__builtin_nans}, except the return type is @code{__float128}. +@findex __builtin_nansq +@end table + The following built-in functions are available for the PowerPC family of processors, starting with ISA 2.06 or later (@option{-mcpu=power7} or @option{-mpopcntd}): @@ -13863,12 +13902,31 @@ The @code{__builtin_divde}, @code{__builtin_divdeo}, 64-bit environment support ISA 2.06 or later. The following built-in functions are available for the PowerPC family -of processors, starting with ISA 3.0 or later (@option{-mcpu=power9} -or @option{-mmodulo}): +of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}): @smallexample long long __builtin_darn (void); long long __builtin_darn_raw (void); int __builtin_darn_32 (void); + +int __builtin_dfp_dtstsfi_lt (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_lt (unsigned int comparison, _Decimal128 value); +int __builtin_dfp_dtstsfi_lt_dd (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_lt_td (unsigned int comparison, _Decimal128 value); + +int __builtin_dfp_dtstsfi_gt (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_gt (unsigned int comparison, _Decimal128 value); +int __builtin_dfp_dtstsfi_gt_dd (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_gt_td (unsigned int comparison, _Decimal128 value); + +int __builtin_dfp_dtstsfi_eq (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_eq (unsigned int comparison, _Decimal128 value); +int __builtin_dfp_dtstsfi_eq_dd (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_eq_td (unsigned int comparison, _Decimal128 value); + +int __builtin_dfp_dtstsfi_ov (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_ov (unsigned int comparison, _Decimal128 value); +int __builtin_dfp_dtstsfi_ov_dd (unsigned int comparison, _Decimal64 value); +int __builtin_dfp_dtstsfi_ov_td (unsigned int comparison, _Decimal128 value); @end smallexample The @code{__builtin_darn} and @code{__builtin_darn_raw} @@ -13879,6 +13937,38 @@ random number. The @code{__builtin_darn_raw} function provides a 64-bit raw random number. The @code{__builtin_darn_32} function provides a 32-bit random number. +The @code{__builtin_dfp_dtstsfi_lt} function returns a non-zero value +if and only if the number of signficant digits of its @code{value} argument +is less than its @code{comparison} argument. The +@code{__builtin_dfp_dtstsfi_lt_dd} and +@code{__builtin_dfp_dtstsfi_lt_td} functions behave similarly, but +require that the type of the @code{value} argument be +@code{__Decimal64} and @code{__Decimal128} respectively. + +The @code{__builtin_dfp_dtstsfi_gt} function returns a non-zero value +if and only if the number of signficant digits of its @code{value} argument +is greater than its @code{comparison} argument. The +@code{__builtin_dfp_dtstsfi_gt_dd} and +@code{__builtin_dfp_dtstsfi_gt_td} functions behave similarly, but +require that the type of the @code{value} argument be +@code{__Decimal64} and @code{__Decimal128} respectively. + +The @code{__builtin_dfp_dtstsfi_eq} function returns a non-zero value +if and only if the number of signficant digits of its @code{value} argument +equals its @code{comparison} argument. The +@code{__builtin_dfp_dtstsfi_eq_dd} and +@code{__builtin_dfp_dtstsfi_eq_td} functions behave similarly, but +require that the type of the @code{value} argument be +@code{__Decimal64} and @code{__Decimal128} respectively. + +The @code{__builtin_dfp_dtstsfi_ov} function returns a non-zero value +if and only if its @code{value} argument has an undefined number of +significant digits, such as when @code{value} is an encoding of @code{NaN}. +The @code{__builtin_dfp_dtstsfi_ov_dd} and +@code{__builtin_dfp_dtstsfi_ov_td} functions behave similarly, but +require that the type of the @code{value} argument be +@code{__Decimal64} and @code{__Decimal128} respectively. + The following built-in functions are available for the PowerPC family of processors when hardware decimal floating point (@option{-mhard-dfp}) is available: @@ -16518,6 +16608,61 @@ vector __int128_t vec_vprtybq (vector __int128_t); vector __uint128_t vec_vprtybd (vector __uint128_t); @end smallexample +The following built-in vector functions are available for the PowerPC family +of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}) +or with @option{-mpower9-vector}: + +@smallexample +__vector unsigned char +vec_absd (__vector unsigned char arg1, __vector unsigned char arg2); +__vector unsigned short +vec_absd (__vector unsigned short arg1, __vector unsigned short arg2); +__vector unsigned int +vec_absd (__vector unsigned int arg1, __vector unsigned int arg2); + +__vector unsigned char +vec_absdb (__vector unsigned char arg1, __vector unsigned char arg2); +__vector unsigned short +vec_absdh (__vector unsigned short arg1, __vector unsigned short arg2); +__vector unsigned int +vec_absdw (__vector unsigned int arg1, __vector unsigned int arg2); + +__vector unsigned char +vec_slv (__vector unsigned char src, __vector unsigned char shift_distance); +__vector unsigned char +vec_srv (__vector unsigned char src, __vector unsigned char shift_distance); +@end smallexample + +The @code{vec_absd}, @code{vec_absdb}, @code{vec_absdh}, and +@code{vec_absdw} built-in functions each computes the absolute +differences of the pairs of vector elements supplied in its two vector +arguments, placing the absolute differences into the corresponding +elements of the vector result. + +The @code{vec_slv} and @code{vec_srv} functions operate on +all of the bytes of their @code{src} and @code{shift_distance} +arguments in parallel. The behavior of the @code{vec_slv} is as if +there existed a temporary array of 17 unsigned characters +@code{slv_array} within which elements 0 through 15 are the same as +the entries in the @code{src} array and element 16 equals 0. The +result returned from the @code{vec_slv} function is a +@code{__vector} of 16 unsigned characters within which element +@code{i} is computed using the C expression +@code{0xff & (*((unsigned short *)(slv_array + i)) << (0x07 & +shift_distance[i]))}, +with this resulting value coerced to the @code{unsigned char} type. +The behavior of the @code{vec_srv} is as if +there existed a temporary array of 17 unsigned characters +@code{srv_array} within which element 0 equals zero and +elements 1 through 16 equal the elements 0 through 15 of +the @code{src} array. The +result returned from the @code{vec_srv} function is a +@code{__vector} of 16 unsigned characters within which element +@code{i} is computed using the C expression +@code{0xff & (*((unsigned short *)(srv_array + i)) >> +(0x07 & shift_distance[i]))}, +with this resulting value coerced to the @code{unsigned char} type. + If the cryptographic instructions are enabled (@option{-mcrypto} or @option{-mcpu=power8}), the following builtins are enabled. @@ -17233,6 +17378,45 @@ int64_t __builtin_vis_xmulx (int64_t, int64_t); int64_t __builtin_vis_xmulxhi (int64_t, int64_t); @end smallexample +When you use the @option{-mvis4} switch, the VIS version 4.0 built-in +functions also become available: + +@smallexample +v8qi __builtin_vis_fpadd8 (v8qi, v8qi); +v8qi __builtin_vis_fpadds8 (v8qi, v8qi); +v8qi __builtin_vis_fpaddus8 (v8qi, v8qi); +v4hi __builtin_vis_fpaddus16 (v4hi, v4hi); + +v8qi __builtin_vis_fpsub8 (v8qi, v8qi); +v8qi __builtin_vis_fpsubs8 (v8qi, v8qi); +v8qi __builtin_vis_fpsubus8 (v8qi, v8qi); +v4hi __builtin_vis_fpsubus16 (v4hi, v4hi); + +long __builtin_vis_fpcmple8 (v8qi, v8qi); +long __builtin_vis_fpcmpgt8 (v8qi, v8qi); +long __builtin_vis_fpcmpule16 (v4hi, v4hi); +long __builtin_vis_fpcmpugt16 (v4hi, v4hi); +long __builtin_vis_fpcmpule32 (v2si, v2si); +long __builtin_vis_fpcmpugt32 (v2si, v2si); + +v8qi __builtin_vis_fpmax8 (v8qi, v8qi); +v4hi __builtin_vis_fpmax16 (v4hi, v4hi); +v2si __builtin_vis_fpmax32 (v2si, v2si); + +v8qi __builtin_vis_fpmaxu8 (v8qi, v8qi); +v4hi __builtin_vis_fpmaxu16 (v4hi, v4hi); +v2si __builtin_vis_fpmaxu32 (v2si, v2si); + + +v8qi __builtin_vis_fpmin8 (v8qi, v8qi); +v4hi __builtin_vis_fpmin16 (v4hi, v4hi); +v2si __builtin_vis_fpmin32 (v2si, v2si); + +v8qi __builtin_vis_fpminu8 (v8qi, v8qi); +v4hi __builtin_vis_fpminu16 (v4hi, v4hi); +v2si __builtin_vis_fpminu32 (v2si, v2si); +@end smallexample + @node SPU Built-in Functions @subsection SPU Built-in Functions diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index cc07cc1335a..9b8b1d66a83 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1241,7 +1241,7 @@ This option is only supported on some targets, including ARC, ARM, i386, M68k, PowerPC, and SPARC@. It is mandatory for ARC@. The @option{--with-cpu-32} and @option{--with-cpu-64} options specify separate default CPUs for 32-bit and 64-bit modes; these options are only supported for i386, -x86-64 and PowerPC. +x86-64, PowerPC, and SPARC@. @item --with-schedule=@var{cpu} @itemx --with-arch=@var{cpu} diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e386f9a7b46..18303b9813c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -999,7 +999,7 @@ See RS/6000 and PowerPC Options. -mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol -msave-toc-indirect -mno-save-toc-indirect @gol -mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol --mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol +-mcrypto -mno-crypto -mhtm -mno-htm -mdirect-move -mno-direct-move @gol -mquad-memory -mno-quad-memory @gol -mquad-memory-atomic -mno-quad-memory-atomic @gol -mcompat-align-parm -mno-compat-align-parm @gol @@ -19947,7 +19947,7 @@ following options: -mpopcntb -mpopcntd -mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol --mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol +-mcrypto -mdirect-move -mhtm -mpower8-fusion -mpower8-vector @gol -mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol -mpower9-fusion -mpower9-vector -mpower9-dform} @@ -20121,6 +20121,14 @@ Generate code that uses (does not use) the instructions to move data between the general purpose registers and the vector/scalar (VSX) registers that were added in version 2.07 of the PowerPC ISA. +@item -mhtm +@itemx -mno-htm +@opindex mhtm +@opindex mno-htm +Enable (disable) the use of the built-in functions that allow direct +access to the Hardware Transactional Memory (HTM) instructions that +were added in version 2.07 of the PowerPC ISA. + @item -mpower8-fusion @itemx -mno-power8-fusion @opindex mpower8-fusion @@ -20197,9 +20205,14 @@ hardware instructions. The VSX instruction set (@option{-mvsx}, @option{-mcpu=power7}, or @option{-mcpu=power8}) must be enabled to use the @option{-mfloat128} -option. The @code{-mfloat128} option only works on PowerPC 64-bit +option. The @option{-mfloat128} option only works on PowerPC 64-bit Linux systems. +If you use the ISA 3.0 instruction set (@option{-mcpu=power9}), the +@option{-mfloat128} option will also enable the generation of ISA 3.0 +IEEE 128-bit floating point instructions. Otherwise, IEEE 128-bit +floating point will be done with software emulation. + @item -mfloat128-hardware @itemx -mno-float128-hardware @opindex mfloat128-hardware @@ -20207,6 +20220,13 @@ Linux systems. Enable/disable using ISA 3.0 hardware instructions to support the @var{__float128} data type. +If you use @option{-mfloat128-hardware}, it will enable the option +@option{-mfloat128} as well. + +If you select ISA 3.0 instructions with @option{-mcpu=power9}, but do +not use either @option{-mfloat128} or @option{-mfloat128-hardware}, +the IEEE 128-bit floating point support will not be enabled. + @item -mmodulo @itemx -mno-modulo @opindex mmodulo @@ -22153,7 +22173,7 @@ for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, -@samp{niagara3} and @samp{niagara4}. +@samp{niagara3}, @samp{niagara4} and @samp{niagara7}. Native Solaris and GNU/Linux toolchains also support the value @samp{native}, which selects the best architecture option for the host processor. @@ -22181,7 +22201,7 @@ f930, f934, sparclite86x tsc701 @item v9 -ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 +ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4, niagara7 @end table By default (unless configured otherwise), GCC generates code for the V7 @@ -22223,7 +22243,9 @@ Sun UltraSPARC T1 chips. With @option{-mcpu=niagara2}, the compiler additionally optimizes it for Sun UltraSPARC T2 chips. With @option{-mcpu=niagara3}, the compiler additionally optimizes it for Sun UltraSPARC T3 chips. With @option{-mcpu=niagara4}, the compiler -additionally optimizes it for Sun UltraSPARC T4 chips. +additionally optimizes it for Sun UltraSPARC T4 chips. With +@option{-mcpu=niagara7}, the compiler additionally optimizes it for +Oracle SPARC M7 chips. @item -mtune=@var{cpu_type} @opindex mtune @@ -22233,12 +22255,13 @@ option @option{-mcpu=@var{cpu_type}} does. The same values for @option{-mcpu=@var{cpu_type}} can be used for @option{-mtune=@var{cpu_type}}, but the only useful values are those -that select a particular CPU implementation. Those are @samp{cypress}, -@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, -@samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701}, -@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, -@samp{niagara3} and @samp{niagara4}. With native Solaris and GNU/Linux -toolchains, @samp{native} can also be used. +that select a particular CPU implementation. Those are +@samp{cypress}, @samp{supersparc}, @samp{hypersparc}, @samp{leon}, +@samp{leon3}, @samp{leon3v7}, @samp{f930}, @samp{f934}, +@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, +@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3}, +@samp{niagara4} and @samp{niagara7}. With native Solaris and +GNU/Linux toolchains, @samp{native} can also be used. @item -mv8plus @itemx -mno-v8plus @@ -22276,6 +22299,16 @@ default is @option{-mvis3} when targeting a cpu that supports such instructions, such as niagara-3 and later. Setting @option{-mvis3} also sets @option{-mvis2} and @option{-mvis}. +@item -mvis4 +@itemx -mno-vis4 +@opindex mvis4 +@opindex mno-vis4 +With @option{-mvis4}, GCC generates code that takes advantage of +version 4.0 of the UltraSPARC Visual Instruction Set extensions. The +default is @option{-mvis4} when targeting a cpu that supports such +instructions, such as niagara-7 and later. Setting @option{-mvis4} +also sets @option{-mvis3}, @option{-mvis2} and @option{-mvis}. + @item -mcbcond @itemx -mno-cbcond @opindex mcbcond diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 536c4004e95..14182489b17 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3214,6 +3214,9 @@ Floating point register if the LFIWZX instruction is enabled or NO_REGS. @item wD Int constant that is the element number of the 64-bit scalar in a vector. +@item wE +Vector constant that can be loaded with the XXSPLTIB instruction. + @item wF Memory operand suitable for power9 fusion load/stores. @@ -3221,9 +3224,12 @@ Memory operand suitable for power9 fusion load/stores. Memory operand suitable for TOC fusion memory references. @item wL -Int constant that is the element number that the MFVSRLD instruction +Int constant that is the element number that the MFVSRLD instruction. targets. +@item wM +Match vector constant with all 1's if the XXLORC instruction is available. + @item wO A memory operand suitable for the ISA 3.0 vector d-form instructions. @@ -3231,6 +3237,9 @@ A memory operand suitable for the ISA 3.0 vector d-form instructions. A memory address that will work with the @code{lq} and @code{stq} instructions. +@item wS +Vector constant that can be loaded with XXSPLTIB & sign extension. + @item h @samp{MQ}, @samp{CTR}, or @samp{LINK} register diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 8b0bd9f5879..016bf921615 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -2194,7 +2194,6 @@ fold_convertible_p (const_tree type, const_tree arg) case REAL_TYPE: case FIXED_POINT_TYPE: - case COMPLEX_TYPE: case VECTOR_TYPE: case VOID_TYPE: return TREE_CODE (type) == TREE_CODE (orig); @@ -7949,6 +7948,8 @@ fold_unary_loc (location_t loc, enum tree_code code, tree type, tree op0) case VIEW_CONVERT_EXPR: if (TREE_CODE (op0) == MEM_REF) { + if (TYPE_ALIGN (TREE_TYPE (op0)) != TYPE_ALIGN (type)) + type = build_aligned_type (type, TYPE_ALIGN (TREE_TYPE (op0))); tem = fold_build2_loc (loc, MEM_REF, type, TREE_OPERAND (op0, 0), TREE_OPERAND (op0, 1)); REF_REVERSE_STORAGE_ORDER (tem) = REF_REVERSE_STORAGE_ORDER (op0); @@ -8581,9 +8582,9 @@ fold_comparison (location_t loc, enum tree_code code, tree type, if ((offset0 == offset1 || (offset0 && offset1 && operand_equal_p (offset0, offset1, 0))) - && (code == EQ_EXPR - || code == NE_EXPR - || (indirect_base0 && DECL_P (base0)) + && (equality_code + || (indirect_base0 + && (DECL_P (base0) || CONSTANT_CLASS_P (base0))) || POINTER_TYPE_OVERFLOW_UNDEFINED)) { @@ -8622,7 +8623,8 @@ fold_comparison (location_t loc, enum tree_code code, tree type, 6.5.6/8 and /9 with respect to the signed ptrdiff_t. */ else if (bitpos0 == bitpos1 && (equality_code - || (indirect_base0 && DECL_P (base0)) + || (indirect_base0 + && (DECL_P (base0) || CONSTANT_CLASS_P (base0))) || POINTER_TYPE_OVERFLOW_UNDEFINED)) { /* By converting to signed sizetype we cover middle-end pointer @@ -10547,11 +10549,15 @@ fold_binary_loc (location_t loc, || TREE_CODE (arg0) == BIT_IOR_EXPR || TREE_CODE (arg0) == BIT_XOR_EXPR) && TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST) - return fold_build2_loc (loc, TREE_CODE (arg0), type, - fold_build2_loc (loc, code, type, - TREE_OPERAND (arg0, 0), arg1), - fold_build2_loc (loc, code, type, - TREE_OPERAND (arg0, 1), arg1)); + { + tree arg00 = fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0)); + tree arg01 = fold_convert_loc (loc, type, TREE_OPERAND (arg0, 1)); + return fold_build2_loc (loc, TREE_CODE (arg0), type, + fold_build2_loc (loc, code, type, + arg00, arg1), + fold_build2_loc (loc, code, type, + arg01, arg1)); + } /* Two consecutive rotates adding up to the some integer multiple of the precision of the type can be ignored. */ @@ -10560,7 +10566,7 @@ fold_binary_loc (location_t loc, && TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST && wi::umod_trunc (wi::add (arg1, TREE_OPERAND (arg0, 1)), prec) == 0) - return TREE_OPERAND (arg0, 0); + return fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0)); return NULL_TREE; diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 5a21c9b5ccc..f49e4234c27 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,97 @@ +2016-07-13 Andre Vehreschild <vehre@gcc.gnu.org> + + Backport from trunk: + PR fortran/71623 + * trans-stmt.c (gfc_trans_allocate): Add code of pre block of typespec + in allocate to parent block. + +2016-07-09 Thomas Koenig <tkoenig@gcc.gnu.org> + + Backport from trunk: + PR fortran/71783 + * frontend-passes.c (create_var): Always allocate a charlen + for character variables. + +2016-07-08 Cesar Philippidis <cesar@codesourcery.com> + + Backport from trunk: + 2016-07-08 Cesar Philippidis <cesar@codesourcery.com> + + * parse.c (matcha): Define. + (decode_oacc_directive): Add spec_only local var and set it. Use + matcha to parse acc directives except for routine and declare. Return + ST_GET_FCN_CHARACTERISTICS if a non-declarative directive could be + matched. + +2016-07-02 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-07-01 Jakub Jelinek <jakub@redhat.com> + + PR fortran/71687 + * f95-lang.c (struct binding_level): Add reversed field. + (clear_binding_level): Adjust initializer. + (getdecls): If reversed is clear, set it and nreverse the names + chain before returning it. + (poplevel): Use getdecls. + * trans-decl.c (gfc_generate_function_code, gfc_process_block_locals): + Use nreverse to pushdecl decls in the declaration order. + + PR fortran/71717 + * trans-openmp.c (gfc_omp_privatize_by_reference): Return false + for GFC_DECL_ASSOCIATE_VAR_P with POINTER_TYPE. + + 2016-06-30 Jakub Jelinek <jakub@redhat.com> + + PR fortran/71704 + * parse.c (matchs, matcho): Move right before decode_omp_directive. + If spec_only, only gfc_match the keyword and if successful, goto + do_spec_only. + (matchds, matchdo): Define. + (decode_omp_directive): Add spec_only local var and set it. + Use matchds or matchdo macros instead of matchs or matcho + for declare target, declare simd, declare reduction and threadprivate + directives. Return ST_GET_FCN_CHARACTERISTICS if a non-declarative + directive could be matched. + (next_statement): For ST_GET_FCN_CHARACTERISTICS restore + gfc_current_locus from old_locus even if there is no label. + + PR fortran/71705 + * trans-openmp.c (gfc_trans_omp_clauses): Set TREE_ADDRESSABLE on + decls in to/from clauses. + +2016-06-29 Cesar Philippidis <cesar@codesourcery.com> + + Back port from trunk + 2016-06-29 Cesar Philippidis <cesar@codesourcery.com> + + * openmp.c (match_oacc_clause_gang): Rename to ... + (match_oacc_clause_gwv): this. Add support for OpenACC worker and + vector clauses. + (gfc_match_omp_clauses): Use match_oacc_clause_gwv for + OMP_CLAUSE_{GANG,WORKER,VECTOR}. Propagate any MATCH_ERRORs for + invalid OMP_CLAUSE_{ASYNC,WAIT,GANG,WORKER,VECTOR} clauses. + (gfc_match_oacc_wait): Propagate MATCH_ERROR for invalid + oacc_expr_lists. Adjust the first and needs_space arguments to + gfc_match_omp_clauses. + +2016-06-27 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/70673 + * frontend-passes.c (realloc_string_callback): Add a call to + gfc_dep_compare_expr. + +2016-06-12 Dominique d'Humieres <dominiq@lps.ens.fr> + + PR fortran/60751 + * io.c (gfc_resolve_dt): Replace GFC_STD_GNU with GFC_STD_LEGACY. + +2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + + PR c/71381 + Backport from trunk r237290: + * openmp.c (gfc_match_oacc_cache): Add comment. + 2016-06-05 Andre Vehreschild <vehre@gcc.gnu.org> PR fortran/69659 diff --git a/gcc/fortran/f95-lang.c b/gcc/fortran/f95-lang.c index b89a291e761..ea9c0ef2d7d 100644 --- a/gcc/fortran/f95-lang.c +++ b/gcc/fortran/f95-lang.c @@ -289,6 +289,9 @@ binding_level { tree blocks; /* The binding level containing this one (the enclosing binding level). */ struct binding_level *level_chain; + /* True if nreverse has been already called on names; if false, names + are ordered from newest declaration to oldest one. */ + bool reversed; }; /* The binding level currently in effect. */ @@ -299,7 +302,7 @@ static GTY(()) struct binding_level *current_binding_level = NULL; static GTY(()) struct binding_level *global_binding_level; /* Binding level structures are initialized by copying this one. */ -static struct binding_level clear_binding_level = { NULL, NULL, NULL }; +static struct binding_level clear_binding_level = { NULL, NULL, NULL, false }; /* Return true if we are in the global binding level. */ @@ -313,6 +316,11 @@ global_bindings_p (void) tree getdecls (void) { + if (!current_binding_level->reversed) + { + current_binding_level->reversed = true; + current_binding_level->names = nreverse (current_binding_level->names); + } return current_binding_level->names; } @@ -350,7 +358,7 @@ poplevel (int keep, int functionbody) binding level that we are about to exit and which is returned by this routine. */ tree block_node = NULL_TREE; - tree decl_chain = current_binding_level->names; + tree decl_chain = getdecls (); tree subblock_chain = current_binding_level->blocks; tree subblock_node; diff --git a/gcc/fortran/frontend-passes.c b/gcc/fortran/frontend-passes.c index 37c42bb5e34..8d993938ee2 100644 --- a/gcc/fortran/frontend-passes.c +++ b/gcc/fortran/frontend-passes.c @@ -175,6 +175,13 @@ realloc_string_callback (gfc_code **c, int *walk_subtrees ATTRIBUTE_UNUSED, if (!gfc_check_dependency (expr1, expr2, true)) return 0; + /* gfc_check_dependency doesn't always pick up identical expressions. + However, eliminating the above sends the compiler into an infinite + loop on valid expressions. Without this check, the gimplifier emits + an ICE for a = a, where a is deferred character length. */ + if (!gfc_dep_compare_expr (expr1, expr2)) + return 0; + current_code = c; inserted_block = NULL; changed_statement = NULL; @@ -658,12 +665,10 @@ create_var (gfc_expr * e, const char *vname) { gfc_expr *length; + symbol->ts.u.cl = gfc_new_charlen (ns, NULL); length = constant_string_length (e); if (length) - { - symbol->ts.u.cl = gfc_new_charlen (ns, NULL); - symbol->ts.u.cl->length = length; - } + symbol->ts.u.cl->length = length; else symbol->attr.allocatable = 1; } diff --git a/gcc/fortran/io.c b/gcc/fortran/io.c index da0e1c5ec49..6a4515d3c1a 100644 --- a/gcc/fortran/io.c +++ b/gcc/fortran/io.c @@ -3007,7 +3007,7 @@ gfc_resolve_dt (gfc_dt *dt, locus *loc) } if (dt->extra_comma - && !gfc_notify_std (GFC_STD_GNU, "Comma before i/o item list at %L", + && !gfc_notify_std (GFC_STD_LEGACY, "Comma before i/o item list at %L", &dt->extra_comma->where)) return false; diff --git a/gcc/fortran/openmp.c b/gcc/fortran/openmp.c index 0dd1a921370..de9a4ad47af 100644 --- a/gcc/fortran/openmp.c +++ b/gcc/fortran/openmp.c @@ -396,43 +396,67 @@ cleanup: } static match -match_oacc_clause_gang (gfc_omp_clauses *cp) +match_oacc_clause_gwv (gfc_omp_clauses *cp, unsigned gwv) { match ret = MATCH_YES; if (gfc_match (" ( ") != MATCH_YES) return MATCH_NO; - /* The gang clause accepts two optional arguments, num and static. - The num argument may either be explicit (num: <val>) or - implicit without (<val> without num:). */ - - while (ret == MATCH_YES) + if (gwv == GOMP_DIM_GANG) { - if (gfc_match (" static :") == MATCH_YES) + /* The gang clause accepts two optional arguments, num and static. + The num argument may either be explicit (num: <val>) or + implicit without (<val> without num:). */ + + while (ret == MATCH_YES) { - if (cp->gang_static) - return MATCH_ERROR; + if (gfc_match (" static :") == MATCH_YES) + { + if (cp->gang_static) + return MATCH_ERROR; + else + cp->gang_static = true; + if (gfc_match_char ('*') == MATCH_YES) + cp->gang_static_expr = NULL; + else if (gfc_match (" %e ", &cp->gang_static_expr) != MATCH_YES) + return MATCH_ERROR; + } else - cp->gang_static = true; - if (gfc_match_char ('*') == MATCH_YES) - cp->gang_static_expr = NULL; - else if (gfc_match (" %e ", &cp->gang_static_expr) != MATCH_YES) - return MATCH_ERROR; - } - else - { - /* This is optional. */ - if (cp->gang_num_expr || gfc_match (" num :") == MATCH_ERROR) - return MATCH_ERROR; - else if (gfc_match (" %e ", &cp->gang_num_expr) != MATCH_YES) - return MATCH_ERROR; + { + if (cp->gang_num_expr) + return MATCH_ERROR; + + /* The 'num' argument is optional. */ + gfc_match (" num :"); + + if (gfc_match (" %e ", &cp->gang_num_expr) != MATCH_YES) + return MATCH_ERROR; + } + + ret = gfc_match (" , "); } + } + else if (gwv == GOMP_DIM_WORKER) + { + /* The 'num' argument is optional. */ + gfc_match (" num :"); - ret = gfc_match (" , "); + if (gfc_match (" %e ", &cp->worker_expr) != MATCH_YES) + return MATCH_ERROR; } + else if (gwv == GOMP_DIM_VECTOR) + { + /* The 'length' argument is optional. */ + gfc_match (" length :"); - return gfc_match (" ) "); + if (gfc_match (" %e ", &cp->vector_expr) != MATCH_YES) + return MATCH_ERROR; + } + else + gfc_fatal_error ("Unexpected OpenACC parallelism."); + + return gfc_match (" )"); } static match @@ -640,17 +664,25 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, uint64_t mask, needs_space = false; first = false; gfc_gobble_whitespace (); + old_loc = gfc_current_locus; if ((mask & OMP_CLAUSE_ASYNC) && !c->async) if (gfc_match ("async") == MATCH_YES) { c->async = true; - needs_space = false; - if (gfc_match (" ( %e )", &c->async_expr) != MATCH_YES) + match m = gfc_match (" ( %e )", &c->async_expr); + if (m == MATCH_ERROR) + { + gfc_current_locus = old_loc; + break; + } + else if (m == MATCH_NO) { - c->async_expr = gfc_get_constant_expr (BT_INTEGER, - gfc_default_integer_kind, - &gfc_current_locus); + c->async_expr + = gfc_get_constant_expr (BT_INTEGER, + gfc_default_integer_kind, + &gfc_current_locus); mpz_set_si (c->async_expr->value.integer, GOMP_ASYNC_NOVAL); + needs_space = true; } continue; } @@ -658,9 +690,13 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, uint64_t mask, if (gfc_match ("gang") == MATCH_YES) { c->gang = true; - if (match_oacc_clause_gang(c) == MATCH_YES) - needs_space = false; - else + match m = match_oacc_clause_gwv (c, GOMP_DIM_GANG); + if (m == MATCH_ERROR) + { + gfc_current_locus = old_loc; + break; + } + else if (m == MATCH_NO) needs_space = true; continue; } @@ -668,10 +704,13 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, uint64_t mask, if (gfc_match ("worker") == MATCH_YES) { c->worker = true; - if (gfc_match (" ( num : %e )", &c->worker_expr) == MATCH_YES - || gfc_match (" ( %e )", &c->worker_expr) == MATCH_YES) - needs_space = false; - else + match m = match_oacc_clause_gwv (c, GOMP_DIM_WORKER); + if (m == MATCH_ERROR) + { + gfc_current_locus = old_loc; + break; + } + else if (m == MATCH_NO) needs_space = true; continue; } @@ -683,10 +722,13 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, uint64_t mask, if (gfc_match ("vector") == MATCH_YES) { c->vector = true; - if (gfc_match (" ( length : %e )", &c->vector_expr) == MATCH_YES - || gfc_match (" ( %e )", &c->vector_expr) == MATCH_YES) - needs_space = false; - else + match m = match_oacc_clause_gwv (c, GOMP_DIM_VECTOR); + if (m == MATCH_ERROR) + { + gfc_current_locus = old_loc; + break; + } + if (m == MATCH_NO) needs_space = true; continue; } @@ -883,10 +925,16 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, uint64_t mask, && gfc_match ("wait") == MATCH_YES) { c->wait = true; - match_oacc_expr_list (" (", &c->wait_list, false); + match m = match_oacc_expr_list (" (", &c->wait_list, false); + if (m == MATCH_ERROR) + { + gfc_current_locus = old_loc; + break; + } + else if (m == MATCH_NO) + needs_space = true; continue; } - old_loc = gfc_current_locus; if ((mask & OMP_CLAUSE_REDUCTION) && gfc_match ("reduction ( ") == MATCH_YES) { @@ -1582,15 +1630,18 @@ gfc_match_oacc_wait (void) { gfc_omp_clauses *c = gfc_get_omp_clauses (); gfc_expr_list *wait_list = NULL, *el; + bool space = true; + match m; - match_oacc_expr_list (" (", &wait_list, true); - gfc_match_omp_clauses (&c, OACC_WAIT_CLAUSES, false, false, true); + m = match_oacc_expr_list (" (", &wait_list, true); + if (m == MATCH_ERROR) + return m; + else if (m == MATCH_YES) + space = false; - if (gfc_match_omp_eos () != MATCH_YES) - { - gfc_error ("Unexpected junk in !$ACC WAIT at %C"); - return MATCH_ERROR; - } + if (gfc_match_omp_clauses (&c, OACC_WAIT_CLAUSES, space, space, true) + == MATCH_ERROR) + return MATCH_ERROR; if (wait_list) for (el = wait_list; el; el = el->next) @@ -1623,6 +1674,10 @@ match gfc_match_oacc_cache (void) { gfc_omp_clauses *c = gfc_get_omp_clauses (); + /* The OpenACC cache directive explicitly only allows "array elements or + subarrays", which we're currently not checking here. Either check this + after the call of gfc_match_omp_variable_list, or add something like a + only_sections variant next to its allow_sections parameter. */ match m = gfc_match_omp_variable_list (" (", &c->lists[OMP_LIST_CACHE], true, NULL, NULL, true); diff --git a/gcc/fortran/parse.c b/gcc/fortran/parse.c index 1081b2e605e..0aa736c7089 100644 --- a/gcc/fortran/parse.c +++ b/gcc/fortran/parse.c @@ -589,21 +589,12 @@ decode_statement (void) return ST_NONE; } -/* Like match, but set a flag simd_matched if keyword matched. */ -#define matchs(keyword, subr, st) \ +/* Like match and if spec_only, goto do_spec_only without actually + matching. */ +#define matcha(keyword, subr, st) \ do { \ - if (match_word_omp_simd (keyword, subr, &old_locus, \ - &simd_matched) == MATCH_YES) \ - return st; \ - else \ - undo_new_statement (); \ - } while (0); - -/* Like match, but don't match anything if not -fopenmp. */ -#define matcho(keyword, subr, st) \ - do { \ - if (!flag_openmp) \ - ; \ + if (spec_only && gfc_match (keyword) == MATCH_YES) \ + goto do_spec_only; \ else if (match_word (keyword, subr, &old_locus) \ == MATCH_YES) \ return st; \ @@ -616,6 +607,7 @@ decode_oacc_directive (void) { locus old_locus; char c; + bool spec_only = false; gfc_enforce_clean_symbol_state (); @@ -630,6 +622,10 @@ decode_oacc_directive (void) return ST_NONE; } + if (gfc_current_state () == COMP_FUNCTION + && gfc_current_block ()->result->ts.kind == -1) + spec_only = true; + gfc_unset_implicit_pure (NULL); old_locus = gfc_current_locus; @@ -643,49 +639,52 @@ decode_oacc_directive (void) switch (c) { case 'a': - match ("atomic", gfc_match_oacc_atomic, ST_OACC_ATOMIC); + matcha ("atomic", gfc_match_oacc_atomic, ST_OACC_ATOMIC); break; case 'c': - match ("cache", gfc_match_oacc_cache, ST_OACC_CACHE); + matcha ("cache", gfc_match_oacc_cache, ST_OACC_CACHE); break; case 'd': - match ("data", gfc_match_oacc_data, ST_OACC_DATA); + matcha ("data", gfc_match_oacc_data, ST_OACC_DATA); match ("declare", gfc_match_oacc_declare, ST_OACC_DECLARE); break; case 'e': - match ("end atomic", gfc_match_omp_eos, ST_OACC_END_ATOMIC); - match ("end data", gfc_match_omp_eos, ST_OACC_END_DATA); - match ("end host_data", gfc_match_omp_eos, ST_OACC_END_HOST_DATA); - match ("end kernels loop", gfc_match_omp_eos, ST_OACC_END_KERNELS_LOOP); - match ("end kernels", gfc_match_omp_eos, ST_OACC_END_KERNELS); - match ("end loop", gfc_match_omp_eos, ST_OACC_END_LOOP); - match ("end parallel loop", gfc_match_omp_eos, ST_OACC_END_PARALLEL_LOOP); - match ("end parallel", gfc_match_omp_eos, ST_OACC_END_PARALLEL); - match ("enter data", gfc_match_oacc_enter_data, ST_OACC_ENTER_DATA); - match ("exit data", gfc_match_oacc_exit_data, ST_OACC_EXIT_DATA); + matcha ("end atomic", gfc_match_omp_eos, ST_OACC_END_ATOMIC); + matcha ("end data", gfc_match_omp_eos, ST_OACC_END_DATA); + matcha ("end host_data", gfc_match_omp_eos, ST_OACC_END_HOST_DATA); + matcha ("end kernels loop", gfc_match_omp_eos, ST_OACC_END_KERNELS_LOOP); + matcha ("end kernels", gfc_match_omp_eos, ST_OACC_END_KERNELS); + matcha ("end loop", gfc_match_omp_eos, ST_OACC_END_LOOP); + matcha ("end parallel loop", gfc_match_omp_eos, + ST_OACC_END_PARALLEL_LOOP); + matcha ("end parallel", gfc_match_omp_eos, ST_OACC_END_PARALLEL); + matcha ("enter data", gfc_match_oacc_enter_data, ST_OACC_ENTER_DATA); + matcha ("exit data", gfc_match_oacc_exit_data, ST_OACC_EXIT_DATA); break; case 'h': - match ("host_data", gfc_match_oacc_host_data, ST_OACC_HOST_DATA); + matcha ("host_data", gfc_match_oacc_host_data, ST_OACC_HOST_DATA); break; case 'p': - match ("parallel loop", gfc_match_oacc_parallel_loop, ST_OACC_PARALLEL_LOOP); - match ("parallel", gfc_match_oacc_parallel, ST_OACC_PARALLEL); + matcha ("parallel loop", gfc_match_oacc_parallel_loop, + ST_OACC_PARALLEL_LOOP); + matcha ("parallel", gfc_match_oacc_parallel, ST_OACC_PARALLEL); break; case 'k': - match ("kernels loop", gfc_match_oacc_kernels_loop, ST_OACC_KERNELS_LOOP); - match ("kernels", gfc_match_oacc_kernels, ST_OACC_KERNELS); + matcha ("kernels loop", gfc_match_oacc_kernels_loop, + ST_OACC_KERNELS_LOOP); + matcha ("kernels", gfc_match_oacc_kernels, ST_OACC_KERNELS); break; case 'l': - match ("loop", gfc_match_oacc_loop, ST_OACC_LOOP); + matcha ("loop", gfc_match_oacc_loop, ST_OACC_LOOP); break; case 'r': match ("routine", gfc_match_oacc_routine, ST_OACC_ROUTINE); break; case 'u': - match ("update", gfc_match_oacc_update, ST_OACC_UPDATE); + matcha ("update", gfc_match_oacc_update, ST_OACC_UPDATE); break; case 'w': - match ("wait", gfc_match_oacc_wait, ST_OACC_WAIT); + matcha ("wait", gfc_match_oacc_wait, ST_OACC_WAIT); break; } @@ -700,14 +699,72 @@ decode_oacc_directive (void) gfc_error_recovery (); return ST_NONE; + + do_spec_only: + reject_statement (); + gfc_clear_error (); + gfc_buffer_error (false); + gfc_current_locus = old_locus; + return ST_GET_FCN_CHARACTERISTICS; } +/* Like match, but set a flag simd_matched if keyword matched + and if spec_only, goto do_spec_only without actually matching. */ +#define matchs(keyword, subr, st) \ + do { \ + if (spec_only && gfc_match (keyword) == MATCH_YES) \ + goto do_spec_only; \ + if (match_word_omp_simd (keyword, subr, &old_locus, \ + &simd_matched) == MATCH_YES) \ + return st; \ + else \ + undo_new_statement (); \ + } while (0); + +/* Like match, but don't match anything if not -fopenmp + and if spec_only, goto do_spec_only without actually matching. */ +#define matcho(keyword, subr, st) \ + do { \ + if (!flag_openmp) \ + ; \ + else if (spec_only && gfc_match (keyword) == MATCH_YES) \ + goto do_spec_only; \ + else if (match_word (keyword, subr, &old_locus) \ + == MATCH_YES) \ + return st; \ + else \ + undo_new_statement (); \ + } while (0); + +/* Like match, but set a flag simd_matched if keyword matched. */ +#define matchds(keyword, subr, st) \ + do { \ + if (match_word_omp_simd (keyword, subr, &old_locus, \ + &simd_matched) == MATCH_YES) \ + return st; \ + else \ + undo_new_statement (); \ + } while (0); + +/* Like match, but don't match anything if not -fopenmp. */ +#define matchdo(keyword, subr, st) \ + do { \ + if (!flag_openmp) \ + ; \ + else if (match_word (keyword, subr, &old_locus) \ + == MATCH_YES) \ + return st; \ + else \ + undo_new_statement (); \ + } while (0); + static gfc_statement decode_omp_directive (void) { locus old_locus; char c; bool simd_matched = false; + bool spec_only = false; gfc_enforce_clean_symbol_state (); @@ -722,6 +779,10 @@ decode_omp_directive (void) return ST_NONE; } + if (gfc_current_state () == COMP_FUNCTION + && gfc_current_block ()->result->ts.kind == -1) + spec_only = true; + gfc_unset_implicit_pure (NULL); old_locus = gfc_current_locus; @@ -750,12 +811,12 @@ decode_omp_directive (void) matcho ("critical", gfc_match_omp_critical, ST_OMP_CRITICAL); break; case 'd': - matchs ("declare reduction", gfc_match_omp_declare_reduction, - ST_OMP_DECLARE_REDUCTION); - matchs ("declare simd", gfc_match_omp_declare_simd, - ST_OMP_DECLARE_SIMD); - matcho ("declare target", gfc_match_omp_declare_target, - ST_OMP_DECLARE_TARGET); + matchds ("declare reduction", gfc_match_omp_declare_reduction, + ST_OMP_DECLARE_REDUCTION); + matchds ("declare simd", gfc_match_omp_declare_simd, + ST_OMP_DECLARE_SIMD); + matchdo ("declare target", gfc_match_omp_declare_target, + ST_OMP_DECLARE_TARGET); matchs ("distribute parallel do simd", gfc_match_omp_distribute_parallel_do_simd, ST_OMP_DISTRIBUTE_PARALLEL_DO_SIMD); @@ -875,8 +936,8 @@ decode_omp_directive (void) matcho ("teams distribute", gfc_match_omp_teams_distribute, ST_OMP_TEAMS_DISTRIBUTE); matcho ("teams", gfc_match_omp_teams, ST_OMP_TEAMS); - matcho ("threadprivate", gfc_match_omp_threadprivate, - ST_OMP_THREADPRIVATE); + matchdo ("threadprivate", gfc_match_omp_threadprivate, + ST_OMP_THREADPRIVATE); break; case 'w': matcho ("workshare", gfc_match_omp_workshare, ST_OMP_WORKSHARE); @@ -899,6 +960,13 @@ decode_omp_directive (void) gfc_error_recovery (); return ST_NONE; + + do_spec_only: + reject_statement (); + gfc_clear_error (); + gfc_buffer_error (false); + gfc_current_locus = old_locus; + return ST_GET_FCN_CHARACTERISTICS; } static gfc_statement @@ -1319,10 +1387,13 @@ next_statement (void) gfc_buffer_error (false); - if (st == ST_GET_FCN_CHARACTERISTICS && gfc_statement_label != NULL) + if (st == ST_GET_FCN_CHARACTERISTICS) { - gfc_free_st_label (gfc_statement_label); - gfc_statement_label = NULL; + if (gfc_statement_label != NULL) + { + gfc_free_st_label (gfc_statement_label); + gfc_statement_label = NULL; + } gfc_current_locus = old_locus; } diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c index d4ea6c8ee68..b45e5e90847 100644 --- a/gcc/fortran/trans-decl.c +++ b/gcc/fortran/trans-decl.c @@ -6276,7 +6276,7 @@ gfc_generate_function_code (gfc_namespace * ns) gfc_finish_block (&cleanup)); /* Add all the decls we created during processing. */ - decl = saved_function_decls; + decl = nreverse (saved_function_decls); while (decl) { tree next; @@ -6468,7 +6468,7 @@ gfc_process_block_locals (gfc_namespace* ns) if (flag_coarray == GFC_FCOARRAY_LIB && has_coarray_vars) generate_coarray_init (ns); - decl = saved_local_decls; + decl = nreverse (saved_local_decls); while (decl) { tree next; diff --git a/gcc/fortran/trans-openmp.c b/gcc/fortran/trans-openmp.c index c2d89eb3eff..b3baeeca573 100644 --- a/gcc/fortran/trans-openmp.c +++ b/gcc/fortran/trans-openmp.c @@ -61,6 +61,7 @@ gfc_omp_privatize_by_reference (const_tree decl) if (GFC_DECL_GET_SCALAR_POINTER (decl) || GFC_DECL_GET_SCALAR_ALLOCATABLE (decl) || GFC_DECL_CRAY_POINTEE (decl) + || GFC_DECL_ASSOCIATE_VAR_P (decl) || VOID_TYPE_P (TREE_TYPE (TREE_TYPE (decl)))) return false; @@ -2180,6 +2181,8 @@ gfc_trans_omp_clauses (stmtblock_t *block, gfc_omp_clauses *clauses, tree decl = gfc_get_symbol_decl (n->sym); if (gfc_omp_privatize_by_reference (decl)) decl = build_fold_indirect_ref (decl); + else if (DECL_P (decl)) + TREE_ADDRESSABLE (decl) = 1; if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl))) { tree type = TREE_TYPE (decl); diff --git a/gcc/fortran/trans-stmt.c b/gcc/fortran/trans-stmt.c index 7d3cf8cae5a..8321eb2f961 100644 --- a/gcc/fortran/trans-stmt.c +++ b/gcc/fortran/trans-stmt.c @@ -5694,9 +5694,11 @@ gfc_trans_allocate (gfc_code * code) tmp = gfc_get_char_type (code->ext.alloc.ts.kind); tmp = TYPE_SIZE_UNIT (tmp); tmp = fold_convert (TREE_TYPE (se_sz.expr), tmp); + gfc_add_block_to_block (&block, &se_sz.pre); expr3_esize = fold_build2_loc (input_location, MULT_EXPR, TREE_TYPE (se_sz.expr), tmp, se_sz.expr); + expr3_esize = gfc_evaluate_now (expr3_esize, &block); } } @@ -5895,6 +5897,7 @@ gfc_trans_allocate (gfc_code * code) source= or mold= expression. */ gfc_init_se (&se_sz, NULL); gfc_conv_expr (&se_sz, code->ext.alloc.ts.u.cl->length); + gfc_add_block_to_block (&block, &se_sz.pre); gfc_add_modify (&block, al_len, fold_convert (TREE_TYPE (al_len), se_sz.expr)); @@ -5979,11 +5982,19 @@ gfc_trans_allocate (gfc_code * code) specified by a type spec for deferred length character arrays or unlimited polymorphic objects without a source= or mold= expression. */ - gfc_init_se (&se_sz, NULL); - gfc_conv_expr (&se_sz, code->ext.alloc.ts.u.cl->length); - gfc_add_modify (&block, al_len, - fold_convert (TREE_TYPE (al_len), - se_sz.expr)); + if (expr3_esize == NULL_TREE || code->ext.alloc.ts.kind != 1) + { + gfc_init_se (&se_sz, NULL); + gfc_conv_expr (&se_sz, code->ext.alloc.ts.u.cl->length); + gfc_add_block_to_block (&block, &se_sz.pre); + gfc_add_modify (&block, al_len, + fold_convert (TREE_TYPE (al_len), + se_sz.expr)); + } + else + gfc_add_modify (&block, al_len, + fold_convert (TREE_TYPE (al_len), + expr3_esize)); } else /* No length information needed, because type to allocate diff --git a/gcc/function.c b/gcc/function.c index f3b9e658bb9..2625ec816df 100644 --- a/gcc/function.c +++ b/gcc/function.c @@ -3325,6 +3325,8 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, set_mem_attributes (parmreg, parm, 1); } + /* We need to preserve an address based on VIRTUAL_STACK_VARS_REGNUM for + the debug info in case it is not legitimate. */ if (GET_MODE (parmreg) != GET_MODE (rtl)) { rtx tempreg = gen_reg_rtx (GET_MODE (rtl)); @@ -3334,7 +3336,8 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, all->last_conversion_insn); emit_move_insn (tempreg, rtl); tempreg = convert_to_mode (GET_MODE (parmreg), tempreg, unsigned_p); - emit_move_insn (parmreg, tempreg); + emit_move_insn (MEM_P (parmreg) ? copy_rtx (parmreg) : parmreg, + tempreg); all->first_conversion_insn = get_insns (); all->last_conversion_insn = get_last_insn (); end_sequence (); @@ -3342,7 +3345,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, did_conversion = true; } else - emit_move_insn (parmreg, rtl); + emit_move_insn (MEM_P (parmreg) ? copy_rtx (parmreg) : parmreg, rtl); rtl = parmreg; diff --git a/gcc/gcc.c b/gcc/gcc.c index 29cec1db509..0d0ffef141b 100644 --- a/gcc/gcc.c +++ b/gcc/gcc.c @@ -7696,12 +7696,14 @@ driver::build_option_suggestions (void) for (unsigned j = 0; e->values[j].arg != NULL; j++) { char *with_arg = concat (opt_text, e->values[j].arg, NULL); - add_misspelling_candidates (m_option_suggestions, with_arg); + add_misspelling_candidates (m_option_suggestions, option, + with_arg); free (with_arg); } } else - add_misspelling_candidates (m_option_suggestions, opt_text); + add_misspelling_candidates (m_option_suggestions, option, + opt_text); break; case OPT_fsanitize_: @@ -7725,7 +7727,8 @@ driver::build_option_suggestions (void) /* Add with_arg and all of its variant spellings e.g. "-fno-sanitize=address" to candidates (albeit without leading dashes). */ - add_misspelling_candidates (m_option_suggestions, with_arg); + add_misspelling_candidates (m_option_suggestions, option, + with_arg); free (with_arg); } } diff --git a/gcc/genmodes.c b/gcc/genmodes.c index 2bfba3ef1b2..788031b7fff 100644 --- a/gcc/genmodes.c +++ b/gcc/genmodes.c @@ -66,6 +66,7 @@ struct mode_data this mode as a component. */ struct mode_data *next_cont; /* Next mode in that list. */ + struct mode_data *complex; /* complex type with mode as component. */ const char *file; /* file and line of definition, */ unsigned int line; /* for error reporting */ unsigned int counter; /* Rank ordering of modes */ @@ -83,7 +84,7 @@ static struct mode_data *void_mode; static const struct mode_data blank_mode = { 0, "<unknown>", MAX_MODE_CLASS, -1U, -1U, -1U, -1U, - 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, "<unknown>", 0, 0, 0, 0, false, 0 }; @@ -472,6 +473,7 @@ make_complex_modes (enum mode_class cl, c = new_mode (cclass, buf, file, line); c->component = m; + m->complex = c; } } @@ -1381,6 +1383,22 @@ emit_mode_wider (void) } static void +emit_mode_complex (void) +{ + int c; + struct mode_data *m; + + print_decl ("unsigned char", "mode_complex", "NUM_MACHINE_MODES"); + + for_all_modes (c, m) + tagged_printf ("%smode", + m->complex ? m->complex->name : void_mode->name, + m->name); + + print_closer (); +} + +static void emit_mode_mask (void) { int c; @@ -1745,6 +1763,7 @@ emit_insn_modes_c (void) emit_mode_size (); emit_mode_nunits (); emit_mode_wider (); + emit_mode_complex (); emit_mode_mask (); emit_mode_inner (); emit_mode_unit_size (); diff --git a/gcc/gimple.c b/gcc/gimple.c index b0e19d515cf..b06e62ce274 100644 --- a/gcc/gimple.c +++ b/gcc/gimple.c @@ -1355,7 +1355,8 @@ gimple_call_same_target_p (const gimple *c1, const gimple *c2) if (gimple_call_internal_p (c1)) return (gimple_call_internal_p (c2) && gimple_call_internal_fn (c1) == gimple_call_internal_fn (c2) - && !gimple_call_internal_unique_p (as_a <const gcall *> (c1))); + && (!gimple_call_internal_unique_p (as_a <const gcall *> (c1)) + || c1 == c2)); else return (gimple_call_fn (c1) == gimple_call_fn (c2) || (gimple_call_fndecl (c1) diff --git a/gcc/gimplify.c b/gcc/gimplify.c index c334e180c44..ea2649ffa90 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -6894,6 +6894,11 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, { while (TREE_CODE (decl) == COMPONENT_REF) decl = TREE_OPERAND (decl, 0); + if (TREE_CODE (decl) == INDIRECT_REF + && DECL_P (TREE_OPERAND (decl, 0)) + && (TREE_CODE (TREE_TYPE (TREE_OPERAND (decl, 0))) + == REFERENCE_TYPE)) + decl = TREE_OPERAND (decl, 0); } if (gimplify_expr (pd, pre_p, NULL, is_gimple_lvalue, fb_lvalue) == GS_ERROR) @@ -6909,9 +6914,11 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, break; } - if (TYPE_SIZE_UNIT (TREE_TYPE (decl)) == NULL - || (TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (decl))) - != INTEGER_CST)) + tree stype = TREE_TYPE (decl); + if (TREE_CODE (stype) == REFERENCE_TYPE) + stype = TREE_TYPE (stype); + if (TYPE_SIZE_UNIT (stype) == NULL + || TREE_CODE (TYPE_SIZE_UNIT (stype)) != INTEGER_CST) { error_at (OMP_CLAUSE_LOCATION (c), "mapping field %qE of variable length " @@ -6951,6 +6958,14 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, base = get_inner_reference (base, &bitsize, &bitpos, &offset, &mode, &unsignedp, &reversep, &volatilep, false); + tree orig_base = base; + if ((TREE_CODE (base) == INDIRECT_REF + || (TREE_CODE (base) == MEM_REF + && integer_zerop (TREE_OPERAND (base, 1)))) + && DECL_P (TREE_OPERAND (base, 0)) + && (TREE_CODE (TREE_TYPE (TREE_OPERAND (base, 0))) + == REFERENCE_TYPE)) + base = TREE_OPERAND (base, 0); gcc_assert (base == decl && (offset == NULL_TREE || TREE_CODE (offset) == INTEGER_CST)); @@ -6964,7 +6979,10 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, tree l = build_omp_clause (OMP_CLAUSE_LOCATION (c), OMP_CLAUSE_MAP); OMP_CLAUSE_SET_MAP_KIND (l, GOMP_MAP_STRUCT); - OMP_CLAUSE_DECL (l) = decl; + if (orig_base != base) + OMP_CLAUSE_DECL (l) = unshare_expr (orig_base); + else + OMP_CLAUSE_DECL (l) = decl; OMP_CLAUSE_SIZE (l) = size_int (1); if (struct_map_to_clause == NULL) struct_map_to_clause = new hash_map<tree, tree>; @@ -7006,6 +7024,18 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, *list_p = l; list_p = &OMP_CLAUSE_CHAIN (l); } + if (orig_base != base && code == OMP_TARGET) + { + tree c2 = build_omp_clause (OMP_CLAUSE_LOCATION (c), + OMP_CLAUSE_MAP); + enum gomp_map_kind mkind + = GOMP_MAP_FIRSTPRIVATE_REFERENCE; + OMP_CLAUSE_SET_MAP_KIND (c2, mkind); + OMP_CLAUSE_DECL (c2) = decl; + OMP_CLAUSE_SIZE (c2) = size_zero_node; + OMP_CLAUSE_CHAIN (c2) = OMP_CLAUSE_CHAIN (l); + OMP_CLAUSE_CHAIN (l) = c2; + } flags = GOVD_MAP | GOVD_EXPLICIT; if (GOMP_MAP_ALWAYS_P (OMP_CLAUSE_MAP_KIND (c)) || ptr) flags |= GOVD_SEEN; @@ -7024,8 +7054,12 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, o1 = 0; if (bitpos) o1 = o1 + bitpos / BITS_PER_UNIT; - for (sc = &OMP_CLAUSE_CHAIN (*osc); - *sc != c; sc = &OMP_CLAUSE_CHAIN (*sc)) + sc = &OMP_CLAUSE_CHAIN (*osc); + if (*sc != c + && (OMP_CLAUSE_MAP_KIND (*sc) + == GOMP_MAP_FIRSTPRIVATE_REFERENCE)) + sc = &OMP_CLAUSE_CHAIN (*sc); + for (; *sc != c; sc = &OMP_CLAUSE_CHAIN (*sc)) if (ptr && sc == prev_list_p) break; else if (TREE_CODE (OMP_CLAUSE_DECL (*sc)) @@ -7061,6 +7095,15 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, &mode, &unsignedp, &reversep, &volatilep, false); + if ((TREE_CODE (base) == INDIRECT_REF + || (TREE_CODE (base) == MEM_REF + && integer_zerop (TREE_OPERAND (base, + 1)))) + && DECL_P (TREE_OPERAND (base, 0)) + && (TREE_CODE (TREE_TYPE (TREE_OPERAND (base, + 0))) + == REFERENCE_TYPE)) + base = TREE_OPERAND (base, 0); if (base != decl) break; if (scp) @@ -8224,7 +8267,13 @@ gimplify_adjust_omp_clauses (gimple_seq *pre_p, gimple_seq body, tree *list_p, case OMP_CLAUSE_VECTOR: case OMP_CLAUSE_AUTO: case OMP_CLAUSE_SEQ: + break; + case OMP_CLAUSE_TILE: + /* We're not yet making use of the information provided by OpenACC + tile clauses. Discard these here, to simplify later middle end + processing. */ + remove = true; break; default: diff --git a/gcc/ipa-chkp.c b/gcc/ipa-chkp.c index 5f5df6483a7..86c48f14f64 100644 --- a/gcc/ipa-chkp.c +++ b/gcc/ipa-chkp.c @@ -207,7 +207,13 @@ chkp_build_instrumented_fndecl (tree fndecl) /* For functions with body versioning will make a copy of arguments. For functions with no body we need to do it here. */ if (!gimple_has_body_p (fndecl)) - DECL_ARGUMENTS (new_decl) = copy_list (DECL_ARGUMENTS (fndecl)); + { + tree arg; + + DECL_ARGUMENTS (new_decl) = copy_list (DECL_ARGUMENTS (fndecl)); + for (arg = DECL_ARGUMENTS (new_decl); arg; arg = DECL_CHAIN (arg)) + DECL_CONTEXT (arg) = new_decl; + } /* We are going to modify attributes list and therefore should make own copy. */ diff --git a/gcc/ipa-inline-analysis.c b/gcc/ipa-inline-analysis.c index 824e5a99203..04b4549533a 100644 --- a/gcc/ipa-inline-analysis.c +++ b/gcc/ipa-inline-analysis.c @@ -2977,6 +2977,18 @@ compute_inline_parameters (struct cgraph_node *node, bool early) node->local.can_change_signature = !e; } } + + /* Functions called by instrumentation thunk can't change signature + because instrumentation thunk modification is not supported. */ + if (node->local.can_change_signature) + for (e = node->callers; e; e = e->next_caller) + if (e->caller->thunk.thunk_p + && e->caller->thunk.add_pointer_bounds_args) + { + node->local.can_change_signature = false; + break; + } + estimate_function_body_sizes (node, early); for (e = node->callees; e; e = e->next_callee) diff --git a/gcc/ipa-inline-transform.c b/gcc/ipa-inline-transform.c index f966fb00ffb..1925bf14416 100644 --- a/gcc/ipa-inline-transform.c +++ b/gcc/ipa-inline-transform.c @@ -334,7 +334,6 @@ inline_call (struct cgraph_edge *e, bool update_original, if (dump_file) fprintf (dump_file, "Dropping flag_strict_aliasing on %s:%i\n", to->name (), to->order); - build_optimization_node (&opts); DECL_FUNCTION_SPECIFIC_OPTIMIZATION (to->decl) = build_optimization_node (&opts); } diff --git a/gcc/machmode.h b/gcc/machmode.h index ef97d83de7e..3dcadd862f2 100644 --- a/gcc/machmode.h +++ b/gcc/machmode.h @@ -269,6 +269,10 @@ extern const unsigned char mode_wider[NUM_MACHINE_MODES]; extern const unsigned char mode_2xwider[NUM_MACHINE_MODES]; #define GET_MODE_2XWIDER_MODE(MODE) ((machine_mode) mode_2xwider[MODE]) +/* Get the complex mode from the component mode. */ +extern const unsigned char mode_complex[NUM_MACHINE_MODES]; +#define GET_MODE_COMPLEX_MODE(MODE) ((machine_mode) mode_complex[MODE]) + /* Return the mode for data of a given size SIZE and mode class CLASS. If LIMIT is nonzero, then don't use modes bigger than MAX_FIXED_MODE_SIZE. The value is BLKmode if no other mode is found. */ diff --git a/gcc/match.pd b/gcc/match.pd index 13734387df0..f1d07dd59fa 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -844,12 +844,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (ne (bit_and:c (bit_not @0) @1) integer_zerop) (if (INTEGRAL_TYPE_P (TREE_TYPE (@1)) && TYPE_PRECISION (TREE_TYPE (@1)) == 1) - (lt @0 @1))) + (if (TYPE_UNSIGNED (TREE_TYPE (@1))) + (lt @0 @1) + (gt @0 @1)))) (simplify (ne (bit_ior:c (bit_not @0) @1) integer_zerop) (if (INTEGRAL_TYPE_P (TREE_TYPE (@1)) && TYPE_PRECISION (TREE_TYPE (@1)) == 1) - (le @0 @1))) + (if (TYPE_UNSIGNED (TREE_TYPE (@1))) + (le @0 @1) + (ge @0 @1)))) /* ~~x -> x */ (simplify diff --git a/gcc/omp-low.c b/gcc/omp-low.c index 4ad26253347..ec2a64e1a93 100644 --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -2186,7 +2186,6 @@ scan_sharing_clauses (tree clauses, omp_context *ctx, case OMP_CLAUSE_GANG: case OMP_CLAUSE_WORKER: case OMP_CLAUSE_VECTOR: - case OMP_CLAUSE_TILE: case OMP_CLAUSE_INDEPENDENT: case OMP_CLAUSE_AUTO: case OMP_CLAUSE_SEQ: @@ -2200,10 +2199,8 @@ scan_sharing_clauses (tree clauses, omp_context *ctx, break; case OMP_CLAUSE_DEVICE_RESIDENT: + case OMP_CLAUSE_TILE: case OMP_CLAUSE__CACHE_: - sorry ("Clause not supported yet"); - break; - default: gcc_unreachable (); } @@ -2360,7 +2357,6 @@ scan_sharing_clauses (tree clauses, omp_context *ctx, case OMP_CLAUSE_GANG: case OMP_CLAUSE_WORKER: case OMP_CLAUSE_VECTOR: - case OMP_CLAUSE_TILE: case OMP_CLAUSE_INDEPENDENT: case OMP_CLAUSE_AUTO: case OMP_CLAUSE_SEQ: @@ -2368,10 +2364,8 @@ scan_sharing_clauses (tree clauses, omp_context *ctx, break; case OMP_CLAUSE_DEVICE_RESIDENT: + case OMP_CLAUSE_TILE: case OMP_CLAUSE__CACHE_: - sorry ("Clause not supported yet"); - break; - default: gcc_unreachable (); } @@ -4481,8 +4475,9 @@ lower_rec_input_clauses (tree clauses, gimple_seq *ilist, gimple_seq *dlist, if (new_var == NULL_TREE) new_var = maybe_lookup_decl_in_outer_ctx (var, ctx); x = builtin_decl_explicit (BUILT_IN_ASSUME_ALIGNED); - x = build_call_expr_loc (clause_loc, x, 2, new_var, - omp_clause_aligned_alignment (c)); + tree alarg = omp_clause_aligned_alignment (c); + alarg = fold_convert_loc (clause_loc, size_type_node, alarg); + x = build_call_expr_loc (clause_loc, x, 2, new_var, alarg); x = fold_convert_loc (clause_loc, TREE_TYPE (new_var), x); x = build2 (MODIFY_EXPR, TREE_TYPE (new_var), new_var, x); gimplify_and_add (x, ilist); @@ -4495,8 +4490,9 @@ lower_rec_input_clauses (tree clauses, gimple_seq *ilist, gimple_seq *dlist, t = maybe_lookup_decl_in_outer_ctx (var, ctx); t = build_fold_addr_expr_loc (clause_loc, t); t2 = builtin_decl_explicit (BUILT_IN_ASSUME_ALIGNED); - t = build_call_expr_loc (clause_loc, t2, 2, t, - omp_clause_aligned_alignment (c)); + tree alarg = omp_clause_aligned_alignment (c); + alarg = fold_convert_loc (clause_loc, size_type_node, alarg); + t = build_call_expr_loc (clause_loc, t2, 2, t, alarg); t = fold_convert_loc (clause_loc, ptype, t); x = create_tmp_var (ptype); t = build2 (MODIFY_EXPR, ptype, x, t); @@ -13356,9 +13352,15 @@ expand_omp_target (struct omp_region *region) make_edge (else_bb, new_bb, EDGE_FALLTHRU); device = tmp_var; + gsi = gsi_last_bb (new_bb); + } + else + { + gsi = gsi_last_bb (new_bb); + device = force_gimple_operand_gsi (&gsi, device, true, NULL_TREE, + true, GSI_SAME_STMT); } - gsi = gsi_last_bb (new_bb); t = gimple_omp_target_data_arg (entry_stmt); if (t == NULL) { diff --git a/gcc/opts-common.c b/gcc/opts-common.c index bb689827227..900c580019e 100644 --- a/gcc/opts-common.c +++ b/gcc/opts-common.c @@ -373,8 +373,9 @@ static const struct option_map option_map[] = to specific options. We want to do the reverse: to find all the ways that a user could validly spell an option. - Given valid OPT_TEXT (with a leading dash), add it and all of its valid - variant spellings to CANDIDATES, each without a leading dash. + Given valid OPT_TEXT (with a leading dash) for OPTION, add it and all + of its valid variant spellings to CANDIDATES, each without a leading + dash. For example, given "-Wabi-tag", the following are added to CANDIDATES: "Wabi-tag" @@ -386,9 +387,11 @@ static const struct option_map option_map[] = void add_misspelling_candidates (auto_vec<char *> *candidates, + const struct cl_option *option, const char *opt_text) { gcc_assert (candidates); + gcc_assert (option); gcc_assert (opt_text); candidates->safe_push (xstrdup (opt_text + 1)); for (unsigned i = 0; i < ARRAY_SIZE (option_map); i++) @@ -397,6 +400,9 @@ add_misspelling_candidates (auto_vec<char *> *candidates, const char *new_prefix = option_map[i].new_prefix; size_t new_prefix_len = strlen (new_prefix); + if (option->cl_reject_negative && option_map[i].negated) + continue; + if (strncmp (opt_text, new_prefix, new_prefix_len) == 0) { char *alternative = concat (opt0 + 1, opt_text + new_prefix_len, diff --git a/gcc/opts.h b/gcc/opts.h index 1b5cf448a29..25d32c1ad49 100644 --- a/gcc/opts.h +++ b/gcc/opts.h @@ -417,6 +417,7 @@ extern const struct sanitizer_opts_s } sanitizer_opts[]; extern void add_misspelling_candidates (auto_vec<char *> *candidates, + const struct cl_option *option, const char *base_option); #endif diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index 29cfa4e361f..73809847fd2 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2016-06-06 Joseph Myers <joseph@codesourcery.com> + + * fr.po: Update. + 2016-05-25 Joseph Myers <joseph@codesourcery.com> * ru.po: Update. diff --git a/gcc/po/fr.po b/gcc/po/fr.po index 372552aafeb..b56d97504d2 100644 --- a/gcc/po/fr.po +++ b/gcc/po/fr.po @@ -122,10 +122,10 @@ # msgid "" msgstr "" -"Project-Id-Version: gcc 6.1-b20160131\n" +"Project-Id-Version: gcc 6.1.0\n" "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n" "POT-Creation-Date: 2016-04-21 15:24+0000\n" -"PO-Revision-Date: 2016-03-17 00:28+0100\n" +"PO-Revision-Date: 2016-06-02 00:10+0200\n" "Last-Translator: Stéphane Aulery <lkppo@free.fr>\n" "Language-Team: French <traduc@traduc.org>\n" "Language: fr\n" @@ -1203,10 +1203,9 @@ msgid "function returns address of local variable" msgstr "cette fonction retourne l'adresse d'une variable locale" #: gimple-ssa-isolate-paths.c:442 gimple-ssa-isolate-paths.c:287 -#, fuzzy, gcc-internal-format -#| msgid "function returns address of local variable" +#, gcc-internal-format msgid "function may return address of local variable" -msgstr "cette fonction retourne l'adresse d'une variable locale" +msgstr "cette fonction peut retourner l'adresse d'une variable locale" #: incpath.c:72 #, c-format @@ -1253,10 +1252,8 @@ msgid "function might be candidate for attribute %<%s%>" msgstr "fonction peut être une candidate pour l'attribut %<%s%>" #: ipa-pure-const.c:188 -#, fuzzy -#| msgid "function might be possible candidate for attribute `noreturn'" msgid "function might be candidate for attribute %<%s%> if it is known to return normally" -msgstr "fonction peut être une possible candidate pour l'attribut « norreturn »" +msgstr "fonction peut être une candidate possible pour l'attribut %<%s%> si elle connue pour returner normallement" #: langhooks.c:373 msgid "At top level:" @@ -1542,16 +1539,12 @@ msgid "function not inlinable" msgstr "fonction ne peut être enligne" #: cif-code.def:60 -#, fuzzy -#| msgid "function cannot be inline" msgid "function body can be overwritten at link time" -msgstr "fonction ne pas pas être enligne" +msgstr "le corps de la fonction peut être remplacé durant l’édition de liaison" #: cif-code.def:64 -#, fuzzy -#| msgid "function not inlinable" msgid "function not inline candidate" -msgstr "fonction ne peut être enligne" +msgstr "la fonction n’est pas une candidate à l'enlignage" #: cif-code.def:68 msgid "--param large-function-growth limit reached" @@ -1610,18 +1603,12 @@ msgid "non-call exception handling mismatch" msgstr "Autoriser le traitement des exceptions" #: cif-code.def:113 -#, fuzzy -#| msgid "" -#| "\n" -#| "Target specific options:\n" msgid "target specific option mismatch" -msgstr "Options spécifiques à la cible:\n" +msgstr "option spécifique de cible incohérente" #: cif-code.def:117 -#, fuzzy -#| msgid "optimization level restored" msgid "optimization level attribute mismatch" -msgstr "niveau d'optimisation restauré" +msgstr "attribut de niveau d’optimisation incohérent" #: cif-code.def:121 msgid "callee refers to comdat-local symbols" @@ -1629,7 +1616,7 @@ msgstr "" #: cif-code.def:125 msgid "function attribute mismatch" -msgstr "" +msgstr "attribut de fonction incohérent" #: cif-code.def:129 #, fuzzy @@ -1650,7 +1637,7 @@ msgstr "erreur fatale : " #. when reporting fatal signal in the compiler. #: diagnostic.def:34 diagnostic.def:50 msgid "internal compiler error: " -msgstr "erreur interne du compilateur: " +msgstr "erreur interne du compilateur : " #. This one is just for counting DK_WARNING promoted to DK_ERROR #. due to -Werror and -Werror=warning. @@ -1660,7 +1647,7 @@ msgstr "erreur : " #: diagnostic.def:36 msgid "sorry, unimplemented: " -msgstr "désolé, pas implanté: " +msgstr "désolé, pas implanté : " #: diagnostic.def:37 msgid "warning: " @@ -1794,10 +1781,9 @@ msgid "Maximal growth due to inlining of large function (in percent)." msgstr "Croissance maximal en raison de l'enlignage d'une grande fonction (en pourcentage)." #: params.def:193 -#, fuzzy, no-c-format -#| msgid "The size of function body to be considered large" +#, no-c-format msgid "The size of translation unit to be considered large." -msgstr "La taille du corps de la fonction est considéré comme étant grande" +msgstr "La taille de l’unité de traduction considérée comme étant grande." #: params.def:197 #, no-c-format @@ -1987,10 +1973,9 @@ msgid "Loops iterating at least selected number of iterations will get loop alig msgstr "" #: params.def:417 -#, fuzzy, no-c-format -#| msgid "The maximum number of instructions when automatically inlining" +#, no-c-format msgid "The maximum number of loop iterations we predict statically." -msgstr "Le nombre maximum d'instructions lorsqu'automatiquement de type enligne" +msgstr "Le nombre maximum d’itérations de boucle à prédire statiquement." #: params.def:430 #, no-c-format @@ -2044,10 +2029,9 @@ msgid "The maximum expansion factor when copying basic blocks." msgstr "" #: params.def:478 -#, fuzzy, no-c-format -#| msgid "The maximum number of insns of an unswitched loop" +#, no-c-format msgid "The maximum number of insns to duplicate when unfactoring computed gotos." -msgstr "Le nombre maximum d'insns d'une boucle sans branchement" +msgstr "Le nombre maximum d'insns à dupliquer lors des supressions de goto." #: params.def:484 #, no-c-format @@ -2055,10 +2039,9 @@ msgid "The maximum length of path considered in cse." msgstr "La longueur maximale des chemins considérés dans cse." #: params.def:488 -#, fuzzy, no-c-format -#| msgid "The maximum number of instructions for the RTL inliner" +#, no-c-format msgid "The maximum instructions CSE process before flushing." -msgstr "Le nombre maximum d'instructions pour la fonction d'enlignage RTL" +msgstr "Le nombre maximum d'instructions de processus CSE avant vidage du buffer." #: params.def:495 #, no-c-format @@ -2133,10 +2116,9 @@ msgid "Target block's relative execution frequency (as a percentage) required to msgstr "" #: params.def:586 params.def:596 -#, fuzzy, no-c-format -#| msgid "The maximum number of incoming edges to consider for crossjumping" +#, no-c-format msgid "The maximum number of blocks in a region to be considered for interblock scheduling." -msgstr "Le nombre maximum de bordures à considérer pour les sauts croisés" +msgstr "Le nombre maximum de blocs dans une région à considérer pour la gestion des interblocages." #: params.def:591 params.def:601 #, fuzzy, no-c-format @@ -2329,10 +2311,9 @@ msgid "size of tiles for loop blocking." msgstr "" #: params.def:842 -#, fuzzy, no-c-format -#| msgid "The maximum number of peelings of a single loop" +#, no-c-format msgid "maximum number of parameters in a SCoP." -msgstr "Le nombre maximum de passes de réduction d'une boucle simple" +msgstr "Le nombre maximum de paramètres dans un scope." #: params.def:849 #, no-c-format @@ -2340,10 +2321,9 @@ msgid "maximum number of basic blocks per function to be analyzed by Graphite." msgstr "" #: params.def:856 -#, fuzzy, no-c-format -#| msgid "The maximum number of peelings of a single loop" +#, no-c-format msgid "maximum number of arrays per scop." -msgstr "Le nombre maximum de passes de réduction d'une boucle simple" +msgstr "Le nombre maximum de tableaux par scope." #: params.def:863 #, no-c-format @@ -2351,10 +2331,9 @@ msgid "minimal number of loops per function to be analyzed by Graphite." msgstr "" #: params.def:868 -#, fuzzy, no-c-format -#| msgid "The maximum number of insns of an unswitched loop" +#, no-c-format msgid "maximum number of isl operations, 0 means unlimited" -msgstr "Le nombre maximum d'insns d'une boucle sans branchement" +msgstr "Le nombre maximum d'opérations isl, 0 pour illimité" #: params.def:874 #, no-c-format @@ -2536,16 +2515,14 @@ msgid "Maximum length of candidate scans for straight-line strength reduction." msgstr "Exécuter un réduction en force des optimisations" #: params.def:1102 -#, fuzzy, no-c-format -#| msgid "Enable stack probing" +#, no-c-format msgid "Enable asan stack protection." -msgstr "Autoriser le sondage de la pile" +msgstr "Autoriser la protection de pile asan" #: params.def:1107 -#, fuzzy, no-c-format -#| msgid "Enable parallel instructions" +#, no-c-format msgid "Enable asan globals protection." -msgstr "Autoriser les instructions parallèles" +msgstr "Autoriser la protection des constantes asan." #: params.def:1112 #, fuzzy, no-c-format diff --git a/gcc/stor-layout.c b/gcc/stor-layout.c index 66b94583b87..05ee996a03b 100644 --- a/gcc/stor-layout.c +++ b/gcc/stor-layout.c @@ -2151,10 +2151,8 @@ layout_type (tree type) case COMPLEX_TYPE: TYPE_UNSIGNED (type) = TYPE_UNSIGNED (TREE_TYPE (type)); SET_TYPE_MODE (type, - mode_for_size (2 * TYPE_PRECISION (TREE_TYPE (type)), - (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE - ? MODE_COMPLEX_FLOAT : MODE_COMPLEX_INT), - 0)); + GET_MODE_COMPLEX_MODE (TYPE_MODE (TREE_TYPE (type)))); + TYPE_SIZE (type) = bitsize_int (GET_MODE_BITSIZE (TYPE_MODE (type))); TYPE_SIZE_UNIT (type) = size_int (GET_MODE_SIZE (TYPE_MODE (type))); break; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fe22ab22511..95a227f2d63 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,676 @@ +2016-07-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/divkc3-1.c: Require p8vector support. + * gcc.target/powerpc/mulkc3-1.c: Likewise. + +2016-07-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/divkc3-1.c: New. + * gcc.target/powerpc/mulkc3-1.c: New. + +2016-07-14 Alan Modra <amodra@gmail.com> + + PR target/71733 + * gcc.target/powerpc/p9-novsx.c: New. + +2016-07-13 Andre Vehreschild <vehre@gcc.gnu.org> + + Backport from trunk: + PR fortran/71623 + * gfortran.dg/deferred_character_17.f90: New test. + +2016-07-13 Ilya Enkovich <ilya.enkovich@intel.com> + + Backport from mainline r238086. + 2016-07-07 Ilya Enkovich <ilya.enkovich@intel.com> + + PR ipa/71624 + * g++.dg/pr71624.C: New test. + +2016-07-12 Michael Meissner <meissner@linux.vnet.ibm.com> + Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-05 Michael Meissner <meissner@linux.vnet.ibm.com> + Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/signbit-1.c: New test. + * gcc.target/powerpc/signbit-2.c: New test. + * gcc.target/powerpc/signbit-3.c: New test. + +2016-07-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71805 + * gcc.target/powerpc/pr71805.c: New test. + +2016-07-12 Segher Boessenkool <segher@kernel.crashing.org> + + Backport from mainline + 2016-07-06 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/70098 + PR target/71763 + * gcc.target/powerpc/pr71763.c: New file. + +2016-07-11 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71758 + * c-c++-common/gomp/pr71758.c: New test. + * gfortran.dg/gomp/pr71758.f90: New test. + + PR tree-optimization/71823 + * gcc.dg/vect/pr71823.c: New test. + +2016-07-11 Yuri Rumyantsev <ysrumyan@gmail.com> + + Backport from mainline r238055. + 2016-07-06 Yuri Rumyantsev <ysrumyan@gmail.com> + + PR tree-optimization/71518 + * gcc.dg/pr71518.c: New test. + +2016-07-09 Thomas Koenig <tkoenig@gcc.gnu.org> + + Backport from trunk: + PR fortran/71783 + * gfortran.dg/dependency_46.f90: New test. + +2016-07-08 Cesar Philippidis <cesar@codesourcery.com> + + Backport from trunk: + 2016-07-08 Cesar Philippidis <cesar@codesourcery.com> + + * gfortran.dg/goacc/pr71704.f90: New test. + +2016-07-08 Martin Liska <mliska@suse.cz> + + Backported from mainline + 2016-07-08 Martin Liska <mliska@suse.cz> + + * gcc.dg/torture/pr71606.c: New test. + +2016-07-08 Jiong Wang <jiong.wang@arm.com> + + Back port from the trunk + 2016-07-08 Jiong Wang <jiong.wang@arm.com> + + * gcc.target/aarch64/simd/vminmaxnm_1.c: New. + +2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk + 2016-07-08 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71806 + * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Add -mfloat128 option. + +2016-07-07 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from the trunk + 2016-07-01 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71720 + * gcc.target/powerpc/pr71720.c: New test. + +2016-07-07 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from mainline r237885 + 2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * gcc.target/powerpc/dfp/dfp.exp: New dejagnu test script. + * gcc.target/powerpc/dfp/dtstsfi-0.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-1.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-10.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-11.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-12.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-13.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-14.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-15.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-16.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-17.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-18.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-19.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-2.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-20.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-21.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-22.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-23.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-24.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-25.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-26.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-27.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-28.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-29.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-3.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-30.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-31.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-32.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-33.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-34.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-35.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-36.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-37.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-38.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-39.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-4.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-40.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-41.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-42.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-43.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-44.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-45.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-46.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-47.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-48.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-49.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-5.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-50.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-51.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-52.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-53.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-54.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-55.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-56.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-57.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-58.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-59.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-6.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-60.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-61.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-62.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-63.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-64.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-65.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-66.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-67.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-68.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-69.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-7.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-70.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-71.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-72.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-73.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-74.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-75.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-76.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-77.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-78.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-79.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-8.c: New test. + * gcc.target/powerpc/dfp/dtstsfi-9.c: New test. + +2016-07-07 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-06-13 Richard Biener <rguenther@suse.de> + + PR middle-end/64516 + * gcc.dg/align-3.c: New testcase. + +2016-07-07 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2016-05-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71264 + * gcc.dg/vect/pr71264.c: New testcase. + + 2016-06-07 Richard Biener <rguenther@suse.de> + + PR middle-end/71423 + * gcc.dg/torture/pr71423.c: New testcase. + + 2016-06-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71521 + * gcc.dg/tree-ssa/vrp101.c: New testcase. + + 2016-06-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71452 + * gcc.dg/torture/pr71452.c: New testcase. + + 2016-06-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/71522 + * gcc.dg/torture/pr71522.c: New testcase. + +2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> + + Backport from mainline + 2016-07-06 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> + + PR target/50739 + * gcc.target/avr/pr50739.c: New test. + +2016-07-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.dg/const-float128-ped.c: Require __float128 effective + target and options. + * gcc.dg/const-float128.c: Likewise. + * gcc.dg/torture/float128-cmp-invalid.c: Require + __float128 and base_quadfloat_support effective targets, and + __float128 options. + * gcc.dg/torture/float128-div-underflow.c: Likewise. + * gcc.dg/torture/float128-extend-nan.c: Likewise. + * gcc.dg/torture/fp-int-convert-float128-timode-2.c: Likewise. + * gcc.dg/torture/fp-int-convert-float128-timode-3.c: Likewise. + * gcc.dg/torture/fp-int-convert-float128-timode.c: Likewise. + * lib/target-supports.exp (check_effective_target___float128): + New. + (add_options_for___float128): New. + (check_effective_target_base_quadword_support): New. + +2016-07-04 Jakub Jelinek <jakub@redhat.com> + + PR c++/71739 + * g++.dg/cpp0x/pr71739.C: New test. + +2016-07-04 Segher Boessenkool <segher@kernel.crashing.org> + + Backport from mainline + 2016-06-27 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/71670 + * gcc.target/powerpc/pr71670.c: New testcase. + +2016-07-02 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-07-01 Jakub Jelinek <jakub@redhat.com> + + PR fortran/71687 + * gfortran.dg/gomp/pr71687.f90: New test. + + 2016-06-30 Jakub Jelinek <jakub@redhat.com> + + PR fortran/71704 + * gfortran.dg/gomp/pr71704.f90: New test. + + PR fortran/71705 + * gfortran.dg/gomp/pr71705.f90: New test. + + 2016-06-29 Jakub Jelinek <jakub@redhat.com> + + PR c/71685 + * gcc.dg/pr71685.c: New test. + + 2016-06-28 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71626 + * gcc.c-torture/execute/pr71626-1.c: New test. + * gcc.c-torture/execute/pr71626-2.c: New test. + + 2016-06-20 Jakub Jelinek <jakub@redhat.com> + + PR target/71559 + * gcc.target/i386/sse2-pr71559.c: New test. + * gcc.target/i386/avx-pr71559.c: New test. + * gcc.target/i386/avx512f-pr71559.c: New test. + +2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from trunk r237659 + 2016-06-21 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * gcc.target/powerpc/darn-0.c: Add dejagnu directives to disable + test if effective-target is not powerpc_p9vector_ok, or if a -mcpu + override other than -mcpu=power9 command-line option is specified, + or if the target operating system is aix. + * gcc.target/powerpc/darn-1.c: Likewise. + * gcc.target/powerpc/darn-2.c: Likewise. + * gcc.target/powerpc/vslv-0.c: Add dejagnu directives to disable + test if effective-target is not powerpc_p9vector_ok or if the + target operating system is aix. + * gcc.target/powerpc/vslv-1.c: Likewise. + * gcc.target/powerpc/vsrv-0.c: Likewise. + * gcc.target/powerpc/vsrv-1.c: Likewise. + +2016-07-01 Peter Bergner <bergner@vnet.ibm.com> + + Backport from trunk + 2016-06-27 Peter Bergner <bergner@vnet.ibm.com> + + PR target/71656 + * gcc.target/powerpc/pr71656-1.c: New test. + * gcc.target/powerpc/pr71656-2.c: New test. + +2016-07-01 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-06-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/abs128-1.c: New. + * gcc.target/powerpc/copysign128-1.c: New. + * gcc.target/powerpc/inf128-1.c: New. + * gcc.target/powerpc/nan128-1.c: New. + + Backport from mainline + 2016-06-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/abs128-1.c: Require VSX. + * gcc.target/powerpc/copysign128-1.c: Likewise. + * gcc.target/powerpc/inf128-1.c: Likewise. + * gcc.target/powerpc/nan128-1.c: Likewise. + +2016-07-01 Peter Bergner <bergner@vnet.ibm.com> + + Backport from trunk + 2016-07-01 Peter Bergner <bergner@vnet.ibm.com> + + PR target/71698 + * gcc.target/powerpc/pr71698.c: New test. + +2016-07-01 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from trunk r236992 + 2016-06-01 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * gcc.target/powerpc/vslv-0.c: New test. + * gcc.target/powerpc/vslv-1.c: New test. + * gcc.target/powerpc/vsrv-0.c: New test. + * gcc.target/powerpc/vsrv-1.c: New test. + +2016-06-30 Kelvin Nilsen <kelvin@gcc.gnu.org> + + Backport from trunk r237390 + 2016-06-13 Kelvin Nilsen <kelvin@gcc.gnu.org> + Backport from trunk r237646 + 2016-06-20 Kelvin Nilsen <kelvin@gcc.gnu.org> + + * gcc.target/powerpc/vadsdu-0.c: New test. + * gcc.target/powerpc/vadsdu-1.c: New test. + * gcc.target/powerpc/vadsdu-2.c: New test. + * gcc.target/powerpc/vadsdu-3.c: New test. + * gcc.target/powerpc/vadsdu-4.c: New test. + * gcc.target/powerpc/vadsdu-5.c: New test. + * gcc.target/powerpc/vadsdub-1.c: New test. + * gcc.target/powerpc/vadsdub-2.c: New test. + * gcc.target/powerpc/vadsduh-1.c: New test. + * gcc.target/powerpc/vadsduh-2.c: New test. + * gcc.target/powerpc/vadsduw-1.c: New test. + * gcc.target/powerpc/vadsduw-2.c: New test. + +2016-06-30 David Malcolm <dmalcolm@redhat.com> + + Backport from trunk r237880. + 2016-06-30 David Malcolm <dmalcolm@redhat.com> + + PR driver/71651 + * gcc.dg/spellcheck-options-12.c: New test case. + +2016-06-30 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71693 + * gcc.c-torture/compile/pr71693.c: New test. + +2016-06-29 Cesar Philippidis <cesar@codesourcery.com> + + Back port from trunk + 2016-06-29 Cesar Philippidis <cesar@codesourcery.com> + + * gfortran.dg/goacc/asyncwait-2.f95: Updated expected diagnostics. + * gfortran.dg/goacc/asyncwait-3.f95: Likewise. + * gfortran.dg/goacc/asyncwait-4.f95: Add test coverage. + +2016-06-27 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/70673 + * gfortran.dg/pr70673.f90: New test. + +2016-06-27 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk + 2016-05-02 Michael Meissner <meissner@linux.vnet.ibm.com> + + * gcc.target/powerpc/float128-complex-1.c: New tests for complex + __float128. + * gcc.target/powerpc/float128-complex-2.c: Likewise. + +2016-06-24 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71647 + * gcc.target/i386/pr71647.c: New test. + +2016-06-22 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.dg/guality/param-5.c: New test. + +2016-06-21 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71588 + * gcc.dg/pr71558.c: New test. + + Backported from mainline + 2016-06-20 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71581 + * gcc.dg/pr71581.c: New test. + + 2016-06-14 Jakub Jelinek <jakub@redhat.com> + + PR c++/71528 + * g++.dg/opt/pr71528.C: New test. + +2016-06-20 Ilya Enkovich <ilya.enkovich@intel.com> + + Backport from mainline r237484. + 2016-06-15 Ilya Enkovich <ilya.enkovich@intel.com> + + PR middle-end/71529 + * gcc.target/i386/pr71529.C: New test. + +2016-06-20 Georg-Johann Lay <avr@gjlay.de> + Pitchumani Sivanupandi <pitchumani.s@atmel.com> + + Backport from 2016-06-20 trunk r237589, r236558. + + PR target/71103 + * gcc.target/avr/pr71103.c: New test. + * gcc.target/avr/torture/pr71103-2.c: New test. + +2016-06-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-06-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + * gcc.target/powerpc/vsx-elemrev-2.c: Change effective target + requirements, and disable for AIX for now. + * gcc.target/powerpc/vsx-elemrev-4.c: Likewise. + +2016-06-16 Jakub Jelinek <jakub@redhat.com> + + PR target/71554 + * gcc.c-torture/execute/pr71554.c: New test. + +2016-06-14 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/70572 + * g++.dg/cpp1y/auto-fn31.C: New. + +2016-06-14 Jakub Jelinek <jakub@redhat.com> + + PR c++/71516 + * g++.dg/init/pr71516.C: New test. + + Backported from mainline + 2016-06-10 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/71494 + * gcc.c-torture/execute/pr71494.c: New test. + + PR c/68657 + * gcc.target/i386/pr68657.c: New test. + + 2016-06-08 Jakub Jelinek <jakub@redhat.com> + + PR c++/71448 + * g++.dg/torture/pr71448.C: New test. + + 2016-06-04 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71405 + * g++.dg/torture/pr71405.C: New test. + +2016-06-13 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/71498 + * c-c++-common/ubsan/bounds-13.c: New test. + +2016-06-13 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/renaming10.ad[sb]: New test. + +2016-06-12 Dominique d'Humieres <dominiq@lps.ens.fr> + + PR target/60751 + * gfortran.dg/comma_IO_extension_1.f90: New test. + * gfortran.dg/comma_IO_extension_2.f90: Likewise. + * gfortran.dg/array_constructor_49.f90: Remove extra comma in WRITE + statement. + * gfortran.dg/graphite/pr38083.f90: Likewise. + * gfortran.dg/guality/pr41558.f90: Likewise. + * gfortran.dg/integer_exponentiation_6.F90: Likewise and add + missing format. + +2016-06-11 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/case_character.adb: New test. + +2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/71373 + Backport from trunk r237291: + 2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + Cesar Philippidis <cesar@codesourcery.com> + + * gcc.dg/goacc/nested-function-1.c: New file. + * gcc.dg/goacc/nested-function-2.c: Likewise. + * gcc.dg/goacc/pr71373.c: Likewise. + * gfortran.dg/goacc/cray-2.f95: Likewise. + * gfortran.dg/goacc/loop-1-2.f95: Likewise. + * gfortran.dg/goacc/loop-3-2.f95: Likewise. + * gfortran.dg/goacc/cray.f95: Update. + * gfortran.dg/goacc/loop-1.f95: Likewise. + * gfortran.dg/goacc/loop-3.f95: Likewise. + * gfortran.dg/goacc/subroutines.f90: Update, and rename to... + * gfortran.dg/goacc/nested-function-1.f90: ... this new file. + + Backport from trunk r237291: + * c-c++-common/goacc/combined-directives.c: XFAIL tree scanning + for OpenACC tile clauses. + * gfortran.dg/goacc/combined-directives.f90: Likewise. + + PR c/71381 + Backport from trunk r237290: + * c-c++-common/goacc/cache-1.c: Update. Move invalid usage tests + to... + * c-c++-common/goacc/cache-2.c: ... this new file. + * gfortran.dg/goacc/cache-1.f95: Move invalid usage tests to... + * gfortran.dg/goacc/cache-2.f95: ... this new file. + * gfortran.dg/goacc/coarray.f95: Update OpenACC cache directive + usage. + * gfortran.dg/goacc/cray.f95: Likewise. + * gfortran.dg/goacc/loop-1.f95: Likewise. + +2016-06-09 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from trunk + 2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com> + + * gcc.target/powerpc/p9-splat-4.c: New test. + + Back port from trunk + 2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/71186 + * gcc.target/powerpc/pr71186.c: New test. + + Back port from trunk + 2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com> + + * gcc.target/powerpc/p9-splat-1.c: New tests for ISA 3.0 word + splat operations and the XXSPLTIB instruction. + * gcc.target/powerpc/p9-splat-2.c: Likewise. + * gcc.target/powerpc/p9-splat-3.c: Likewise. + * gcc.target/powerpc/pr47755.c: Allow vspltisw in addition to + xxlxor to clear a register. + +2016-06-08 Jakub Jelinek <jakub@redhat.com> + + PR c++/71442 + * g++.dg/cpp0x/Wunused-variable-1.C: New test. + +2016-06-08 Eric Botcazou <ebotcazou@adacore.com> + + Backport from mainline + 2016-06-06 Jose E. Marchesi <jose.marchesi@oracle.com> + + * gcc.target/sparc/vis4misc.c: New file. + * gcc.target/sparc/fpcmp.c: Likewise. + * gcc.target/sparc/fpcmpu.c: Likewise. + +2016-06-08 Ilya Verbin <ilya.verbin@intel.com> + + Backport from mainline + 2016-05-25 Ilya Verbin <ilya.verbin@intel.com> + + * gcc.target/i386/avx512f-ceil-vec-1.c: New test. + * gcc.target/i386/avx512f-ceil-vec-2.c: New test. + * gcc.target/i386/avx512f-ceilf-sfix-vec-1.c: New test. + * gcc.target/i386/avx512f-ceilf-sfix-vec-2.c: New test. + * gcc.target/i386/avx512f-ceilf-vec-1.c: New test. + * gcc.target/i386/avx512f-ceilf-vec-2.c: New test. + * gcc.target/i386/avx512f-floor-vec-1.c: New test. + * gcc.target/i386/avx512f-floor-vec-2.c: New test. + * gcc.target/i386/avx512f-floorf-sfix-vec-1.c: New test. + * gcc.target/i386/avx512f-floorf-sfix-vec-2.c: New test. + * gcc.target/i386/avx512f-floorf-vec-1.c: New test. + * gcc.target/i386/avx512f-floorf-vec-2.c: New test. + * gcc.target/i386/avx512f-rint-sfix-vec-1.c: New test. + * gcc.target/i386/avx512f-rint-sfix-vec-2.c: New test. + * gcc.target/i386/avx512f-rintf-sfix-vec-1.c: New test. + * gcc.target/i386/avx512f-rintf-sfix-vec-2.c: New test. + * gcc.target/i386/avx512f-round-sfix-vec-1.c: New test. + * gcc.target/i386/avx512f-round-sfix-vec-2.c: New test. + * gcc.target/i386/avx512f-roundf-sfix-vec-1.c: New test. + * gcc.target/i386/avx512f-roundf-sfix-vec-2.c: New test. + * gcc.target/i386/avx512f-trunc-vec-1.c: New test. + * gcc.target/i386/avx512f-trunc-vec-2.c: New test. + * gcc.target/i386/avx512f-truncf-vec-1.c: New test. + * gcc.target/i386/avx512f-truncf-vec-2.c: New test. + +2016-06-07 Uros Bizjak <ubizjak@gmail.com> + + PR target/71389 + * g++.dg/pr71389.C: New test. + +2016-06-06 Jakub Jelinek <jakub@redhat.com> + Patrick Palka <ppalka@gcc.gnu.org> + + PR c++/70847 + PR c++/71330 + PR c++/71393 + * g++.dg/opt/pr70847.C: New test. + * g++.dg/ubsan/pr70847.C: New test. + * g++.dg/ubsan/pr71393.C: New test. + +2016-06-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/71259 + * gcc.dg/vect/pr71259.c: New test. + 2016-06-05 Andre Vehreschild <vehre@gcc.gnu.org> PR fortran/69659 diff --git a/gcc/testsuite/c-c++-common/goacc/cache-1.c b/gcc/testsuite/c-c++-common/goacc/cache-1.c index 950334102db..1d4759e738c 100644 --- a/gcc/testsuite/c-c++-common/goacc/cache-1.c +++ b/gcc/testsuite/c-c++-common/goacc/cache-1.c @@ -1,3 +1,7 @@ +/* OpenACC cache directive: valid usage. */ +/* For execution testing, this file is "#include"d from + libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c. */ + int main (int argc, char **argv) { @@ -21,57 +25,31 @@ main (int argc, char **argv) int n = 1; const int len = n; -#pragma acc cache /* { dg-error "expected '\\\(' before end of line" } */ - -#pragma acc cache a[0:N] /* { dg-error "expected '\\\(' before 'a'" } */ - /* { dg-bogus "expected end of line before 'a'" "" { xfail c++ } 26 } */ - -#pragma acc cache (a) /* { dg-error "expected '\\\['" } */ - -#pragma acc cache ( /* { dg-error "expected (identifier|unqualified-id) before end of line" } */ - -#pragma acc cache () /* { dg-error "expected (identifier|unqualified-id) before '\\\)' token" } */ - -#pragma acc cache (,) /* { dg-error "expected (identifier|unqualified-id) before '(,|\\\))' token" } */ - -#pragma acc cache (a[0:N] /* { dg-error "expected '\\\)' before end of line" } */ - -#pragma acc cache (a[0:N],) /* { dg-error "expected (identifier|unqualified-id) before '(,|\\\))' token" "" { xfail c } } */ - -#pragma acc cache (a[0:N]) copyin (a[0:N]) /* { dg-error "expected end of line before 'copyin'" } */ - -#pragma acc cache () /* { dg-error "expected (identifier|unqualified-id) before '\\\)' token" } */ - -#pragma acc cache (a[0:N] b[0:N]) /* { dg-error "expected '\\\)' before 'b'" } */ - -#pragma acc cache (a[0:N] b[0:N}) /* { dg-error "expected '\\\)' before 'b'" } */ - /* { dg-bogus "expected end of line before '\\\}' token" "" { xfail c++ } 47 } */ - -#pragma acc cache (a[0:N] /* { dg-error "expected '\\\)' before end of line" } */ - -#pragma acc cache (a[ii]) /* { dg-error "'ii' is not a constant" } */ - -#pragma acc cache (a[idx:n]) /* { dg-error "'n' is not a constant" } */ - -#pragma acc cache (a[0:N]) ( /* { dg-error "expected end of line before '\\(' token" } */ - -#pragma acc cache (a[0:N]) ii /* { dg-error "expected end of line before 'ii'" } */ - -#pragma acc cache (a[0:N] ii) /* { dg-error "expected '\\)' before 'ii'" } */ - + /* Have at it, GCC! */ #pragma acc cache (a[0:N]) - #pragma acc cache (a[0:N], a[0:N]) - #pragma acc cache (a[0:N], b[0:N]) - #pragma acc cache (a[0]) - #pragma acc cache (a[0], a[1], b[0:N]) - +#pragma acc cache (a[i - 5]) +#pragma acc cache (a[i + 5:len]) +#pragma acc cache (a[i + 5:len - 1]) +#pragma acc cache (b[i]) +#pragma acc cache (b[i:len]) +#pragma acc cache (a[ii]) +#pragma acc cache (a[ii:len]) +#pragma acc cache (b[ii - 1]) +#pragma acc cache (b[ii - 1:len]) +#pragma acc cache (b[i - ii + 1]) +#pragma acc cache (b[i + ii - 1:len]) +#pragma acc cache (b[i * ii - 1:len + 1]) +#pragma acc cache (a[idx + 2]) +#pragma acc cache (a[idx:len + 2]) #pragma acc cache (a[idx]) - #pragma acc cache (a[idx:len]) +#pragma acc cache (a[idx + 2:len]) +#pragma acc cache (a[idx + 2 + i:len]) +#pragma acc cache (a[idx + 2 + i + ii:len]) b[ii] = a[ii]; } diff --git a/gcc/testsuite/c-c++-common/goacc/cache-2.c b/gcc/testsuite/c-c++-common/goacc/cache-2.c new file mode 100644 index 00000000000..f7175157915 --- /dev/null +++ b/gcc/testsuite/c-c++-common/goacc/cache-2.c @@ -0,0 +1,57 @@ +/* OpenACC cache directive: invalid usage. */ + +int +main (int argc, char **argv) +{ +#define N 2 + int a[N], b[N]; + int i; + + for (i = 0; i < N; i++) + { + a[i] = 3; + b[i] = 0; + } + +#pragma acc parallel copyin (a[0:N]) copyout (b[0:N]) +{ + int ii; + + for (ii = 0; ii < N; ii++) + { + const int idx = ii; + int n = 1; + const int len = n; + +#pragma acc cache /* { dg-error "expected '\\\(' before end of line" } */ +#pragma acc cache a[0:N] /* { dg-error "expected '\\\(' before 'a'" } */ + /* { dg-bogus "expected end of line before 'a'" "" { xfail c++ } 27 } */ +#pragma acc cache (a) /* { dg-error "expected '\\\['" } */ +#pragma acc cache ( /* { dg-error "expected (identifier|unqualified-id) before end of line" } */ +#pragma acc cache () /* { dg-error "expected (identifier|unqualified-id) before '\\\)' token" } */ +#pragma acc cache (,) /* { dg-error "expected (identifier|unqualified-id) before '(,|\\\))' token" } */ +#pragma acc cache (a[0:N] /* { dg-error "expected '\\\)' before end of line" } */ +#pragma acc cache (a[0:N],) /* { dg-error "expected (identifier|unqualified-id) before '(,|\\\))' token" "" { xfail c } } */ +#pragma acc cache (a[0:N]) copyin (a[0:N]) /* { dg-error "expected end of line before 'copyin'" } */ +#pragma acc cache () /* { dg-error "expected (identifier|unqualified-id) before '\\\)' token" } */ +#pragma acc cache (a[0:N] b[0:N]) /* { dg-error "expected '\\\)' before 'b'" } */ +#pragma acc cache (a[0:N] b[0:N}) /* { dg-error "expected '\\\)' before 'b'" } */ + /* { dg-bogus "expected end of line before '\\\}' token" "" { xfail c++ } 38 } */ +#pragma acc cache (a[0:N] /* { dg-error "expected '\\\)' before end of line" } */ +#pragma acc cache (a[0:N]) ( /* { dg-error "expected end of line before '\\(' token" } */ +#pragma acc cache (a[0:N]) ii /* { dg-error "expected end of line before 'ii'" } */ +#pragma acc cache (a[0:N] ii) /* { dg-error "expected '\\)' before 'ii'" } */ + + b[ii] = a[ii]; + } +} + + + for (i = 0; i < N; i++) + { + if (a[i] != b[i]) + __builtin_abort (); + } + + return 0; +} diff --git a/gcc/testsuite/c-c++-common/goacc/combined-directives.c b/gcc/testsuite/c-c++-common/goacc/combined-directives.c index c2a3c57b48b..3fa800d7bbe 100644 --- a/gcc/testsuite/c-c++-common/goacc/combined-directives.c +++ b/gcc/testsuite/c-c++-common/goacc/combined-directives.c @@ -111,6 +111,7 @@ test () // { dg-final { scan-tree-dump-times "acc loop vector" 2 "gimple" } } // { dg-final { scan-tree-dump-times "acc loop seq" 2 "gimple" } } // { dg-final { scan-tree-dump-times "acc loop auto" 2 "gimple" } } -// { dg-final { scan-tree-dump-times "acc loop tile.2, 3" 2 "gimple" } } +// XFAILed: OpenACC tile clauses are discarded during gimplification. +// { dg-final { scan-tree-dump-times "acc loop tile.2, 3" 2 "gimple" { xfail *-*-* } } } // { dg-final { scan-tree-dump-times "acc loop independent private.i" 2 "gimple" } } // { dg-final { scan-tree-dump-times "private.z" 2 "gimple" } } diff --git a/gcc/testsuite/c-c++-common/gomp/pr71758.c b/gcc/testsuite/c-c++-common/gomp/pr71758.c new file mode 100644 index 00000000000..d3c86972ef5 --- /dev/null +++ b/gcc/testsuite/c-c++-common/gomp/pr71758.c @@ -0,0 +1,10 @@ +/* PR middle-end/71758 */ + +void +foo (int *p) +{ + long long i = 0; + #pragma omp target device (i) + ; + #pragma omp target update device (i) to (p[0]) +} diff --git a/gcc/testsuite/c-c++-common/ubsan/bounds-13.c b/gcc/testsuite/c-c++-common/ubsan/bounds-13.c new file mode 100644 index 00000000000..25b0467ec67 --- /dev/null +++ b/gcc/testsuite/c-c++-common/ubsan/bounds-13.c @@ -0,0 +1,31 @@ +/* PR sanitizer/71498 */ +/* { dg-do run } */ +/* { dg-options "-fsanitize=bounds -Wno-array-bounds" } */ + +struct S { int a[100]; int b, c; } s; + +__attribute__((noinline, noclone)) int +foo (int x) +{ + return s.a[x]; +} + +__attribute__((noinline, noclone)) int +bar (int x) +{ + static int *d = &s.a[99]; + asm volatile ("" : : "r" (&d)); + return s.a[x]; +} + +int +main () +{ + volatile int a = 0; + a += foo (100); + a += bar (100); + return 0; +} + +/* { dg-output "index 100 out of bounds for type 'int \\\[100\\\]'\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*index 100 out of bounds for type 'int \\\[100\\\]'\[^\n\r]*(\n|\r\n|\r)" } */ diff --git a/gcc/testsuite/g++.dg/cpp0x/Wunused-variable-1.C b/gcc/testsuite/g++.dg/cpp0x/Wunused-variable-1.C new file mode 100644 index 00000000000..39592b26a58 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/Wunused-variable-1.C @@ -0,0 +1,37 @@ +// PR c++/71442 +// { dg-do compile { target c++11 } } +// { dg-options "-Wunused-variable" } + +struct C +{ + template<typename... Ts> + int operator()(Ts &&...) + { + return sizeof...(Ts); + } +}; + +int +foo () +{ + C {} (1, 1L, 1LL, 1.0); +} + +template<int N> +void +bar () +{ + char a; // { dg-warning "unused variable" } + short b; // { dg-warning "unused variable" } + int c; // { dg-warning "unused variable" } + long d; // { dg-warning "unused variable" } + long long e; // { dg-warning "unused variable" } + float f; // { dg-warning "unused variable" } + double g; // { dg-warning "unused variable" } +} + +void +baz () +{ + bar <0> (); +} diff --git a/gcc/testsuite/g++.dg/cpp0x/pr71739.C b/gcc/testsuite/g++.dg/cpp0x/pr71739.C new file mode 100644 index 00000000000..b31a580cd0e --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/pr71739.C @@ -0,0 +1,5 @@ +// PR c++/71739 +// { dg-do compile { target c++11 } } + +template <int N> struct alignas(N) A; +template <int N> struct alignas(N) A {}; diff --git a/gcc/testsuite/g++.dg/cpp1y/auto-fn31.C b/gcc/testsuite/g++.dg/cpp1y/auto-fn31.C new file mode 100644 index 00000000000..c99c59571e9 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/auto-fn31.C @@ -0,0 +1,7 @@ +// PR c++/70572 +// { dg-do compile { target c++14 } } + +void foo () +{ + decltype (auto) a = foo; // { dg-error "initializer" } +} diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C index 397b9a89957..6928d6bcbd8 100644 --- a/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx11.C @@ -77,10 +77,10 @@ # error "__cpp_attributes != 200809" #endif -#ifndef __cpp_rvalue_reference -# error "__cpp_rvalue_reference" -#elif __cpp_rvalue_reference != 200610 -# error "__cpp_rvalue_reference != 200610" +#ifndef __cpp_rvalue_references +# error "__cpp_rvalue_references" +#elif __cpp_rvalue_references != 200610 +# error "__cpp_rvalue_references != 200610" #endif #ifndef __cpp_variadic_templates diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C index fa59f90fa89..dc30a9b3cf8 100644 --- a/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx14.C @@ -70,10 +70,10 @@ # error "__cpp_attributes != 200809" #endif -#ifndef __cpp_rvalue_reference -# error "__cpp_rvalue_reference" -#elif __cpp_rvalue_reference != 200610 -# error "__cpp_rvalue_reference != 200610" +#ifndef __cpp_rvalue_references +# error "__cpp_rvalue_references" +#elif __cpp_rvalue_references != 200610 +# error "__cpp_rvalue_references != 200610" #endif #ifndef __cpp_variadic_templates diff --git a/gcc/testsuite/g++.dg/cpp1y/feat-cxx98-neg.C b/gcc/testsuite/g++.dg/cpp1y/feat-cxx98-neg.C index 886b3d3df10..5fbffabd139 100644 --- a/gcc/testsuite/g++.dg/cpp1y/feat-cxx98-neg.C +++ b/gcc/testsuite/g++.dg/cpp1y/feat-cxx98-neg.C @@ -42,8 +42,8 @@ # error "__cpp_attributes" // { dg-error "error" } #endif -#ifndef __cpp_rvalue_reference -# error "__cpp_rvalue_reference" // { dg-error "error" } +#ifndef __cpp_rvalue_references +# error "__cpp_rvalue_references" // { dg-error "error" } #endif #ifndef __cpp_variadic_templates diff --git a/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C b/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C index 74c6f2978df..4a036d48fd9 100644 --- a/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C +++ b/gcc/testsuite/g++.dg/cpp1z/feat-cxx1z.C @@ -58,10 +58,10 @@ # error "__cpp_attributes != 200809" #endif -#ifndef __cpp_rvalue_reference -# error "__cpp_rvalue_reference" -#elif __cpp_rvalue_reference != 200610 -# error "__cpp_rvalue_reference != 200610" +#ifndef __cpp_rvalue_references +# error "__cpp_rvalue_references" +#elif __cpp_rvalue_references != 200610 +# error "__cpp_rvalue_references != 200610" #endif #ifndef __cpp_variadic_templates diff --git a/gcc/testsuite/g++.dg/init/pr71516.C b/gcc/testsuite/g++.dg/init/pr71516.C new file mode 100644 index 00000000000..0b9aec41707 --- /dev/null +++ b/gcc/testsuite/g++.dg/init/pr71516.C @@ -0,0 +1,10 @@ +// PR c++/71516 +// { dg-do compile } + +struct A; // { dg-message "forward declaration of" } +struct B +{ + static A a; +}; +A B::a = A(); // { dg-error "has initializer but incomplete type|invalid use of incomplete type" } +struct A {}; diff --git a/gcc/testsuite/g++.dg/opt/pr70847.C b/gcc/testsuite/g++.dg/opt/pr70847.C new file mode 100644 index 00000000000..2b5435317cb --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/pr70847.C @@ -0,0 +1,11 @@ +// PR c++/70847 +// { dg-do compile } + +struct D { virtual D& f(); }; + +void +g() +{ + D d; + d.f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f(); +} diff --git a/gcc/testsuite/g++.dg/opt/pr71528.C b/gcc/testsuite/g++.dg/opt/pr71528.C new file mode 100644 index 00000000000..bfe06220472 --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/pr71528.C @@ -0,0 +1,23 @@ +// PR c++/71528 +// { dg-do run } +// { dg-options "-O2" } + +extern int &x; +int y; + +int & +foo () +{ + return y; +} + +int &x = foo (); + +int +main () +{ + if (&x != &y) + __builtin_abort (); +} + +extern int &x; diff --git a/gcc/testsuite/g++.dg/pr71389.C b/gcc/testsuite/g++.dg/pr71389.C new file mode 100644 index 00000000000..023abe1755c --- /dev/null +++ b/gcc/testsuite/g++.dg/pr71389.C @@ -0,0 +1,23 @@ +// { dg-do compile { target i?86-*-* x86_64-*-* } } +// { dg-options "-std=c++11 -O3 -march=ivybridge" } + +#include <functional> + +extern int le_s6, le_s9, le_s11; +long foo_v14[16][16]; + +void fn1() { + std::array<std::array<int, 16>, 16> v13; + for (; le_s6;) + for (int k1 = 2; k1 < 4; k1 = k1 + 1) { + for (int n1 = 0; n1 < le_s9; n1 = 8) { + *foo_v14[6] = 20923310; + for (int i2 = n1; i2 < n1 + 8; i2 = i2 + 1) + v13.at(5).at(i2 + 6 - n1) = 306146921; + } + + for (int l2 = 0; l2 < le_s11; l2 = l2 + 1) + *(l2 + v13.at(5).begin()) = 306146921; + } + v13.at(le_s6 - 4); +} diff --git a/gcc/testsuite/g++.dg/pr71624.C b/gcc/testsuite/g++.dg/pr71624.C new file mode 100644 index 00000000000..94a75cd4c41 --- /dev/null +++ b/gcc/testsuite/g++.dg/pr71624.C @@ -0,0 +1,35 @@ +/* PR71624 */ +// { dg-do compile { target i?86-*-* x86_64-*-* } } +/* { dg-options "-fcheck-pointer-bounds -mmpx -O2" } */ + +class c1 +{ +public: + virtual int fn1 () const; + int fn2 (const int *) const; +}; + +class c2 +{ + int fn1 (); + c1 obj; +}; + +int +c1::fn1 () const +{ + return 0; +} + +int +c1::fn2 (const int *) const +{ + return this->fn1 (); +} + +int +c2::fn1 () +{ + return obj.fn2 (0); +} + diff --git a/gcc/testsuite/g++.dg/torture/pr71405.C b/gcc/testsuite/g++.dg/torture/pr71405.C new file mode 100644 index 00000000000..52602437a08 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr71405.C @@ -0,0 +1,22 @@ +// PR tree-optimization/71405 +// { dg-do compile } + +struct C +{ + C () {} + int i; +}; + +void * +operator new (__SIZE_TYPE__ x, void *y) +{ + return y; +} + +int +main () +{ + int a; + new (&a) C; + return a; +} diff --git a/gcc/testsuite/g++.dg/torture/pr71448.C b/gcc/testsuite/g++.dg/torture/pr71448.C new file mode 100644 index 00000000000..ca00ca83b36 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr71448.C @@ -0,0 +1,27 @@ +// PR c++/71448 +// { dg-do compile } +// { dg-additional-options "-std=c++11" } + +static constexpr const char foo[] = "foo"; +static constexpr const char *bar = "bar"; + +static_assert ((foo + 3 - foo) == 3, "check"); +static_assert (foo + 2 != foo, "check"); +static_assert (foo + 2 >= foo, "check"); +static_assert (3 + foo >= foo, "check"); +static_assert (foo <= foo + 2, "check"); +static_assert (foo <= 3 + foo, "check"); +static_assert (foo + 2 > foo, "check"); +static_assert (3 + foo > foo, "check"); +static_assert (foo < 2 + foo, "check"); +static_assert (foo < foo + 3, "check"); +static_assert ((bar + 3 - bar) == 3, "check"); +static_assert (bar + 2 != bar, "check"); +static_assert (2 + bar >= bar, "check"); +static_assert (bar + 3 >= bar, "check"); +static_assert (bar <= bar + 2, "check"); +static_assert (bar <= 3 + bar, "check"); +static_assert (bar + 2 > bar, "check"); +static_assert (3 + bar > bar, "check"); +static_assert (bar < 2 + bar, "check"); +static_assert (bar < bar + 3, "check"); diff --git a/gcc/testsuite/g++.dg/torture/pr71452.C b/gcc/testsuite/g++.dg/torture/pr71452.C new file mode 100644 index 00000000000..3ebe3a176f3 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr71452.C @@ -0,0 +1,10 @@ +// { dg-do run } + +int main() +{ + bool b; + *(char *)&b = 123; + if (*(char *)&b != 123) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/g++.dg/ubsan/pr70847.C b/gcc/testsuite/g++.dg/ubsan/pr70847.C new file mode 100644 index 00000000000..2b5435317cb --- /dev/null +++ b/gcc/testsuite/g++.dg/ubsan/pr70847.C @@ -0,0 +1,11 @@ +// PR c++/70847 +// { dg-do compile } + +struct D { virtual D& f(); }; + +void +g() +{ + D d; + d.f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f(); +} diff --git a/gcc/testsuite/g++.dg/ubsan/pr71393.C b/gcc/testsuite/g++.dg/ubsan/pr71393.C new file mode 100644 index 00000000000..6011e3a8de0 --- /dev/null +++ b/gcc/testsuite/g++.dg/ubsan/pr71393.C @@ -0,0 +1,14 @@ +// PR c++/71393 +// { dg-do compile } +// { dg-options "-fsanitize=undefined" } + +struct B { B &operator << (long); }; +struct A { A (); long a, b, c, d, e, f; }; + +A::A () +{ + B q; + q << 0 << a << 0 << b << 0 << (b / a) << 0 << c << 0 << (c / a) << 0 + << d << 0 << (d / a) << 0 << e << 0 << (e / a) << 0 << f << 0 + << (f / a) << 0; +} diff --git a/gcc/testsuite/gcc.c-torture/compile/pr71693.c b/gcc/testsuite/gcc.c-torture/compile/pr71693.c new file mode 100644 index 00000000000..fc9249c922c --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr71693.c @@ -0,0 +1,10 @@ +/* PR middle-end/71693 */ + +unsigned short v; + +void +foo (int x) +{ + v = ((((unsigned short) (0x0001 | (x & 0x0070) | 0x0100) & 0x00ffU) << 8) + | (((unsigned short) (0x0001 | (x & 0x0070) | 0x0100) >> 8) & 0x00ffU)); +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr71494.c b/gcc/testsuite/gcc.c-torture/execute/pr71494.c new file mode 100644 index 00000000000..f962f2c2e21 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr71494.c @@ -0,0 +1,22 @@ +/* PR middle-end/71494 */ + +int +main () +{ + void *label = &&out; + int i = 0; + void test (void) + { + label = &&out2; + goto *label; + out2:; + i++; + } + goto *label; + out: + i += 2; + test (); + if (i != 3) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr71554.c b/gcc/testsuite/gcc.c-torture/execute/pr71554.c new file mode 100644 index 00000000000..f0cb4bb0778 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr71554.c @@ -0,0 +1,28 @@ +/* PR target/71554 */ + +int v; + +__attribute__ ((noinline, noclone)) void +bar (void) +{ + v++; +} + +__attribute__ ((noinline, noclone)) +void +foo (unsigned int x) +{ + signed int y = ((-__INT_MAX__ - 1) / 2); + signed int r; + if (__builtin_mul_overflow (x, y, &r)) + bar (); +} + +int +main () +{ + foo (2); + if (v) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr71626-1.c b/gcc/testsuite/gcc.c-torture/execute/pr71626-1.c new file mode 100644 index 00000000000..26cfa9650e0 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr71626-1.c @@ -0,0 +1,19 @@ +/* PR middle-end/71626 */ + +typedef __INTPTR_TYPE__ V __attribute__((__vector_size__(sizeof (__INTPTR_TYPE__)))); + +__attribute__((noinline, noclone)) V +foo () +{ + V v = { (__INTPTR_TYPE__) foo }; + return v; +} + +int +main () +{ + V v = foo (); + if (v[0] != (__INTPTR_TYPE__) foo) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr71626-2.c b/gcc/testsuite/gcc.c-torture/execute/pr71626-2.c new file mode 100644 index 00000000000..4a27c54fbf3 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr71626-2.c @@ -0,0 +1,4 @@ +/* PR middle-end/71626 */ +/* { dg-additional-options "-fpic" { target fpic } } */ + +#include "pr71626-1.c" diff --git a/gcc/testsuite/gcc.dg/align-3.c b/gcc/testsuite/gcc.dg/align-3.c new file mode 100644 index 00000000000..5c97d5ac3cc --- /dev/null +++ b/gcc/testsuite/gcc.dg/align-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-expand" } */ + +typedef struct { char a[2]; } __attribute__((__packed__)) TU2; +unsigned short get16_unaligned(const void *p) { + unsigned short v; + *(TU2 *)(void *)(&v) = *(const TU2 *)p; + return v; +} + +/* { dg-final { scan-rtl-dump "MEM\[^\n\r\]*A8\\\]" "expand" } } */ diff --git a/gcc/testsuite/gcc.dg/const-float128-ped.c b/gcc/testsuite/gcc.dg/const-float128-ped.c index 6a6b6223ce2..c1869cc43f3 100644 --- a/gcc/testsuite/gcc.dg/const-float128-ped.c +++ b/gcc/testsuite/gcc.dg/const-float128-ped.c @@ -1,5 +1,7 @@ /* Test 'q' suffix with -pedantic on __float128 type constants. */ -/* { dg-do compile { target ia64-*-* i?86-*-* x86_64-*-* } } */ +/* { dg-do compile } */ +/* { dg-require-effective-target __float128 } */ /* { dg-options "-pedantic" } */ +/* { dg-add-options __float128 } */ __float128 a = 123.456789q; /* { dg-warning "non-standard suffix on floating constant" } */ diff --git a/gcc/testsuite/gcc.dg/const-float128.c b/gcc/testsuite/gcc.dg/const-float128.c index 116e4597b44..15394b483fc 100644 --- a/gcc/testsuite/gcc.dg/const-float128.c +++ b/gcc/testsuite/gcc.dg/const-float128.c @@ -1,6 +1,8 @@ /* Test 'q' and 'Q' suffixes on __float128 type constants. */ -/* { dg-do compile { target ia64-*-* i?86-*-* x86_64-*-* } } */ +/* { dg-do compile } */ +/* { dg-require-effective-target __float128 } */ /* { dg-options "" } */ +/* { dg-add-options __float128 } */ __float128 a = 123.456789q; __float128 b = 123.456789Q; diff --git a/gcc/testsuite/gcc.dg/goacc/nested-function-1.c b/gcc/testsuite/gcc.dg/goacc/nested-function-1.c new file mode 100644 index 00000000000..e17c0e2227f --- /dev/null +++ b/gcc/testsuite/gcc.dg/goacc/nested-function-1.c @@ -0,0 +1,100 @@ +/* Exercise nested function decomposition, gcc/tree-nested.c. */ +/* See gcc/testsuite/gfortran.dg/goacc/nested-function-1.f90 for the Fortran + version. */ + +int main () +{ +#define N 100 + int nonlocal_arg; + int nonlocal_a[N]; + int nonlocal_i; + int nonlocal_j; + + for (int i = 0; i < N; ++i) + nonlocal_a[i] = 5; + nonlocal_arg = 5; + + void local () + { + int local_i; + int local_arg; + int local_a[N]; + int local_j; + + for (int i = 0; i < N; ++i) + local_a[i] = 5; + local_arg = 5; + +#pragma acc kernels loop \ + gang(num:local_arg) worker(local_arg) vector(local_arg) \ + wait async(local_arg) + for (local_i = 0; local_i < N; ++local_i) + { +#pragma acc cache (local_a[local_i:5]) + local_a[local_i] = 100; +#pragma acc loop seq tile(*) + for (local_j = 0; local_j < N; ++local_j) + ; +#pragma acc loop auto independent tile(1) + for (local_j = 0; local_j < N; ++local_j) + ; + } + +#pragma acc kernels loop \ + gang(static:local_arg) worker(local_arg) vector(local_arg) \ + wait(local_arg, local_arg + 1, local_arg + 2) async + for (local_i = 0; local_i < N; ++local_i) + { +#pragma acc cache (local_a[local_i:4]) + local_a[local_i] = 100; +#pragma acc loop seq tile(1) + for (local_j = 0; local_j < N; ++local_j) + ; +#pragma acc loop auto independent tile(*) + for (local_j = 0; local_j < N; ++local_j) + ; + } + } + + void nonlocal () + { + for (int i = 0; i < N; ++i) + nonlocal_a[i] = 5; + nonlocal_arg = 5; + +#pragma acc kernels loop \ + gang(num:nonlocal_arg) worker(nonlocal_arg) vector(nonlocal_arg) \ + wait async(nonlocal_arg) + for (nonlocal_i = 0; nonlocal_i < N; ++nonlocal_i) + { +#pragma acc cache (nonlocal_a[nonlocal_i:3]) + nonlocal_a[nonlocal_i] = 100; +#pragma acc loop seq tile(2) + for (nonlocal_j = 0; nonlocal_j < N; ++nonlocal_j) + ; +#pragma acc loop auto independent tile(3) + for (nonlocal_j = 0; nonlocal_j < N; ++nonlocal_j) + ; + } + +#pragma acc kernels loop \ + gang(static:nonlocal_arg) worker(nonlocal_arg) vector(nonlocal_arg) \ + wait(nonlocal_arg, nonlocal_arg + 1, nonlocal_arg + 2) async + for (nonlocal_i = 0; nonlocal_i < N; ++nonlocal_i) + { +#pragma acc cache (nonlocal_a[nonlocal_i:2]) + nonlocal_a[nonlocal_i] = 100; +#pragma acc loop seq tile(*) + for (nonlocal_j = 0; nonlocal_j < N; ++nonlocal_j) + ; +#pragma acc loop auto independent tile(*) + for (nonlocal_j = 0; nonlocal_j < N; ++nonlocal_j) + ; + } + } + + local (); + nonlocal (); + + return 0; +} diff --git a/gcc/testsuite/gcc.dg/goacc/nested-function-2.c b/gcc/testsuite/gcc.dg/goacc/nested-function-2.c new file mode 100644 index 00000000000..70c9ec8ebfa --- /dev/null +++ b/gcc/testsuite/gcc.dg/goacc/nested-function-2.c @@ -0,0 +1,45 @@ +/* Exercise nested function decomposition, gcc/tree-nested.c. */ + +int +main (void) +{ + int j = 0, k = 6, l = 7, m = 8; + void simple (void) + { + int i; +#pragma acc parallel + { +#pragma acc loop + for (i = 0; i < m; i+= k) + j = (m + i - j) * l; + } + } + void collapse (void) + { + int x, y, z; +#pragma acc parallel + { +#pragma acc loop collapse (3) + for (x = 0; x < k; x++) + for (y = -5; y < l; y++) + for (z = 0; z < m; z++) + j += x + y + z; + } + } + void reduction (void) + { + int x, y, z; +#pragma acc parallel reduction (+:j) + { +#pragma acc loop reduction (+:j) collapse (3) + for (x = 0; x < k; x++) + for (y = -5; y < l; y++) + for (z = 0; z < m; z++) + j += x + y + z; + } + } + simple(); + collapse(); + reduction(); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/goacc/pr71373.c b/gcc/testsuite/gcc.dg/goacc/pr71373.c new file mode 100644 index 00000000000..9381752cc9d --- /dev/null +++ b/gcc/testsuite/gcc.dg/goacc/pr71373.c @@ -0,0 +1,41 @@ +/* Unintentional nested function usage. */ +/* Due to missing right braces '}', the following functions are parsed as + nested functions. This ran into an ICE. */ + +void foo (void) +{ + #pragma acc parallel + { + #pragma acc loop independent + for (int i = 0; i < 16; i++) + ; + // Note right brace '}' commented out here. + //} +} +void bar (void) +{ +} + +// Adding right brace '}' here, to make this compile. +} + + +// ..., and the other way round: + +void BAR (void) +{ +// Note right brace '}' commented out here. +//} + +void FOO (void) +{ + #pragma acc parallel + { + #pragma acc loop independent + for (int i = 0; i < 16; i++) + ; + } +} + +// Adding right brace '}' here, to make this compile. +} diff --git a/gcc/testsuite/gcc.dg/guality/param-5.c b/gcc/testsuite/gcc.dg/guality/param-5.c new file mode 100644 index 00000000000..8ca82ea68e5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/guality/param-5.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-g" } */ +/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */ + +typedef __UINTPTR_TYPE__ uintptr_t; + +typedef struct { uintptr_t pa; uintptr_t pb; } fatp_t + __attribute__ ((aligned (2 * __alignof__ (uintptr_t)))); + +__attribute__((noinline, noclone)) void +clear_stack (void) +{ + char a[128 * 1024 + 128]; + + __builtin_memset (a + 128 * 1024, 0, 128); +} + +__attribute__((noinline, noclone)) void +foo (fatp_t str, int count) +{ + char a[128 * 1024]; + + if (count > 0) + foo (str, count - 1); + clear_stack (); + count--; /* BREAK */ +} + +int +main (void) +{ + fatp_t ptr = { 31415927, 27182818 }; + foo (ptr, 1); + return 0; +} + +/* { dg-final { gdb-test 26 "str.pa" "31415927" } } */ +/* { dg-final { gdb-test 26 "str.pb" "27182818" } } */ diff --git a/gcc/testsuite/gcc.dg/pr71518.c b/gcc/testsuite/gcc.dg/pr71518.c new file mode 100644 index 00000000000..6240ca8f2bf --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr71518.c @@ -0,0 +1,25 @@ +/* PR tree-optimization/71518 */ +/* { dg-options "-O3" } */ + +int a, *b[9], c, d, e; + +static int +fn1 () +{ + for (c = 6; c >= 0; c--) + for (d = 0; d < 2; d++) + { + b[d * 2 + c] = 0; + e = a > 1 ? : 0; + if (e == 2) + return 0; + } + return 0; +} + +int +main () +{ + fn1 (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr71558.c b/gcc/testsuite/gcc.dg/pr71558.c new file mode 100644 index 00000000000..33a648e108c --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr71558.c @@ -0,0 +1,17 @@ +/* PR tree-optimization/71588 */ + +/* strcpy must not be pure, but make sure we don't ICE even when + it is declared incorrectly. */ +char *strcpy (char *, const char *) __attribute__ ((__pure__)); +__SIZE_TYPE__ strlen (const char *); +void *malloc (__SIZE_TYPE__); + +char a[20]; + +char * +foo (void) +{ + __SIZE_TYPE__ b = strlen (a); + char *c = malloc (b); + return strcpy (c, a); +} diff --git a/gcc/testsuite/gcc.dg/pr71581.c b/gcc/testsuite/gcc.dg/pr71581.c new file mode 100644 index 00000000000..d82eb1ed5c9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr71581.c @@ -0,0 +1,24 @@ +/* PR middle-end/71581 */ +/* { dg-do compile } */ +/* { dg-options "-Wuninitialized" } */ + +_Complex float +f1 (void) +{ + float x; + return x; /* { dg-warning "is used uninitialized in this function" } */ +} + +_Complex double +f2 (void) +{ + double x; + return x; /* { dg-warning "is used uninitialized in this function" } */ +} + +_Complex int +f3 (void) +{ + int x; + return x; /* { dg-warning "is used uninitialized in this function" } */ +} diff --git a/gcc/testsuite/gcc.dg/pr71685.c b/gcc/testsuite/gcc.dg/pr71685.c new file mode 100644 index 00000000000..80e5c8f5902 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr71685.c @@ -0,0 +1,6 @@ +/* PR c/71685 */ +/* { dg-do compile } */ +/* { dg-options "-std=gnu11" } */ + +extern struct S v, s; +struct S { int t; int p[]; } v = { 4, 0 }; diff --git a/gcc/testsuite/gcc.dg/spellcheck-options-12.c b/gcc/testsuite/gcc.dg/spellcheck-options-12.c new file mode 100644 index 00000000000..b5e65e54a39 --- /dev/null +++ b/gcc/testsuite/gcc.dg/spellcheck-options-12.c @@ -0,0 +1,7 @@ +/* Verify that we don't include -Wno- variants for options marked + with RejectNegative when considering hints for misspelled options + (PR driver/71651). */ + +/* { dg-do compile } */ +/* { dg-options "-fno-stack-protector-explicit" } */ +/* { dg-error "unrecognized command line option .-fno-stack-protector-explicit.; did you mean .-fstack-protector-explicit.." "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.dg/torture/float128-cmp-invalid.c b/gcc/testsuite/gcc.dg/torture/float128-cmp-invalid.c index 9d37ba25b6d..129ceeef6ff 100644 --- a/gcc/testsuite/gcc.dg/torture/float128-cmp-invalid.c +++ b/gcc/testsuite/gcc.dg/torture/float128-cmp-invalid.c @@ -1,7 +1,10 @@ /* Test for "invalid" exceptions from __float128 comparisons. */ -/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */ +/* { dg-do run } */ /* { dg-options "" } */ +/* { dg-require-effective-target __float128 } */ +/* { dg-require-effective-target base_quadfloat_support } */ /* { dg-require-effective-target fenv_exceptions } */ +/* { dg-add-options __float128 } */ #include <fenv.h> #include <stdlib.h> diff --git a/gcc/testsuite/gcc.dg/torture/float128-div-underflow.c b/gcc/testsuite/gcc.dg/torture/float128-div-underflow.c index f721e562b8a..dc284dec6dc 100644 --- a/gcc/testsuite/gcc.dg/torture/float128-div-underflow.c +++ b/gcc/testsuite/gcc.dg/torture/float128-div-underflow.c @@ -1,7 +1,10 @@ /* Test for spurious underflow from __float128 division. */ -/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */ +/* { dg-do run } */ /* { dg-options "" } */ +/* { dg-require-effective-target __float128 } */ +/* { dg-require-effective-target base_quadfloat_support } */ /* { dg-require-effective-target fenv_exceptions } */ +/* { dg-add-options __float128 } */ #include <fenv.h> #include <stdlib.h> diff --git a/gcc/testsuite/gcc.dg/torture/float128-extend-nan.c b/gcc/testsuite/gcc.dg/torture/float128-extend-nan.c index 60f9bbe9435..65dc520af7f 100644 --- a/gcc/testsuite/gcc.dg/torture/float128-extend-nan.c +++ b/gcc/testsuite/gcc.dg/torture/float128-extend-nan.c @@ -1,7 +1,10 @@ /* Test extensions to __float128 quiet signaling NaNs. */ -/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */ +/* { dg-do run } */ /* { dg-options "-fsignaling-nans" } */ +/* { dg-require-effective-target __float128 } */ +/* { dg-require-effective-target base_quadfloat_support } */ /* { dg-require-effective-target fenv_exceptions } */ +/* { dg-add-options __float128 } */ #include <fenv.h> #include <float.h> diff --git a/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-2.c b/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-2.c index 9990e190c60..b46acb39fd5 100644 --- a/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-2.c +++ b/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-2.c @@ -1,9 +1,12 @@ /* Test floating-point conversions. __float128 type with TImode: bug 53317. */ /* Origin: Joseph Myers <joseph@codesourcery.com> */ -/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */ +/* { dg-do run } */ +/* { dg-require-effective-target __float128 } */ +/* { dg-require-effective-target base_quadfloat_support } */ /* { dg-require-effective-target int128 } */ /* { dg-options "" } */ +/* { dg-add-options __float128 } */ extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-3.c b/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-3.c index 944494d9bcc..fa6eb6b72bf 100644 --- a/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-3.c +++ b/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode-3.c @@ -1,8 +1,11 @@ /* Test for correct rounding of conversions from __int128 to __float128. */ -/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */ +/* { dg-do run } */ +/* { dg-require-effective-target __float128 } */ +/* { dg-require-effective-target base_quadfloat_support } */ /* { dg-require-effective-target int128 } */ /* { dg-options "-frounding-math" } */ +/* { dg-add-options __float128 } */ #include <fenv.h> #include <stdlib.h> diff --git a/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode.c b/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode.c index 8318f8ad8ae..493dee892b0 100644 --- a/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode.c +++ b/gcc/testsuite/gcc.dg/torture/fp-int-convert-float128-timode.c @@ -1,7 +1,10 @@ /* Test floating-point conversions. __float128 type with TImode. */ /* Origin: Joseph Myers <joseph@codesourcery.com> */ -/* { dg-do run { target i?86-*-* x86_64-*-* ia64-*-* } } */ +/* { dg-do run } */ +/* { dg-require-effective-target __float128 } */ +/* { dg-require-effective-target base_quadfloat_support } */ /* { dg-options "" } */ +/* { dg-add-options __float128 } */ #include "fp-int-convert.h" diff --git a/gcc/testsuite/gcc.dg/torture/pr71423.c b/gcc/testsuite/gcc.dg/torture/pr71423.c new file mode 100644 index 00000000000..06a613f11fe --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr71423.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ + +struct S1 +{ + int f1:1; +}; + +volatile struct S1 b = { 0 }; + +int +main () +{ + char c = b.f1; + b.f1 = 1; + + if (b.f1 > -1 || c) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr71452.c b/gcc/testsuite/gcc.dg/torture/pr71452.c new file mode 100644 index 00000000000..8948d39fdaf --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr71452.c @@ -0,0 +1,10 @@ +/* { dg-do run } */ + +int main() +{ + _Bool b; + *(char *)&b = 123; + if (*(char *)&b != 123) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr71522.c b/gcc/testsuite/gcc.dg/torture/pr71522.c new file mode 100644 index 00000000000..953c4c71100 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr71522.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ + +#if __SIZEOF_LONG_DOUBLE__ == 16 +#define STR "AAAAAAAAAAAAAAA" +#elif __SIZEOF_LONG_DOUBLE__ == 12 +#define STR "AAAAAAAAAAA" +#elif __SIZEOF_LONG_DOUBLE__ == 8 +#define STR "AAAAAAA" +#elif __SIZEOF_LONG_DOUBLE__ == 4 +#define STR "AAA" +#else +#define STR "A" +#endif + +int main() +{ + long double d; + char s[sizeof d]; + + __builtin_memcpy(&d, STR, sizeof d); + __builtin_memcpy(&s, &d, sizeof s); + + if (__builtin_strncmp (s, STR, sizeof s) != 0) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr71606.c b/gcc/testsuite/gcc.dg/torture/pr71606.c new file mode 100644 index 00000000000..b0cc26ac771 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr71606.c @@ -0,0 +1,11 @@ +_Complex a; +void fn1 (); + +int main () { + fn1 (a); + return 0; +} + +void fn1 (__complex__ long double p1) { + __imag__ p1 = 6.0L; +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp101.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp101.c new file mode 100644 index 00000000000..cfca5396e63 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp101.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +int x = 1; + +int main () +{ + int t = (1/(1>=x))>>1; + if (t != 0) __builtin_abort(); + return 0; +} + +/* { dg-final { scan-tree-dump "<bb 2>:\[\n\r \]*return 0;" "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr71259.c b/gcc/testsuite/gcc.dg/vect/pr71259.c new file mode 100644 index 00000000000..eefa2433225 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr71259.c @@ -0,0 +1,28 @@ +/* PR tree-optimization/71259 */ +/* { dg-do run } */ +/* { dg-options "-O3" } */ +/* { dg-additional-options "-mavx" { target avx_runtime } } */ + +#include "tree-vect.h" + +long a, b[1][44][2]; +long long c[44][17][2]; + +int +main () +{ + int i, j, k; + check_vect (); + asm volatile ("" : : : "memory"); + for (i = 0; i < 44; i++) + for (j = 0; j < 17; j++) + for (k = 0; k < 2; k++) + c[i][j][k] = (30995740 >= *(k + *(j + *b)) != (a != 8)) - 5105075050047261684; + asm volatile ("" : : : "memory"); + for (i = 0; i < 44; i++) + for (j = 0; j < 17; j++) + for (k = 0; k < 2; k++) + if (c[i][j][k] != -5105075050047261684) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/vect/pr71264.c b/gcc/testsuite/gcc.dg/vect/pr71264.c new file mode 100644 index 00000000000..4f6381e323a --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr71264.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target vect_int } */ + +typedef unsigned char uint8_t; +typedef uint8_t footype __attribute__((vector_size(4))); + +void test(uint8_t *ptr, uint8_t *mask) +{ + footype mv; + __builtin_memcpy(&mv, mask, sizeof(mv)); + for (unsigned i = 0; i < 16; i += 4) + { + footype temp; + __builtin_memcpy(&temp, &ptr[i], sizeof(temp)); + temp ^= mv; + __builtin_memcpy(&ptr[i], &temp, sizeof(temp)); + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr71823.c b/gcc/testsuite/gcc.dg/vect/pr71823.c new file mode 100644 index 00000000000..079cde41ce4 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr71823.c @@ -0,0 +1,14 @@ +/* PR tree-optimization/71823 */ +/* { dg-do compile } */ +/* { dg-additional-options "-mfma" { target i?86-*-* x86_64-*-* } } */ + +float a[4], b[4]; + +int +main () +{ + int i; + for (i = 0; i < 4; ++i) + b[i] = __builtin_fma (1024.0f, 1024.0f, a[i]); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c new file mode 100644 index 00000000000..96608ebb283 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c @@ -0,0 +1,82 @@ +/* Test the `v[min|max]nm{q}_f*' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "arm_neon.h" + +extern void abort (); + +#define CHECK(T, N, R, E) \ + {\ + int i = 0;\ + for (; i < N; i++)\ + if (* (T *) &R[i] != * (T *) &E[i])\ + abort ();\ + } + +int +main (int argc, char **argv) +{ + float32x2_t f32x2_input1 = vdup_n_f32 (-1.0); + float32x2_t f32x2_input2 = vdup_n_f32 (0.0); + float32x2_t f32x2_exp_minnm = vdup_n_f32 (-1.0); + float32x2_t f32x2_exp_maxnm = vdup_n_f32 (0.0); + float32x2_t f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); + float32x2_t f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); + + CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + + f32x2_input1 = vdup_n_f32 (__builtin_nanf ("")); + f32x2_input2 = vdup_n_f32 (1.0); + f32x2_exp_minnm = vdup_n_f32 (1.0); + f32x2_exp_maxnm = vdup_n_f32 (1.0); + f32x2_ret_minnm = vminnm_f32 (f32x2_input1, f32x2_input2); + f32x2_ret_maxnm = vmaxnm_f32 (f32x2_input1, f32x2_input2); + + CHECK (uint32_t, 2, f32x2_ret_minnm, f32x2_exp_minnm); + CHECK (uint32_t, 2, f32x2_ret_maxnm, f32x2_exp_maxnm); + + float32x4_t f32x4_input1 = vdupq_n_f32 (-1024.0); + float32x4_t f32x4_input2 = vdupq_n_f32 (77.0); + float32x4_t f32x4_exp_minnm = vdupq_n_f32 (-1024.0); + float32x4_t f32x4_exp_maxnm = vdupq_n_f32 (77.0); + float32x4_t f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); + float32x4_t f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); + + CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + + f32x4_input1 = vdupq_n_f32 (-__builtin_nanf ("")); + f32x4_input2 = vdupq_n_f32 (-1.0); + f32x4_exp_minnm = vdupq_n_f32 (-1.0); + f32x4_exp_maxnm = vdupq_n_f32 (-1.0); + f32x4_ret_minnm = vminnmq_f32 (f32x4_input1, f32x4_input2); + f32x4_ret_maxnm = vmaxnmq_f32 (f32x4_input1, f32x4_input2); + + CHECK (uint32_t, 4, f32x4_ret_minnm, f32x4_exp_minnm); + CHECK (uint32_t, 4, f32x4_ret_maxnm, f32x4_exp_maxnm); + + float64x2_t f64x2_input1 = vdupq_n_f64 (1.23); + float64x2_t f64x2_input2 = vdupq_n_f64 (4.56); + float64x2_t f64x2_exp_minnm = vdupq_n_f64 (1.23); + float64x2_t f64x2_exp_maxnm = vdupq_n_f64 (4.56); + float64x2_t f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); + float64x2_t f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); + + CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + + f64x2_input1 = vdupq_n_f64 (-__builtin_nan ("")); + f64x2_input2 = vdupq_n_f64 (1.0); + f64x2_exp_minnm = vdupq_n_f64 (1.0); + f64x2_exp_maxnm = vdupq_n_f64 (1.0); + f64x2_ret_minnm = vminnmq_f64 (f64x2_input1, f64x2_input2); + f64x2_ret_maxnm = vmaxnmq_f64 (f64x2_input1, f64x2_input2); + + CHECK (uint64_t, 2, f64x2_ret_minnm, f64x2_exp_minnm); + CHECK (uint64_t, 2, f64x2_ret_maxnm, f64x2_exp_maxnm); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/pr50739.c b/gcc/testsuite/gcc.target/avr/pr50739.c new file mode 100644 index 00000000000..a6850b73c3e --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr50739.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-fmerge-all-constants" } */ + +char *ca = "123"; + +const char a[] __attribute__((__progmem__))= "a"; +const char b[] __attribute__((__progmem__))= "b"; diff --git a/gcc/testsuite/gcc.target/avr/pr71103.c b/gcc/testsuite/gcc.target/avr/pr71103.c new file mode 100644 index 00000000000..43244d15e97 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr71103.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +struct ResponseStruct{ + unsigned char responseLength; + char *response; +}; + +static char response[5]; +struct ResponseStruct something(){ + struct ResponseStruct returnValue; + returnValue.responseLength = 5; + returnValue.response = response; + return returnValue; +} + diff --git a/gcc/testsuite/gcc.target/avr/torture/pr71103-2.c b/gcc/testsuite/gcc.target/avr/torture/pr71103-2.c new file mode 100644 index 00000000000..480ad05acab --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr71103-2.c @@ -0,0 +1,118 @@ +/* Use -g0 so that this test case doesn't just fail because + of PR52472. */ + +/* { dg-do compile } */ +/* { dg-options "-std=gnu99 -g0" } */ + +struct S12 +{ + char c; + const char *p; +}; + +struct S12f +{ + char c; + struct S12f (*f)(void); +}; + +struct S12labl +{ + char c; + void **labl; +}; + +struct S121 +{ + char c; + const char *p; + char d; +}; + +const char str[5] = "abcd"; + +struct S12 test_S12_0 (void) +{ + struct S12 s; + s.c = 'A'; + s.p = str; + return s; +} + +struct S12 test_S12_4 (void) +{ + struct S12 s; + s.c = 'A'; + s.p = str + 4; + return s; +} + +struct S12f test_S12f (void) +{ + struct S12f s; + s.c = 'A'; + s.f = test_S12f; + return s; +} + +struct S121 test_S121 (void) +{ + struct S121 s; + s.c = 'c'; + s.p = str + 4; + s.d = 'd'; + return s; +} + +extern void use_S12lab (struct S12labl*); + +struct S12labl test_S12lab (void) +{ + struct S12labl s; +labl:; + s.c = 'A'; + s.labl = &&labl; + return s; +} + +#ifdef __MEMX + +struct S13 +{ + char c; + const __memx char *p; +}; + +const __memx char str_x[] = "abcd"; + +struct S13 test_S13_0 (void) +{ + struct S13 s; + s.c = 'A'; + s.p = str_x; + return s; +} + +struct S13 test_S13_4a (void) +{ + struct S13 s; + s.c = 'A'; + s.p = str_x + 4; + return s; +} + +#ifdef __FLASH1 + +const __flash1 char str_1[] = "abcd"; + +struct S13 test_13_4b (void) +{ + struct S13 s; + s.c = 'A'; + s.p = str_1 + 4; + return s; +} + +#endif /* have __flash1 */ +#endif /* have __memx */ + diff --git a/gcc/testsuite/gcc.target/i386/avx-pr71559.c b/gcc/testsuite/gcc.target/i386/avx-pr71559.c new file mode 100644 index 00000000000..af16d56d785 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-pr71559.c @@ -0,0 +1,8 @@ +/* PR target/71559 */ +/* { dg-do run { target avx } } */ +/* { dg-options "-O2 -ftree-vectorize -mavx" } */ + +#include "avx-check.h" +#define PR71559_TEST avx_test + +#include "sse2-pr71559.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-1.c new file mode 100644 index 00000000000..fc48b1572b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceil (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-2.c new file mode 100644 index 00000000000..bf8af064cfe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceil-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-ceil-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-1.c new file mode 100644 index 00000000000..c6d53d89fc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceilf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-2.c new file mode 100644 index 00000000000..80e594dbfa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-ceilf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-1.c new file mode 100644 index 00000000000..4788825fc3d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceilf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-2.c new file mode 100644 index 00000000000..95a79e29d12 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-ceilf-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-ceilf-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-1.c new file mode 100644 index 00000000000..b7cbed005dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floor (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c new file mode 100644 index 00000000000..0d401f78d63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-floor-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-1.c new file mode 100644 index 00000000000..6a25f438a8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floorf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-2.c new file mode 100644 index 00000000000..f4bfec5385e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-floorf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-1.c new file mode 100644 index 00000000000..69fc73d78ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floorf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-2.c new file mode 100644 index 00000000000..90c6c0fade5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-floorf-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-floorf-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c b/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c new file mode 100644 index 00000000000..d78d86ac2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c @@ -0,0 +1,8 @@ +/* PR target/71559 */ +/* { dg-do run { target avx512f } } */ +/* { dg-options "-O2 -ftree-vectorize -mavx512f" } */ + +#include "avx512f-check.h" +#define PR71559_TEST avx512f_test + +#include "sse2-pr71559.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-1.c new file mode 100644 index 00000000000..8e1745aa13a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rint (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-2.c new file mode 100644 index 00000000000..c3f78ac3f25 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rint-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-rint-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vcvtpd2dq\[^\n\]+ymm\[0-9\](?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vinserti64x4\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-1.c new file mode 100644 index 00000000000..ac3e9a25973 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rintf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rintf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-2.c new file mode 100644 index 00000000000..c172e61f84a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-rintf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vcvtps2dq\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-1.c new file mode 100644 index 00000000000..61bea578e18 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) round (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-2.c new file mode 100644 index 00000000000..5982c65d1e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-round-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-round-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvttpd2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c new file mode 100644 index 00000000000..c5ec9e7ec00 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) roundf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) roundf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-2.c new file mode 100644 index 00000000000..0d8abb892d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-roundf-sfix-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttps2dq\[^\n\]+zmm\[0-9\].{7}(?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-1.c new file mode 100644 index 00000000000..dfb93d72324 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = trunc (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != trunc (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c new file mode 100644 index 00000000000..e8ec0227653 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-trunc-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-1.c b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-1.c new file mode 100644 index 00000000000..db13e712829 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define __NO_MATH_INLINES +#include <math.h> +#include "avx512f-check.h" + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +avx512f_test (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = truncf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != truncf (a[i])) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-2.c new file mode 100644 index 00000000000..ae542d8276b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-truncf-vec-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */ + +#include "avx512f-truncf-vec-1.c" + +/* { dg-final { scan-assembler-times "vrndscaleps\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr68657.c b/gcc/testsuite/gcc.target/i386/pr68657.c new file mode 100644 index 00000000000..6f0d4987d39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr68657.c @@ -0,0 +1,15 @@ +/* PR c/68657 */ +/* { dg-options "-mno-avx512f -Werror=psabi" } */ + +typedef int V __attribute__((vector_size (64))); + +void foo (V x, V *y) { /* { dg-error "AVX512F vector argument without AVX512F enabled" } */ + *y = x; +} + +V bar (V *x) { /* { dg-error "AVX512F vector return without AVX512F enabled" } */ + return *x; +} + +/* { dg-message "The ABI for passing parameters with 64-byte alignment has changed" "" { target *-*-* } 6 } */ +/* { dg-message "some warnings being treated as errors" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr71529.C b/gcc/testsuite/gcc.target/i386/pr71529.C new file mode 100644 index 00000000000..3169101e1a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr71529.C @@ -0,0 +1,22 @@ +/* PR71529 */ +/* { dg-do compile { target { ! x32 } } } */ +/* { dg-options "-fcheck-pointer-bounds -mmpx -O2" } */ + +class c1 +{ + public: + virtual ~c1 (); +}; + +class c2 +{ + public: + virtual ~c2 (); +}; + +class c3 : c1, c2 { }; + +int main (int, char **) +{ + c3 obj; +} diff --git a/gcc/testsuite/gcc.target/i386/pr71647.c b/gcc/testsuite/gcc.target/i386/pr71647.c new file mode 100644 index 00000000000..ab091bd93dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr71647.c @@ -0,0 +1,32 @@ +/* PR tree-optimization/71647 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -fopenmp-simd -mavx -mno-avx512f -fdump-tree-vect-details" } */ + +void +foo (double *a, double *b) +{ + int i; +#pragma omp simd aligned(a,b:4*sizeof(double)) + for (i = 0; i < 32768; i++) + a[i] += b[i]; +} + +void +bar (double *a, double *b) +{ + int i; +#pragma omp simd aligned(a,b:32) + for (i = 0; i < 32768; i++) + a[i] += b[i]; +} + +void +baz (double *a, double *b) +{ + int i; +#pragma omp simd aligned(a,b:32L) + for (i = 0; i < 32768; i++) + a[i] += b[i]; +} + +/* { dg-final { scan-tree-dump-not "Alignment of access forced using peeling" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr71559.c b/gcc/testsuite/gcc.target/i386/sse2-pr71559.c new file mode 100644 index 00000000000..59ecc7fb37f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-pr71559.c @@ -0,0 +1,73 @@ +/* PR target/71559 */ +/* { dg-do run { target sse2 } } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ + +#ifndef PR71559_TEST +#include "sse2-check.h" +#define PR71559_TEST sse2_test +#endif + +#define N 16 +float a[N] = { 5.0f, -3.0f, 1.0f, __builtin_nanf (""), 9.0f, 7.0f, -3.0f, -9.0f, + -3.0f, -5.0f, -9.0f, __builtin_nanf (""), 0.5f, -0.5f, 0.0f, 0.0f }; +float b[N] = { -5.0f, 3.0f, 1.0f, 7.0f, 8.0f, 8.0f, -3.0f, __builtin_nanf (""), + -4.0f, -4.0f, -9.0f, __builtin_nanf (""), 0.0f, 0.0f, 0.0f, __builtin_nanf ("") }; +int c[N], d[N]; + +#define FN(name, op) \ +void \ +name (void) \ +{ \ + int i; \ + for (i = 0; i < N; i++) \ + c[i] = (op || d[i] > 37) ? 5 : 32; \ +} +FN (eq, a[i] == b[i]) +FN (ne, a[i] != b[i]) +FN (gt, a[i] > b[i]) +FN (ge, a[i] >= b[i]) +FN (lt, a[i] < b[i]) +FN (le, a[i] <= b[i]) +FN (unle, !__builtin_isgreater (a[i], b[i])) +FN (unlt, !__builtin_isgreaterequal (a[i], b[i])) +FN (unge, !__builtin_isless (a[i], b[i])) +FN (ungt, !__builtin_islessequal (a[i], b[i])) +FN (uneq, !__builtin_islessgreater (a[i], b[i])) +FN (ordered, !__builtin_isunordered (a[i], b[i])) +FN (unordered, __builtin_isunordered (a[i], b[i])) + +#define TEST(name, GT, LT, EQ, UO) \ + name (); \ + for (i = 0; i < N; i++) \ + { \ + int v; \ + switch (i % 4) \ + { \ + case 0: v = GT ? 5 : 32; break; \ + case 1: v = LT ? 5 : 32; break; \ + case 2: v = EQ ? 5 : 32; break; \ + case 3: v = UO ? 5 : 32; break; \ + } \ + if (c[i] != v) \ + __builtin_abort (); \ + } + +void +PR71559_TEST (void) +{ + int i; + asm volatile ("" : : "g" (a), "g" (b), "g" (c), "g" (d) : "memory"); + TEST (eq, 0, 0, 1, 0) + TEST (ne, 1, 1, 0, 1) + TEST (gt, 1, 0, 0, 0) + TEST (ge, 1, 0, 1, 0) + TEST (lt, 0, 1, 0, 0) + TEST (le, 0, 1, 1, 0) + TEST (unle, 0, 1, 1, 1) + TEST (unlt, 0, 1, 0, 1) + TEST (unge, 1, 0, 1, 1) + TEST (ungt, 1, 0, 0, 1) + TEST (uneq, 0, 0, 1, 1) + TEST (ordered, 1, 1, 1, 0) + TEST (unordered, 0, 0, 0, 1) +} diff --git a/gcc/testsuite/gcc.target/powerpc/abs128-1.c b/gcc/testsuite/gcc.target/powerpc/abs128-1.c new file mode 100644 index 00000000000..49635df2b90 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/abs128-1.c @@ -0,0 +1,61 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 x, z; + + x.nan.negative = 1; + x.nan.exponent = 0x22; + x.nan.quiet_nan = 0; + x.nan.mant_high = 0x1234; + x.nan.mant_low = 0xabcdef; + + z.value = __builtin_fabsq (x.value); + + if (z.nan.negative != 0 + || z.nan.exponent != 0x22 + || z.nan.quiet_nan != 0 + || z.nan.mant_high != 0x1234 + || z.nan.mant_low != 0xabcdef) + abort (); + + z.value = __builtin_fabsq (z.value); + + if (z.nan.negative != 0 + || z.nan.exponent != 0x22 + || z.nan.quiet_nan != 0 + || z.nan.mant_high != 0x1234 + || z.nan.mant_low != 0xabcdef) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c new file mode 100644 index 00000000000..429dfc072e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c @@ -0,0 +1,58 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 x, y, z; + + x.nan.negative = 0; + x.nan.exponent = 0x22; + x.nan.quiet_nan = 0; + x.nan.mant_high = 0x1234; + x.nan.mant_low = 0xabcdef; + + y.nan.negative = 1; + y.nan.exponent = 0; + y.nan.quiet_nan = 0; + y.nan.mant_high = 0; + y.nan.mant_low = 0; + + z.value = __builtin_copysignq (x.value, y.value); + + if (z.nan.negative != 1 + || z.nan.exponent != 0x22 + || z.nan.quiet_nan != 0 + || z.nan.mant_high != 0x1234 + || z.nan.mant_low != 0xabcdef) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c b/gcc/testsuite/gcc.target/powerpc/darn-0.c index ce2e25e22a1..fc150766108 100644 --- a/gcc/testsuite/gcc.target/powerpc/darn-0.c +++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c @@ -1,4 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-options "-mcpu=power9" } */ /* This test should succeed on both 32- and 64-bit configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c b/gcc/testsuite/gcc.target/powerpc/darn-1.c index d79e5c1b4d9..9b7482d6551 100644 --- a/gcc/testsuite/gcc.target/powerpc/darn-1.c +++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c @@ -1,6 +1,9 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-require-effective-target lp64 } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c b/gcc/testsuite/gcc.target/powerpc/darn-2.c index 7f47332ec49..84493602cfc 100644 --- a/gcc/testsuite/gcc.target/powerpc/darn-2.c +++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c @@ -1,6 +1,9 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-options "-mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-require-effective-target lp64 } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dfp.exp b/gcc/testsuite/gcc.target/powerpc/dfp/dfp.exp new file mode 100644 index 00000000000..081946f7fbf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dfp.exp @@ -0,0 +1,39 @@ +# Copyright (C) 2014-2016 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Exit immediately if this isn't a PowerPC target. +if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then { + return +} + +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Load support procs. +load_lib gcc-dg.exp +load_lib torture-options.exp + +# Initialize. +dg-init + +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c*]] "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c new file mode 100644 index 00000000000..29859c55986 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c new file mode 100644 index 00000000000..d634a2acd04 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c new file mode 100644 index 00000000000..a56f19ba391 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c new file mode 100644 index 00000000000..523facea156 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c new file mode 100644 index 00000000000..e62e4bc7bbe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c new file mode 100644 index 00000000000..38bff163c02 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_lt_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c new file mode 100644 index 00000000000..57fc81ad742 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c new file mode 100644 index 00000000000..990461f9c53 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c new file mode 100644 index 00000000000..dcd4a16635f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c new file mode 100644 index 00000000000..5fbf5b5cc0c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c new file mode 100644 index 00000000000..675109552b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_lt_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c new file mode 100644 index 00000000000..d24eb10f7a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c new file mode 100644 index 00000000000..d66ba886a92 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c new file mode 100644 index 00000000000..e42f0debc82 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c new file mode 100644 index 00000000000..975843c6a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c new file mode 100644 index 00000000000..d6eced78f6a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c new file mode 100644 index 00000000000..eccca7e5d85 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_gt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c new file mode 100644 index 00000000000..54f1cd3d134 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c new file mode 100644 index 00000000000..0c6594ecf46 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c new file mode 100644 index 00000000000..e30c2f4ac79 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c new file mode 100644 index 00000000000..aaa0a854370 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c new file mode 100644 index 00000000000..efec051639a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_gt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c new file mode 100644 index 00000000000..2f84bbfd36a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c new file mode 100644 index 00000000000..ac0380973f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_lt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c new file mode 100644 index 00000000000..cfa8d0d2817 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c new file mode 100644 index 00000000000..a95dcb8dbb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c new file mode 100644 index 00000000000..512e1574555 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c new file mode 100644 index 00000000000..f21399e9d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_gt_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c new file mode 100644 index 00000000000..86422831975 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_gt_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c new file mode 100644 index 00000000000..5987b438970 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c new file mode 100644 index 00000000000..00be5389310 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_gt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c new file mode 100644 index 00000000000..dcbde72a7f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c new file mode 100644 index 00000000000..c892c100aa8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_gt_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c new file mode 100644 index 00000000000..d54138d8c5c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_gt_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c new file mode 100644 index 00000000000..f00756aa23c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c new file mode 100644 index 00000000000..6b2ecf775d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c new file mode 100644 index 00000000000..c84387dc38b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c new file mode 100644 index 00000000000..f193b415007 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c new file mode 100644 index 00000000000..0de23f4f225 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_eq (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c new file mode 100644 index 00000000000..41652c99f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c new file mode 100644 index 00000000000..4ef2d555d43 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c new file mode 100644 index 00000000000..f1d6e2de80f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c new file mode 100644 index 00000000000..c85b709f228 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c new file mode 100644 index 00000000000..94962fcff2f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_eq (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c new file mode 100644 index 00000000000..79190d0dde0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c new file mode 100644 index 00000000000..2aadb7e7dc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c new file mode 100644 index 00000000000..3d9869d39f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c new file mode 100644 index 00000000000..58f542673de --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c new file mode 100644 index 00000000000..382fdc21060 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c new file mode 100644 index 00000000000..067c2071b4b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_eq_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c new file mode 100644 index 00000000000..ac2c692b51f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_eq_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c new file mode 100644 index 00000000000..cd732fbc885 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c new file mode 100644 index 00000000000..7efb1a3d0f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_eq_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c new file mode 100644 index 00000000000..74ff7ec0d50 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c new file mode 100644 index 00000000000..d6ee4f72a75 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_eq_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c new file mode 100644 index 00000000000..acd2a208379 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_eq_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c new file mode 100644 index 00000000000..1bddb651b0e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_lt_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c new file mode 100644 index 00000000000..71eab2609b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c new file mode 100644 index 00000000000..247c1448a70 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c new file mode 100644 index 00000000000..fbe137de7f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c new file mode 100644 index 00000000000..18d17f36ee3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_ov (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c new file mode 100644 index 00000000000..6e601160ef7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c new file mode 100644 index 00000000000..2ad93313760 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c new file mode 100644 index 00000000000..69272acb47a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c new file mode 100644 index 00000000000..a9ba111b82f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c new file mode 100644 index 00000000000..bd8040a175a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_ov (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c new file mode 100644 index 00000000000..078f232cb4a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c new file mode 100644 index 00000000000..1875741f5c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c new file mode 100644 index 00000000000..f84faf8022b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (5, source); +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c new file mode 100644 index 00000000000..3e512038cf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_dd requires" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c new file mode 100644 index 00000000000..044d039b464 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c new file mode 100644 index 00000000000..52a5d9a5664 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p) +{ + _Decimal64 source = *p; + + if (__builtin_dfp_dtstsfi_ov_dd (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfi" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c new file mode 100644 index 00000000000..2dd72ee1253 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal64 *p, unsigned int significance) +{ + _Decimal64 source = *p; + + return __builtin_dfp_dtstsfi_ov_dd (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c new file mode 100644 index 00000000000..6bbe73b7511 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (5, source); +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c new file mode 100644 index 00000000000..572897fee55 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (5, source); /* { dg-error "Builtin function __builtin_dtstsfi_ov_td requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c new file mode 100644 index 00000000000..4b725377e09 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (65, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c new file mode 100644 index 00000000000..c302027e3be --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_ov_td (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c new file mode 100644 index 00000000000..789b3ada11a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_ov_td (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c new file mode 100644 index 00000000000..d3aa64efa97 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p) +{ + _Decimal128 source = *p; + + if (__builtin_dfp_dtstsfi_lt (63, source)) + return 3; + else + return 5; +} + +/* { dg-final { scan-assembler "dtstsfiq" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c new file mode 100644 index 00000000000..9180e3e9a01 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +int doTestBCDSignificance (_Decimal128 *p, unsigned int significance) +{ + _Decimal128 source = *p; + + return __builtin_dfp_dtstsfi_lt (significance, source); /* { dg-error "argument 1 must be a 6-bit unsigned literal" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c new file mode 100644 index 00000000000..c5954f18a86 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef __complex float __cfloat128 __attribute__((mode(KC))); + +__cfloat128 divide (__cfloat128 x, __cfloat128 y) +{ + return x / y; +} + +__cfloat128 z, a; + +int main () +{ + z = divide (5.0q + 5.0jq, 2.0q + 1.0jq); + a = 3.0q + 1.0jq; + if (z != a) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c b/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c new file mode 100644 index 00000000000..4e3b3253caf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c @@ -0,0 +1,157 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_float128_sw_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-O2 -mcpu=power7 -mfloat128" } */ + +#ifndef NO_FLOAT +typedef _Complex float float_complex; +extern float_complex cfloat1 (void); +extern float_complex cfloat2 (void); + +#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP) +#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP) +#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2) + +#else +#define FLOAT_ARG(NAME, OP) +#define FLOAT_PTR(NAME, OP) +#define FLOAT_CALL() +#endif + +#ifndef NO_DOUBLE +typedef _Complex double double_complex; +extern double_complex cdouble1 (void); +extern double_complex cdouble2 (void); + +#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP) +#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP) +#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2) + +#else +#define DOUBLE_ARG(NAME, OP) +#define DOUBLE_PTR(NAME, OP) +#define DOUBLE_CALL() +#endif + +#ifndef NO_FLOAT128 +#ifdef __VSX__ +typedef _Complex float __attribute__((mode(KC))) float128_complex; +#else +typedef _Complex float __attribute__((mode(TC))) float128_complex; +#endif + +extern float128_complex cfloat128_1 (void); +extern float128_complex cfloat128_2 (void); + +#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2) + +#else +#define FLOAT128_ARG(NAME, OP) +#define FLOAT128_PTR(NAME, OP) +#define FLOAT128_CALL() +#endif + +#ifndef NO_LDOUBLE +typedef _Complex long double ldouble_complex; +extern ldouble_complex cldouble1 (void); +extern ldouble_complex cldouble2 (void); + +#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2) + +#else +#define LDOUBLE_ARG(NAME, OP) +#define LDOUBLE_PTR(NAME, OP) +#define LDOUBLE_CALL() +#endif + + +#define ARG_OP(SUFFIX, TYPE, NAME, OP) \ +TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \ +{ \ + return a OP b; \ +} + +#define PTR_OP(SUFFIX, TYPE, NAME, OP) \ +void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \ +{ \ + *p = *a OP *b; \ +} + +#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \ +TYPE call_ ## SUFFIX (void) \ +{ \ + TYPE value1 = FUNC1 (); \ + TYPE value2 = FUNC2 (); \ + return value1 + value2; \ +} + +#ifndef NO_ARG +#ifndef NO_ADD +FLOAT_ARG (add, +) +DOUBLE_ARG (add, +) +FLOAT128_ARG (add, +) +LDOUBLE_ARG (add, +) +#endif + +#ifndef NO_SUB +FLOAT_ARG (sub, -) +DOUBLE_ARG (sub, -) +FLOAT128_ARG (sub, -) +LDOUBLE_ARG (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_ARG (mul, *) +DOUBLE_ARG (mul, *) +FLOAT128_ARG (mul, *) +LDOUBLE_ARG (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_ARG (div, /) +DOUBLE_ARG (div, /) +FLOAT128_ARG (div, /) +LDOUBLE_ARG (div, /) +#endif +#endif + +#ifndef NO_PTR +#ifndef NO_ADD +FLOAT_PTR (add, +) +DOUBLE_PTR (add, +) +FLOAT128_PTR (add, +) +LDOUBLE_PTR (add, +) +#endif + +#ifndef NO_SUB +FLOAT_PTR (sub, -) +DOUBLE_PTR (sub, -) +FLOAT128_PTR (sub, -) +LDOUBLE_PTR (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_PTR (mul, *) +DOUBLE_PTR (mul, *) +FLOAT128_PTR (mul, *) +LDOUBLE_PTR (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_PTR (div, /) +DOUBLE_PTR (div, /) +FLOAT128_PTR (div, /) +LDOUBLE_PTR (div, /) +#endif +#endif + +#ifndef NO_CALL +FLOAT_CALL () +DOUBLE_CALL () +FLOAT128_CALL () +LDOUBLE_CALL () +#endif diff --git a/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c b/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c new file mode 100644 index 00000000000..06dd8e2f01b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target powerpc_float128_hw_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O2 -mcpu=power9 -mfloat128 -mfloat128-hardware" } */ + +#ifndef NO_FLOAT +typedef _Complex float float_complex; +extern float_complex cfloat1 (void); +extern float_complex cfloat2 (void); + +#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP) +#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP) +#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2) + +#else +#define FLOAT_ARG(NAME, OP) +#define FLOAT_PTR(NAME, OP) +#define FLOAT_CALL() +#endif + +#ifndef NO_DOUBLE +typedef _Complex double double_complex; +extern double_complex cdouble1 (void); +extern double_complex cdouble2 (void); + +#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP) +#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP) +#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2) + +#else +#define DOUBLE_ARG(NAME, OP) +#define DOUBLE_PTR(NAME, OP) +#define DOUBLE_CALL() +#endif + +#ifndef NO_FLOAT128 +#ifdef __VSX__ +typedef _Complex float __attribute__((mode(KC))) float128_complex; +#else +typedef _Complex float __attribute__((mode(TC))) float128_complex; +#endif + +extern float128_complex cfloat128_1 (void); +extern float128_complex cfloat128_2 (void); + +#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP) +#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2) + +#else +#define FLOAT128_ARG(NAME, OP) +#define FLOAT128_PTR(NAME, OP) +#define FLOAT128_CALL() +#endif + +#ifndef NO_LDOUBLE +typedef _Complex long double ldouble_complex; +extern ldouble_complex cldouble1 (void); +extern ldouble_complex cldouble2 (void); + +#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP) +#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2) + +#else +#define LDOUBLE_ARG(NAME, OP) +#define LDOUBLE_PTR(NAME, OP) +#define LDOUBLE_CALL() +#endif + + +#define ARG_OP(SUFFIX, TYPE, NAME, OP) \ +TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \ +{ \ + return a OP b; \ +} + +#define PTR_OP(SUFFIX, TYPE, NAME, OP) \ +void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \ +{ \ + *p = *a OP *b; \ +} + +#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \ +TYPE call_ ## SUFFIX (void) \ +{ \ + TYPE value1 = FUNC1 (); \ + TYPE value2 = FUNC2 (); \ + return value1 + value2; \ +} + +#ifndef NO_ARG +#ifndef NO_ADD +FLOAT_ARG (add, +) +DOUBLE_ARG (add, +) +FLOAT128_ARG (add, +) +LDOUBLE_ARG (add, +) +#endif + +#ifndef NO_SUB +FLOAT_ARG (sub, -) +DOUBLE_ARG (sub, -) +FLOAT128_ARG (sub, -) +LDOUBLE_ARG (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_ARG (mul, *) +DOUBLE_ARG (mul, *) +FLOAT128_ARG (mul, *) +LDOUBLE_ARG (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_ARG (div, /) +DOUBLE_ARG (div, /) +FLOAT128_ARG (div, /) +LDOUBLE_ARG (div, /) +#endif +#endif + +#ifndef NO_PTR +#ifndef NO_ADD +FLOAT_PTR (add, +) +DOUBLE_PTR (add, +) +FLOAT128_PTR (add, +) +LDOUBLE_PTR (add, +) +#endif + +#ifndef NO_SUB +FLOAT_PTR (sub, -) +DOUBLE_PTR (sub, -) +FLOAT128_PTR (sub, -) +LDOUBLE_PTR (sub, -) +#endif + +#ifndef NO_MUL +FLOAT_PTR (mul, *) +DOUBLE_PTR (mul, *) +FLOAT128_PTR (mul, *) +LDOUBLE_PTR (mul, *) +#endif + +#ifndef NO_DIV +FLOAT_PTR (div, /) +DOUBLE_PTR (div, /) +FLOAT128_PTR (div, /) +LDOUBLE_PTR (div, /) +#endif +#endif + +#ifndef NO_CALL +FLOAT_CALL () +DOUBLE_CALL () +FLOAT128_CALL () +LDOUBLE_CALL () +#endif + +/* { dg-final { scan-assembler "xsaddqp" } } */ +/* { dg-final { scan-assembler "xssubqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/inf128-1.c b/gcc/testsuite/gcc.target/powerpc/inf128-1.c new file mode 100644 index 00000000000..df797e33220 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/inf128-1.c @@ -0,0 +1,55 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 y; + + y.value = __builtin_infq (); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0) + abort (); + + y.value = __builtin_huge_valq (); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c b/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c new file mode 100644 index 00000000000..0a1e18e1651 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mulkc3-1.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +void abort (); + +typedef __complex float __cfloat128 __attribute__((mode(KC))); + +__cfloat128 multiply (__cfloat128 x, __cfloat128 y) +{ + return x * y; +} + +__cfloat128 z, a; + +int main () +{ + z = multiply (2.0q + 1.0jq, 3.0q + 1.0jq); + a = 5.0q + 5.0jq; + if (z != a) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/nan128-1.c b/gcc/testsuite/gcc.target/powerpc/nan128-1.c new file mode 100644 index 00000000000..e327f40f837 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/nan128-1.c @@ -0,0 +1,77 @@ +/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */ +/* { dg-options "-mfloat128 -mvsx" } */ + +#include <stdio.h> + +void abort (); + +typedef unsigned long long int uint64_t; + +typedef union +{ + __float128 value; + + struct + { +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + unsigned negative:1; + unsigned exponent:15; + unsigned quiet_nan:1; + uint64_t mant_high:47; + uint64_t mant_low:64; +#else + uint64_t mant_low:64; + uint64_t mant_high:47; + unsigned quiet_nan:1; + unsigned exponent:15; + unsigned negative:1; +#endif + } nan; + +} ieee854_float128; + +int +main (int argc, int *argv[]) +{ + ieee854_float128 y; + + y.value = __builtin_nanq ("1"); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 1 + || y.nan.mant_high != 0 + || y.nan.mant_low != 1) + abort (); + + y.value = __builtin_nanq ("0x2ab3c"); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 1 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0x2ab3c) + abort (); + + y.value = __builtin_nansq ("1"); + + if ( + y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 1 + ) + abort (); + + y.value = __builtin_nansq ("0x2ab3c"); + + if (y.nan.negative != 0 + || y.nan.exponent != 0x7fff + || y.nan.quiet_nan != 0 + || y.nan.mant_high != 0 + || y.nan.mant_low != 0x2ab3c) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c index 4947386721a..b8a03d30f9a 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64le-*-* } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O3" } */ +/* { dg-options "-mcpu=power9 -O3 -mfloat128" } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-final { scan-assembler "lxvx" } } */ /* { dg-final { scan-assembler "stxvx" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c new file mode 100644 index 00000000000..13b72872d74 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +vector int +foo_r (int a) +{ + return (vector int) { a, a, a, a }; /* mtvsrws */ +} + +vector int +foo_r2 (int a) +{ + return vec_splats (a); /* mtvsrws */ +} + +vector int +foo_p (int *a) +{ + return (vector int) { *a, *a, *a, *a }; /* lxvwsx */ +} + +/* { dg-final { scan-assembler-times "mtvsrws" 2 } } */ +/* { dg-final { scan-assembler-times "lxvwsx" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c new file mode 100644 index 00000000000..2468e92dddb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +vector float +foo_r (float a) +{ + return (vector float) { a, a, a, a }; /* xscvdpspn/xxspltw */ +} + +vector float +foo_r2 (float a) +{ + return vec_splats (a); /* xscvdpspn/xxspltw */ +} + +vector float +foo_g (float *a) +{ + float f = *a; + + __asm__ (" # %0" : "+r" (f)); + return (vector float) { f, f, f, f }; /* mtvsrws */ +} + +vector float +foo_p (float *a) +{ + return (vector float) { *a, *a, *a, *a }; /* lxvwsx */ +} + +/* { dg-final { scan-assembler-times "xscvdpspn" 2 } } */ +/* { dg-final { scan-assembler-times "xxspltw" 2 } } */ +/* { dg-final { scan-assembler-times "mtvsrws" 1 } } */ +/* { dg-final { scan-assembler-times "lxvwsx" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c new file mode 100644 index 00000000000..8a121da2572 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c @@ -0,0 +1,61 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +typedef vector signed char v16qi_t; +typedef vector short v8hi_t; +typedef vector int v4si_t; +typedef vector long long v2di_t; + +void v16qi_0a (v16qi_t *p) { *p = (v16qi_t) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; } +void v8hi_0a (v8hi_t *p) { *p = (v8hi_t) { 0, 0, 0, 0, 0, 0, 0, 0 }; } +void v4si_0a (v4si_t *p) { *p = (v4si_t) { 0, 0, 0, 0 }; } +void v2di_0a (v2di_t *p) { *p = (v2di_t) { 0, 0 }; } + +void v16qi_0b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)0); } +void v8hi_0b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)0); } +void v4si_0b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)0); } +void v2di_0b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)0); } + +void v16qi_m1a (v16qi_t *p) { *p = (v16qi_t) { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; } +void v8hi_m1a (v8hi_t *p) { *p = (v8hi_t) { -1, -1, -1, -1, -1, -1, -1, -1 }; } +void v4si_m1a (v4si_t *p) { *p = (v4si_t) { -1, -1, -1, -1 }; } +void v2di_m1a (v2di_t *p) { *p = (v2di_t) { -1, -1 }; } + +void v16qi_m1b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)-1); } +void v8hi_m1b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)-1); } +void v4si_m1b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)-1); } +void v2di_m1b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)-1); } + +void v16qi_5a (v16qi_t *p) { *p = (v16qi_t) { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; } +void v8hi_5a (v8hi_t *p) { *p = (v8hi_t) { 5, 5, 5, 5, 5, 5, 5, 5 }; } +void v4si_5a (v4si_t *p) { *p = (v4si_t) { 5, 5, 5, 5 }; } +void v2di_5a (v2di_t *p) { *p = (v2di_t) { 5, 5 }; } + +void v16qi_5b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)5); } +void v8hi_5b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)5); } +void v4si_5b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)5); } +void v2di_5b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)5); } + +void v16qi_33a (v16qi_t *p) { *p = (v16qi_t) { 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33, 33 }; } +void v8hi_33a (v8hi_t *p) { *p = (v8hi_t) { 33, 33, 33, 33, 33, 33, 33, 33 }; } +void v4si_33a (v4si_t *p) { *p = (v4si_t) { 33, 33, 33, 33 }; } +void v2di_33a (v2di_t *p) { *p = (v2di_t) { 33, 33 }; } + +void v16qi_33b (v16qi_t *p) { *p = (v16qi_t) vec_splats ((signed char)33); } +void v8hi_33b (v8hi_t *p) { *p = (v8hi_t) vec_splats ((short)33); } +void v4si_33b (v4si_t *p) { *p = (v4si_t) vec_splats ((int)33); } +void v2di_33b (v2di_t *p) { *p = (v2di_t) vec_splats ((long long)33); } + +/* { dg-final { scan-assembler "xxspltib" } } */ +/* { dg-final { scan-assembler "vextsb2d" } } */ +/* { dg-final { scan-assembler "vextsb2w" } } */ +/* { dg-final { scan-assembler "vupk\[hl\]sb" } } */ +/* { dg-final { scan-assembler-not "lxvd2x" } } */ +/* { dg-final { scan-assembler-not "lxvw4x" } } */ +/* { dg-final { scan-assembler-not "lxv " } } */ +/* { dg-final { scan-assembler-not "lxvx" } } */ +/* { dg-final { scan-assembler-not "lvx" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c new file mode 100644 index 00000000000..d643324afe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +#include <altivec.h> + +vector long long foo (long long a) { return (vector long long) { a, a }; } + +/* { dg-final { scan-assembler "mtvsrdd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr47755.c b/gcc/testsuite/gcc.target/powerpc/pr47755.c index 8feef291e56..d5feecac691 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr47755.c +++ b/gcc/testsuite/gcc.target/powerpc/pr47755.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ -/* { dg-final { scan-assembler "xxlxor" } } */ +/* { dg-final { scan-assembler "xxlxor\|vspltis\[bhw\]" } } */ /* { dg-final { scan-assembler-not "lxvd2x" } } */ /* { dg-final { scan-assembler-not "lxvw4x" } } */ /* { dg-final { scan-assembler-not "lvx" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71186.c b/gcc/testsuite/gcc.target/powerpc/pr71186.c new file mode 100644 index 00000000000..22762ccafb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71186.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ + +static unsigned short x[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16))); +static unsigned short y[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16))); +static unsigned short a; + +void obfuscate(void *a, ...); + +static void __attribute__((noinline)) do_one(void) +{ + unsigned long i; + + obfuscate(x, y, &a); + + for (i = 0; i < (16384/sizeof(unsigned short)); i++) + y[i] = a * x[i]; + + obfuscate(x, y, &a); +} + +int main(void) +{ + unsigned long i; + + for (i = 0; i < 1000000; i++) + do_one(); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c new file mode 100644 index 00000000000..fa6b4ffb816 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c @@ -0,0 +1,20 @@ +/* Test for reload ICE arising from POWER9 Vector Dform code generation. */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */ + +typedef __attribute__((altivec(vector__))) int type_t; +type_t +func (type_t *src) +{ + asm volatile ("# force the base reg on the load below to be spilled" + : /* no outputs */ + : /* no inputs */ + : "r0", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"); + return src[1]; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c new file mode 100644 index 00000000000..99855fa1667 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c @@ -0,0 +1,47 @@ +/* Test for reload ICE arising from POWER9 Vector Dform code generation. */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */ + +typedef double vec[3]; +struct vec_t +{ + vec x; + vec y; +}; +int a, j, k, l, m, n, o, p, q; +double b, i; +vec c; +double h[6]; +void func1 (vec); + +void +func2 (double *b) +{ + for (; k; k--) + for (; j <= k;) + for (; m <= q; m++) + for (; n <= k; n++) + for (; o <= l; o++) + { + j = p + m + n + o; + h[j] = i; + } +} + +void +func3 (void) +{ + struct vec_t d; + func1 (d.y); + func2 (&b); + for (; a;) + { + double *e = d.y, *g; + double f; + c[0] = g[0] + f * e[0]; + c[1] = g[1] + f * e[1]; + func1 (c); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71670.c b/gcc/testsuite/gcc.target/powerpc/pr71670.c new file mode 100644 index 00000000000..18fb62759d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71670.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O1" } */ + +volatile int a; +int b; +void fn1(void) { b + (long)b || a; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr71698.c b/gcc/testsuite/gcc.target/powerpc/pr71698.c new file mode 100644 index 00000000000..c752f64e1c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71698.c @@ -0,0 +1,13 @@ +/* Test for a reload ICE arising from trying to direct move a TDmode value. */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target dfp } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */ + +extern void testvad128 (int n, ...); +void +testitd128 (_Decimal128 g01d128) +{ + testvad128 (1, g01d128); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71720.c b/gcc/testsuite/gcc.target/powerpc/pr71720.c new file mode 100644 index 00000000000..732daf97595 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71720.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat. */ + +vector float +splat_v4sf (float f) +{ + return (vector float) { f, f, f, f }; +} + +/* { dg-final { scan-assembler "xscvdpspn " } } */ +/* { dg-final { scan-assembler "xxspltw .*,.*,0" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71763.c b/gcc/testsuite/gcc.target/powerpc/pr71763.c new file mode 100644 index 00000000000..7910a90b988 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71763.c @@ -0,0 +1,27 @@ +// PR target/71763 +// { dg-do compile } +// { dg-options "-O1 -mvsx" } +// { dg-xfail-if "PR70098" { lp64 && powerpc64_no_dm } } +// { dg-prune-output ".*internal compiler error.*" } + +int a, b; +float c; + +void fn2(void); + +void fn1(void) +{ + long d; + + for (d = 3; d; d--) { + for (a = 0; a <= 1; a++) { + b &= 1; + if (b) { + for (;;) { + fn2(); + c = d; + } + } + } + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr71805.c b/gcc/testsuite/gcc.target/powerpc/pr71805.c new file mode 100644 index 00000000000..02db059dff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71805.c @@ -0,0 +1,113 @@ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O3 --param tree-reassoc-width=1" } */ + +/* Originally from gcc.dg/vect/pr45752.c. */ +#include <stdarg.h> + +#ifdef __cplusplus +extern "C" { +#endif +extern void abort (void); +extern void exit (int); +#ifdef __cplusplus +} +#endif + +#define M00 100 +#define M10 216 +#define M20 23 +#define M30 237 +#define M40 437 + +#define M01 1322 +#define M11 13 +#define M21 27271 +#define M31 2280 +#define M41 284 + +#define M02 74 +#define M12 191 +#define M22 500 +#define M32 111 +#define M42 1114 + +#define M03 134 +#define M13 117 +#define M23 11 +#define M33 771 +#define M43 71 + +#define M04 334 +#define M14 147 +#define M24 115 +#define M34 7716 +#define M44 16 + +#define N 20 + +void foo (unsigned int *__restrict__ pInput, + unsigned int *__restrict__ pOutput, + unsigned int *__restrict__ pInput2, + unsigned int *__restrict__ pOutput2) +{ + unsigned int i, a, b, c, d, e; + + for (i = 0; i < N / 5; i++) + { + a = *pInput++; + b = *pInput++; + c = *pInput++; + d = *pInput++; + e = *pInput++; + + *pOutput++ = M00 * a + M01 * b + M02 * c + M03 * d + M04 * e; + *pOutput++ = M10 * a + M11 * b + M12 * c + M13 * d + M14 * e; + *pOutput++ = M20 * a + M21 * b + M22 * c + M23 * d + M24 * e; + *pOutput++ = M30 * a + M31 * b + M32 * c + M33 * d + M34 * e; + *pOutput++ = M40 * a + M41 * b + M42 * c + M43 * d + M44 * e; + + + a = *pInput2++; + b = *pInput2++; + c = *pInput2++; + d = *pInput2++; + e = *pInput2++; + + *pOutput2++ = M00 * a + M01 * b + M02 * c + M03 * d + M04 * e; + *pOutput2++ = M10 * a + M11 * b + M12 * c + M13 * d + M14 * e; + *pOutput2++ = M20 * a + M21 * b + M22 * c + M23 * d + M24 * e; + *pOutput2++ = M30 * a + M31 * b + M32 * c + M33 * d + M34 * e; + *pOutput2++ = M40 * a + M41 * b + M42 * c + M43 * d + M44 * e; + + } +} + +int main (int argc, const char* argv[]) +{ + unsigned int input[N], output[N], i, input2[N], output2[N]; + unsigned int check_results[N] + = {3208, 1334, 28764, 35679, 2789, 13028, 4754, 168364, 91254, 12399, + 22848, 8174, 307964, 146829, 22009, 32668, 11594, 447564, 202404, 31619 }; + unsigned int check_results2[N] + = {7136, 2702, 84604, 57909, 6633, 16956, 6122, 224204, 113484, 16243, + 26776, 9542, 363804, 169059, 25853, 36596, 12962, 503404, 224634, 35463 }; + + for (i = 0; i < N; i++) + { + input[i] = i%256; + input2[i] = i + 2; + output[i] = 0; + output2[i] = 0; + __asm__ volatile (""); + } + + foo (input, output, input2, output2); + + for (i = 0; i < N; i++) + if (output[i] != check_results[i] + || output2[i] != check_results2[i]) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-1.c b/gcc/testsuite/gcc.target/powerpc/signbit-1.c new file mode 100644 index 00000000000..bdfeb702663 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/signbit-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O2 -mfloat128" } */ + +int do_signbit_kf (__float128 a) { return __builtin_signbit (a); } +int do_signbit_if (__ibm128 a) { return __builtin_signbit (a); } +int do_signbit_tf (long double a) { return __builtin_signbit (a); } + +/* { dg-final { scan-assembler-not "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "stxsd" } } */ +/* { dg-final { scan-assembler-not "stxsdx" } } */ +/* { dg-final { scan-assembler-times "mfvsrd" 3 } } */ +/* { dg-final { scan-assembler-times "srdi" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-2.c b/gcc/testsuite/gcc.target/powerpc/signbit-2.c new file mode 100644 index 00000000000..b5bd856d909 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/signbit-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -mfloat128" } */ + +int do_signbit_kf (__float128 *a) { return __builtin_signbit (*a); } + +/* { dg-final { scan-assembler-not "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "stxsd" } } */ +/* { dg-final { scan-assembler-not "stxsdx" } } */ +/* { dg-final { scan-assembler-not "lxvd2x" } } */ +/* { dg-final { scan-assembler-not "lxvw4x" } } */ +/* { dg-final { scan-assembler-not "lxsd" } } */ +/* { dg-final { scan-assembler-not "lxsdx" } } */ +/* { dg-final { scan-assembler-times "ld" 1 } } */ +/* { dg-final { scan-assembler-times "srdi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-3.c b/gcc/testsuite/gcc.target/powerpc/signbit-3.c new file mode 100644 index 00000000000..cd64143fc2f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/signbit-3.c @@ -0,0 +1,172 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target ppc_float128_sw } */ +/* { dg-options "-mcpu=power7 -O2 -mfloat128 -lm" } */ + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <stddef.h> +#include <stdint.h> +#include <inttypes.h> +#include <stdlib.h> +#include <math.h> + +#if defined(__BIG_ENDIAN__) +struct ieee128 { + uint64_t upper; + uint64_t lower; +}; + +#elif defined(__LITTLE_ENDIAN__) +struct ieee128 { + uint64_t lower; + uint64_t upper; +}; + +#else +#error "Unknown system" +#endif + +union ieee_union { + __float128 f128; + struct ieee128 st128; +}; + +#ifdef DEBUG +static int num_errors = 0; + +__attribute__((__noinline__)) +static void +failure (int expected, int got, __float128 x) +{ + unsigned sign; + unsigned exponent; + uint64_t mantissa1; + uint64_t mantissa2; + uint64_t upper; + uint64_t lower; + + union ieee_union u; + + u.f128 = x; + upper = u.st128.upper; + lower = u.st128.lower; + + sign = (unsigned)((upper >> 63) & 1); + exponent = (unsigned)((upper >> 48) & ((((uint64_t)1) << 16) - 1)); + mantissa1 = (upper & ((((uint64_t)1) << 48) - 1)); + mantissa2 = lower; + + printf ("Expected %d, got %d, %c 0x%.4x 0x%.12" PRIx64 " 0x%.16" PRIx64, + expected, got, + sign ? '-' : '+', + exponent, + mantissa1, + mantissa2); + + num_errors++; +} + +#else + +#define failure(E, G, F) abort () +#endif + +__attribute__((__noinline__)) +static void +test_signbit_arg (__float128 f128, int expected) +{ + int sign = __builtin_signbit (f128); + + if ((expected != 0 && sign == 0) + || (expected == 0 && sign != 0)) + failure (f128, expected, sign); +} + +__attribute__((__noinline__)) +static void +test_signbit_mem (__float128 *ptr, int expected) +{ + int sign = __builtin_signbit (*ptr); + + if ((expected != 0 && sign == 0) + || (expected == 0 && sign != 0)) + failure (*ptr, expected, sign); +} + +__attribute__((__noinline__)) +static void +test_signbit_gpr (__float128 *ptr, int expected) +{ + __float128 f128 = *ptr; + int sign; + + __asm__ (" # %0" : "+r" (f128)); + + sign = __builtin_signbit (f128); + if ((expected != 0 && sign == 0) + || (expected == 0 && sign != 0)) + failure (f128, expected, sign); +} + +__attribute__((__noinline__)) +static void +test_signbit (__float128 f128, int expected) +{ +#ifdef DEBUG + union ieee_union u; + u.f128 = f128; + printf ("Expecting %d, trying %-5g " + "(0x%.16" PRIx64 " 0x%.16" PRIx64 ")\n", + expected, (double)f128, + u.st128.upper, u.st128.lower); +#endif + + test_signbit_arg (f128, expected); + test_signbit_mem (&f128, expected); + test_signbit_gpr (&f128, expected); +} + +int +main (void) +{ + union ieee_union u; + + test_signbit (+0.0q, 0); + test_signbit (+1.0q, 0); + + test_signbit (-0.0q, 1); + test_signbit (-1.0q, 1); + + test_signbit (__builtin_copysign (__builtin_infq (), +1.0q), 0); + test_signbit (__builtin_copysign (__builtin_infq (), -1.0q), 1); + + test_signbit (__builtin_copysign (__builtin_nanq (""), +1.0q), 0); + test_signbit (__builtin_copysign (__builtin_nanq (""), -1.0q), 1); + + /* force the bottom double word to have specific bits in the 'sign' bit to + make sure we are picking the right word. */ + u.f128 = 1.0q; + u.st128.lower = 0ULL; + test_signbit (u.f128, 0); + + u.st128.lower = ~0ULL; + test_signbit (u.f128, 0); + + u.f128 = -1.0q; + u.st128.lower = 0ULL; + test_signbit (u.f128, 1); + + u.st128.lower = ~0ULL; + test_signbit (u.f128, 1); + +#ifdef DEBUG + printf ("%d error(s) were found\n", num_errors); + if (num_errors) + return num_errors; +#endif + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c new file mode 100644 index 00000000000..4d66df8ffdf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsignedInt (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int source_1, source_2; + __vector unsigned int result; + + source_1 = *p; + source_2 = *q; + + result = __builtin_vec_vadu (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c new file mode 100644 index 00000000000..28c85655066 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsignedIntMacro (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absd (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c new file mode 100644 index 00000000000..726c90478c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsignedShort (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short source_1, source_2; + __vector unsigned short result; + + source_1 = *p; + source_2 = *q; + + result = __builtin_vec_vadu (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c new file mode 100644 index 00000000000..d3618db7184 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsignedShortMacro (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absd (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c new file mode 100644 index 00000000000..e5744d13994 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsignedChar (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char source_1, source_2; + __vector unsigned char result; + + source_1 = *p; + source_2 = *q; + + result = __builtin_vec_vadu (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c new file mode 100644 index 00000000000..5dc14a956f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsignedCharMacro (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absd (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c new file mode 100644 index 00000000000..649811ae0ce --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsigned (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char source_1, source_2; + __vector unsigned char uc_result; + + source_1 = *p; + source_2 = *q; + + uc_result = __builtin_vec_vadub (source_1, source_2); + return uc_result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c new file mode 100644 index 00000000000..142c3d39af5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned char +doAbsoluteDifferenceUnsigned (__vector unsigned char *p, + __vector unsigned char *q) +{ + __vector unsigned char source_1, source_2; + __vector unsigned char uc_result; + + source_1 = *p; + source_2 = *q; + + uc_result = vec_absdb (source_1, source_2); + return uc_result; +} + +/* { dg-final { scan-assembler "vabsdub" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c new file mode 100644 index 00000000000..6d933b9aa78 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsigned (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short source_1, source_2; + __vector unsigned short us_result; + + source_1 = *p; + source_2 = *q; + + us_result = __builtin_vec_vaduh (source_1, source_2); + return us_result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c new file mode 100644 index 00000000000..bf28b713b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned short +doAbsoluteDifferenceUnsignedMacro (__vector unsigned short *p, + __vector unsigned short *q) +{ + __vector unsigned short result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absdh (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduh" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c new file mode 100644 index 00000000000..5188d68e143 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsigned (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int source_1, source_2; + __vector unsigned int ui_result; + + source_1 = *p; + source_2 = *q; + + ui_result = __builtin_vec_vaduw (source_1, source_2); + return ui_result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c new file mode 100644 index 00000000000..bf93d96d967 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include <altivec.h> + +__vector unsigned int +doAbsoluteDifferenceUnsignedMacro (__vector unsigned int *p, + __vector unsigned int *q) +{ + __vector unsigned int result, source_1, source_2; + + source_1 = *p; + source_2 = *q; + + result = vec_absdw (source_1, source_2); + return result; +} + +/* { dg-final { scan-assembler "vabsduw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vslv-0.c b/gcc/testsuite/gcc.target/powerpc/vslv-0.c new file mode 100644 index 00000000000..9ad04dd92e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vslv-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = __builtin_vec_vslv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vslv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vslv-1.c b/gcc/testsuite/gcc.target/powerpc/vslv-1.c new file mode 100644 index 00000000000..2d09543c814 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vslv-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = vec_slv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vslv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsrv-0.c b/gcc/testsuite/gcc.target/powerpc/vsrv-0.c new file mode 100644 index 00000000000..29c7e3fde20 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsrv-0.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = __builtin_vec_vsrv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vsrv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsrv-1.c b/gcc/testsuite/gcc.target/powerpc/vsrv-1.c new file mode 100644 index 00000000000..cd3f714bd64 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsrv-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> + +__vector unsigned char +doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q) +{ + __vector unsigned char result, input, shift_distance; + result = vec_srv (input, shift_distance); + return result; +} + +/* { dg-final { scan-assembler "vsrv" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c index 28b62547a34..eb4a13081a2 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc64le*-*-* } } } */ /* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O0" } */ -/* { dg-require-effective-target p9vector_hw } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ /* { dg-final { scan-assembler-times "lxvd2x" 6 } } */ /* { dg-final { scan-assembler-times "lxvw4x" 6 } } */ /* { dg-final { scan-assembler-times "lxvh8x" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c index 9a7a9943033..a116316c174 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc64-*-* } } } */ /* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O0" } */ -/* { dg-require-effective-target p9vector_hw } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ /* { dg-final { scan-assembler-times "lxvx" 40 } } */ /* { dg-final { scan-assembler-times "stxvx" 40 } } */ diff --git a/gcc/testsuite/gcc.target/sparc/fpcmp.c b/gcc/testsuite/gcc.target/sparc/fpcmp.c new file mode 100644 index 00000000000..1255d67442f --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmp.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4" } */ + +typedef unsigned char vec8 __attribute__((vector_size(8))); + +long test_fpcmple8 (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmple8 (a, b); +} + +long test_fpcmpgt8 (vec8 a, vec8 b) +{ + return __builtin_vis_fpcmpgt8 (a, b); +} + +/* { dg-final { scan-assembler "fpcmple8\t%" } } */ +/* { dg-final { scan-assembler "fpcmpgt8\t%" } } */ + diff --git a/gcc/testsuite/gcc.target/sparc/fpcmpu.c b/gcc/testsuite/gcc.target/sparc/fpcmpu.c new file mode 100644 index 00000000000..816a22d7078 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fpcmpu.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4" } */ + + +typedef short vec16 __attribute__((vector_size(8))); +typedef int vec32 __attribute__((vector_size(8))); + +long test_fpcmpule16 (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpule16 (a, b); +} + +long test_fpcmpugt16 (vec16 a, vec16 b) +{ + return __builtin_vis_fpcmpugt16 (a, b); +} + +long test_fpcmpule32 (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpule32 (a, b); +} + +long test_fpcmpugt32 (vec32 a, vec32 b) +{ + return __builtin_vis_fpcmpugt32 (a, b); +} + +/* { dg-final { scan-assembler "fpcmpule16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt16\t%" } } */ +/* { dg-final { scan-assembler "fpcmpule32\t%" } } */ +/* { dg-final { scan-assembler "fpcmpugt32\t%" } } */ diff --git a/gcc/testsuite/gcc.target/sparc/vis4misc.c b/gcc/testsuite/gcc.target/sparc/vis4misc.c new file mode 100644 index 00000000000..b520b12b381 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/vis4misc.c @@ -0,0 +1,126 @@ +/* { dg-do compile } */ +/* { dg-options "-mvis4" } */ +typedef int __v2si __attribute__((vector_size(8))); +typedef short __v4hi __attribute__((vector_size(8))); +typedef unsigned char __v8qi __attribute__((vector_size(8))); + +__v8qi test_fpadd8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpadd8 (x, y); +} + +__v8qi test_fpadds8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpadds8 (x, y); +} + +__v8qi test_fpaddus8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpaddus8 (x, y); +} + +__v4hi test_fpaddus16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpaddus16 (x, y); +} + +__v8qi test_fpsub8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpsub8 (x, y); +} + +__v8qi test_fpsubs8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpsubs8 (x, y); +} + +__v8qi test_fpsubus8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpsubus8 (x, y); +} + +__v4hi test_fpsubus16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpsubus16 (x, y); +} + +__v8qi test_fpmax8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpmax8 (x, y); +} + +__v4hi test_fpmax16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpmax16 (x, y); +} + +__v2si test_fpmax32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpmax32 (x, y); +} + +__v8qi test_fpmaxu8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpmaxu8 (x, y); +} + +__v4hi test_fpmaxu16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpmaxu16 (x, y); +} + +__v2si test_fpmaxu32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpmaxu32 (x, y); +} + +__v8qi test_fpmin8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpmin8 (x, y); +} + +__v4hi test_fpmin16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpmin16 (x, y); +} + +__v2si test_fpmin32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpmin32 (x, y); +} + +__v8qi test_fpminu8 (__v8qi x, __v8qi y) +{ + return __builtin_vis_fpminu8 (x, y); +} + +__v4hi test_fpminu16 (__v4hi x, __v4hi y) +{ + return __builtin_vis_fpminu16 (x, y); +} + +__v2si test_fpminu32 (__v2si x, __v2si y) +{ + return __builtin_vis_fpminu32 (x, y); +} + +/* { dg-final { scan-assembler "fpadd8\t%" } } */ +/* { dg-final { scan-assembler "fpadds8\t%" } } */ +/* { dg-final { scan-assembler "fpaddus8\t%" } } */ +/* { dg-final { scan-assembler "fpaddus16\t%" } } */ +/* { dg-final { scan-assembler "fpsub8\t%" } } */ +/* { dg-final { scan-assembler "fpsubs8\t%" } } */ +/* { dg-final { scan-assembler "fpsubus8\t%" } } */ +/* { dg-final { scan-assembler "fpsubus16\t%" } } */ +/* { dg-final { scan-assembler "fpmax8\t%" } } */ +/* { dg-final { scan-assembler "fpmax16\t%" } } */ +/* { dg-final { scan-assembler "fpmax32\t%" } } */ +/* { dg-final { scan-assembler "fpmaxu8\t%" } } */ +/* { dg-final { scan-assembler "fpmaxu16\t%" } } */ +/* { dg-final { scan-assembler "fpmaxu32\t%" } } */ +/* { dg-final { scan-assembler "fpmin8\t%" } } */ +/* { dg-final { scan-assembler "fpmin16\t%" } } */ +/* { dg-final { scan-assembler "fpmin32\t%" } } */ +/* { dg-final { scan-assembler "fpminu8\t%" } } */ +/* { dg-final { scan-assembler "fpminu16\t%" } } */ +/* { dg-final { scan-assembler "fpminu32\t%" } } */ diff --git a/gcc/testsuite/gfortran.dg/array_constructor_49.f90 b/gcc/testsuite/gfortran.dg/array_constructor_49.f90 index ca963d3ac73..0f5036a03da 100644 --- a/gcc/testsuite/gfortran.dg/array_constructor_49.f90 +++ b/gcc/testsuite/gfortran.dg/array_constructor_49.f90 @@ -6,7 +6,7 @@ program t integer :: ndim=2, ndfp=4, i character (len=8) :: line - write (unit=line,fmt='(4I2)'), (/ ( i, i = 1, ndfp ) /) + ndim + write (unit=line,fmt='(4I2)') (/ ( i, i = 1, ndfp ) /) + ndim if (line /= ' 3 4 5 6') call abort end program t ! { dg-final { scan-tree-dump-times "__var" 3 "original" } } diff --git a/gcc/testsuite/gfortran.dg/comma_IO_extension_1.f90 b/gcc/testsuite/gfortran.dg/comma_IO_extension_1.f90 new file mode 100644 index 00000000000..abbb69d66f6 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/comma_IO_extension_1.f90 @@ -0,0 +1,8 @@ +! { dg-do compile } +! PR 60751 +! Contributed by Walter Spector <w6ws@earthlink.net> +program extracomma + implicit none + + write (*,*), 1, 2, 3 ! { dg-warning "Legacy Extension: Comma before i/o item list" } +end program diff --git a/gcc/testsuite/gfortran.dg/comma_IO_extension_2.f90 b/gcc/testsuite/gfortran.dg/comma_IO_extension_2.f90 new file mode 100644 index 00000000000..5e80a174201 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/comma_IO_extension_2.f90 @@ -0,0 +1,9 @@ +! { dg-do compile } +! { dg-options "-std=legacy" } +! PR 60751 +! Contributed by Walter Spector <w6ws@earthlink.net> +program extracomma + implicit none + + write (*,*), 1, 2, 3 +end program diff --git a/gcc/testsuite/gfortran.dg/deferred_character_17.f90 b/gcc/testsuite/gfortran.dg/deferred_character_17.f90 new file mode 100644 index 00000000000..5a9d725d263 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/deferred_character_17.f90 @@ -0,0 +1,13 @@ +!{ dg-do run } + +! Check fix for PR fortran/71623 + +program allocatemvce + implicit none + character(len=:), allocatable :: string + integer, dimension(4), target :: array = [1,2,3,4] + integer, dimension(:), pointer :: array_ptr + array_ptr => array + ! The allocate used to segfault + allocate(character(len=size(array_ptr))::string) +end program allocatemvce diff --git a/gcc/testsuite/gfortran.dg/dependency_46.f90 b/gcc/testsuite/gfortran.dg/dependency_46.f90 new file mode 100644 index 00000000000..28942a80769 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/dependency_46.f90 @@ -0,0 +1,11 @@ +! { dg-do compile } +! PR 71783 - this used to ICE due to a missing charlen for the temporary. +! Test case by Toon Moene. + +SUBROUTINE prtdata(ilen) + INTEGER :: ilen + character(len=ilen), allocatable :: cline(:) + allocate(cline(2)) + cline(1) = 'a' + cline(2) = cline(1) +END SUBROUTINE prtdata diff --git a/gcc/testsuite/gfortran.dg/goacc/asyncwait-2.f95 b/gcc/testsuite/gfortran.dg/goacc/asyncwait-2.f95 index db0ce1f912a..fe4e4eeed2c 100644 --- a/gcc/testsuite/gfortran.dg/goacc/asyncwait-2.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/asyncwait-2.f95 @@ -83,6 +83,18 @@ program asyncwait end do !$acc end parallel ! { dg-error "Unexpected \\\!\\\$ACC END PARALLEL" } + !$acc parallel copyin (a(1:N)) copy (b(1:N)) waitasync ! { dg-error "Unclassifiable OpenACC directive" } + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel ! { dg-error "Unexpected \\\!\\\$ACC END PARALLEL" } + + !$acc parallel copyin (a(1:N)) copy (b(1:N)) asyncwait ! { dg-error "Unclassifiable OpenACC directive" } + do i = 1, N + b(i) = a(i) + end do + !$acc end parallel ! { dg-error "Unexpected \\\!\\\$ACC END PARALLEL" } + !$acc parallel copyin (a(1:N)) copy (b(1:N)) wait do i = 1, N b(i) = a(i) diff --git a/gcc/testsuite/gfortran.dg/goacc/asyncwait-3.f95 b/gcc/testsuite/gfortran.dg/goacc/asyncwait-3.f95 index 32c11def6f7..ed72a9ba28a 100644 --- a/gcc/testsuite/gfortran.dg/goacc/asyncwait-3.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/asyncwait-3.f95 @@ -11,17 +11,17 @@ program asyncwait a(:) = 3.0 b(:) = 0.0 - !$acc wait (1 2) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait (1 2) ! { dg-error "Syntax error in OpenACC expression list at" } - !$acc wait (1,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait (1,) ! { dg-error "Syntax error in OpenACC expression list at" } - !$acc wait (,1) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait (,1) ! { dg-error "Syntax error in OpenACC expression list at" } - !$acc wait (1, 2, ) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait (1, 2, ) ! { dg-error "Syntax error in OpenACC expression list at" } - !$acc wait (1, 2, ,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait (1, 2, ,) ! { dg-error "Syntax error in OpenACC expression list at" } - !$acc wait (1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait (1 ! { dg-error "Syntax error in OpenACC expression list at" } !$acc wait (1, *) ! { dg-error "Invalid argument to \\\$\\\!ACC WAIT" } @@ -33,9 +33,9 @@ program asyncwait !$acc wait (1.0) ! { dg-error "WAIT clause at \\\(1\\\) requires a scalar INTEGER expression" } - !$acc wait 1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait 1 ! { dg-error "Unclassifiable OpenACC directive" } - !$acc wait N ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait N ! { dg-error "Unclassifiable OpenACC directive" } !$acc wait (1) end program asyncwait diff --git a/gcc/testsuite/gfortran.dg/goacc/asyncwait-4.f95 b/gcc/testsuite/gfortran.dg/goacc/asyncwait-4.f95 index cd64ef3d387..df311545c52 100644 --- a/gcc/testsuite/gfortran.dg/goacc/asyncwait-4.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/asyncwait-4.f95 @@ -11,21 +11,21 @@ program asyncwait a(:) = 3.0 b(:) = 0.0 - !$acc wait async (1 2) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (1 2) ! { dg-error "Unclassifiable OpenACC directive" } - !$acc wait async (1,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (1,) ! { dg-error "Unclassifiable OpenACC directive" } - !$acc wait async (,1) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (,1) ! { dg-error "Invalid character in name" } - !$acc wait async (1, 2, ) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (1, 2, ) ! { dg-error "Unclassifiable OpenACC directive" } - !$acc wait async (1, 2, ,) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (1, 2, ,) ! { dg-error "Unclassifiable OpenACC directive" } - !$acc wait async (1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (1 ! { dg-error "Unclassifiable OpenACC directive" } - !$acc wait async (1, *) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (1, *) ! { dg-error "Unclassifiable OpenACC directive" } - !$acc wait async (1, a) ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async (1, a) ! { dg-error "Unclassifiable OpenACC directive" } !$acc wait async (a) ! { dg-error "ASYNC clause at \\\(1\\\) requires a scalar INTEGER expression" } @@ -33,5 +33,9 @@ program asyncwait !$acc wait async (1.0) ! { dg-error "ASYNC clause at \\\(1\\\) requires a scalar INTEGER expression" } - !$acc wait async 1 ! { dg-error "Unexpected junk in \\\!\\\$ACC WAIT at" } + !$acc wait async 1 ! { dg-error "Unclassifiable OpenACC directive" } + + !$acc waitasync ! { dg-error "Unclassifiable OpenACC directive" } + + !$acc wait,async ! { dg-error "Unclassifiable OpenACC directive" } end program asyncwait diff --git a/gcc/testsuite/gfortran.dg/goacc/cache-1.f95 b/gcc/testsuite/gfortran.dg/goacc/cache-1.f95 index 2aa9e053627..39fbf2cf55a 100644 --- a/gcc/testsuite/gfortran.dg/goacc/cache-1.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/cache-1.f95 @@ -1,4 +1,6 @@ -! { dg-do compile } +! OpenACC cache directive: valid usage. +! For execution testing, this file is "#include"d from +! libgomp/testsuite/libgomp.oacc-fortran/cache-1.f95. ! { dg-additional-options "-std=f2008" } program test @@ -6,11 +8,8 @@ program test integer :: i, d(10), e(5,13) do concurrent (i=1:5) - !$acc cache (d) !$acc cache (d(1:3)) !$acc cache (d(i:i+2)) - - !$acc cache (e) !$acc cache (e(1:3,2:4)) !$acc cache (e(i:i+2,i+1:i+3)) enddo diff --git a/gcc/testsuite/gfortran.dg/goacc/cache-2.f95 b/gcc/testsuite/gfortran.dg/goacc/cache-2.f95 new file mode 100644 index 00000000000..be818788556 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/cache-2.f95 @@ -0,0 +1,12 @@ +! OpenACC cache directive: invalid usage. +! { dg-additional-options "-std=f2008" } + +program test + implicit none + integer :: i, d(10), e(5,13) + + do concurrent (i=1:5) + !$acc cache (d) ! { dg-error "" "TODO" { xfail *-*-* } } + !$acc cache (e) ! { dg-error "" "TODO" { xfail *-*-* } } + enddo +end diff --git a/gcc/testsuite/gfortran.dg/goacc/coarray.f95 b/gcc/testsuite/gfortran.dg/goacc/coarray.f95 index 932e1f7fd0d..f30917b8a9c 100644 --- a/gcc/testsuite/gfortran.dg/goacc/coarray.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/coarray.f95 @@ -24,7 +24,7 @@ contains !$acc end parallel loop !$acc parallel loop do i = 1,5 - !$acc cache (a) + !$acc cache (a) ! { dg-error "" "TODO" { xfail *-*-* } } enddo !$acc end parallel loop !$acc update device (a) diff --git a/gcc/testsuite/gfortran.dg/goacc/combined-directives.f90 b/gcc/testsuite/gfortran.dg/goacc/combined-directives.f90 index 42a447ad06b..abb5e6b6c3d 100644 --- a/gcc/testsuite/gfortran.dg/goacc/combined-directives.f90 +++ b/gcc/testsuite/gfortran.dg/goacc/combined-directives.f90 @@ -143,7 +143,8 @@ end subroutine test ! { dg-final { scan-tree-dump-times "acc loop private.i. private.j. vector" 2 "gimple" } } ! { dg-final { scan-tree-dump-times "acc loop private.i. private.j. seq" 2 "gimple" } } ! { dg-final { scan-tree-dump-times "acc loop private.i. private.j. auto" 2 "gimple" } } -! { dg-final { scan-tree-dump-times "acc loop private.i. private.j. tile.2, 3" 2 "gimple" } } +! XFAILed: OpenACC tile clauses are discarded during gimplification. +! { dg-final { scan-tree-dump-times "acc loop private.i. private.j. tile.2, 3" 2 "gimple" { xfail *-*-* } } } ! { dg-final { scan-tree-dump-times "acc loop private.i. independent" 2 "gimple" } } ! { dg-final { scan-tree-dump-times "private.z" 2 "gimple" } } ! { dg-final { scan-tree-dump-times "omp target oacc_\[^ \]+ map.force_tofrom:y" 2 "gimple" } } diff --git a/gcc/testsuite/gfortran.dg/goacc/cray-2.f95 b/gcc/testsuite/gfortran.dg/goacc/cray-2.f95 new file mode 100644 index 00000000000..51b79b53636 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/cray-2.f95 @@ -0,0 +1,56 @@ +! { dg-additional-options "-fcray-pointer" } +! See also cray.f95. + +program test + call oacc1 +contains + subroutine oacc1 + implicit none + integer :: i + real :: pointee + pointer (ptr, pointee) + !$acc declare device_resident (pointee) + !$acc declare device_resident (ptr) + !$acc data copy (pointee) ! { dg-error "Cray pointee" } + !$acc end data + !$acc data deviceptr (pointee) ! { dg-error "Cray pointee" } + !$acc end data + !$acc parallel private (pointee) ! { dg-error "Cray pointee" } + !$acc end parallel + !$acc host_data use_device (pointee) ! { dg-error "Cray pointee" } + !$acc end host_data + !$acc parallel loop reduction(+:pointee) ! { dg-error "Cray pointee" } + do i = 1,5 + enddo + !$acc end parallel loop + !$acc parallel loop + do i = 1,5 + !$acc cache (pointee) ! { dg-error "Cray pointee" } + enddo + !$acc end parallel loop + !$acc update device (pointee) ! { dg-error "Cray pointee" } + !$acc update host (pointee) ! { dg-error "Cray pointee" } + !$acc update self (pointee) ! { dg-error "Cray pointee" } + !$acc data copy (ptr) + !$acc end data + !$acc data deviceptr (ptr) ! { dg-error "Cray pointer" } + !$acc end data + !$acc parallel private (ptr) + !$acc end parallel + !$acc host_data use_device (ptr) ! { dg-error "Cray pointer" } + !$acc end host_data + !$acc parallel loop reduction(+:ptr) ! { dg-error "Cray pointer" } + do i = 1,5 + enddo + !$acc end parallel loop + !$acc parallel loop + do i = 1,5 + !TODO: This must fail, as in openacc-1_0-branch. + !$acc cache (ptr) ! { dg-error "" "TODO" { xfail *-*-* } } + enddo + !$acc end parallel loop + !$acc update device (ptr) + !$acc update host (ptr) + !$acc update self (ptr) + end subroutine oacc1 +end program test diff --git a/gcc/testsuite/gfortran.dg/goacc/cray.f95 b/gcc/testsuite/gfortran.dg/goacc/cray.f95 index a35ab0dc995..d6d531705a6 100644 --- a/gcc/testsuite/gfortran.dg/goacc/cray.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/cray.f95 @@ -1,5 +1,5 @@ -! { dg-do compile } ! { dg-additional-options "-fcray-pointer" } +! See also cray-2.f95. module test contains @@ -8,8 +8,8 @@ contains integer :: i real :: pointee pointer (ptr, pointee) - !$acc declare device_resident (pointee) - !$acc declare device_resident (ptr) + !$acc declare device_resident (pointee) + !$acc declare device_resident (ptr) !$acc data copy (pointee) ! { dg-error "Cray pointee" } !$acc end data !$acc data deviceptr (pointee) ! { dg-error "Cray pointee" } @@ -44,7 +44,8 @@ contains !$acc end parallel loop !$acc parallel loop do i = 1,5 - !$acc cache (ptr) ! TODO: This must fail, as in openacc-1_0-branch + !TODO: This must fail, as in openacc-1_0-branch. + !$acc cache (ptr) ! { dg-error "" "TODO" { xfail *-*-* } } enddo !$acc end parallel loop !$acc update device (ptr) diff --git a/gcc/testsuite/gfortran.dg/goacc/loop-1-2.f95 b/gcc/testsuite/gfortran.dg/goacc/loop-1-2.f95 new file mode 100644 index 00000000000..79665b948c3 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/loop-1-2.f95 @@ -0,0 +1,176 @@ +! See also loop-1.f95. + +program test + call test1 +contains + +subroutine test1 + integer :: i, j, k, b(10) + integer, dimension (30) :: a + double precision :: d + real :: r + i = 0 + !$acc loop + do 100 ! { dg-error "cannot be a DO WHILE or DO without loop control" } + if (i .gt. 0) exit ! { dg-error "EXIT statement" } + 100 i = i + 1 + i = 0 + !$acc loop + do ! { dg-error "cannot be a DO WHILE or DO without loop control" } + if (i .gt. 0) exit ! { dg-error "EXIT statement" } + i = i + 1 + end do + i = 0 + !$acc loop + do 200 while (i .lt. 4) ! { dg-error "cannot be a DO WHILE or DO without loop control" } + 200 i = i + 1 + !$acc loop + do while (i .lt. 8) ! { dg-error "cannot be a DO WHILE or DO without loop control" } + i = i + 1 + end do + !$acc loop + do 300 d = 1, 30, 6 + i = d + 300 a(i) = 1 + ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 32 } + ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 32 } + !$acc loop + do d = 1, 30, 5 + i = d + a(i) = 2 + end do + ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 38 } + ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 38 } + !$acc loop + do i = 1, 30 + if (i .eq. 16) exit ! { dg-error "EXIT statement" } + end do + !$acc loop + outer: do i = 1, 30 + do j = 5, 10 + if (i .eq. 6 .and. j .eq. 7) exit outer ! { dg-error "EXIT statement" } + end do + end do outer + last: do i = 1, 30 + end do last + + ! different types of loop are allowed + !$acc loop + do i = 1,10 + end do + !$acc loop + do 400, i = 1,10 +400 a(i) = i + + ! after loop directive must be loop + !$acc loop + a(1) = 1 ! { dg-error "Expected DO loop" } + do i = 1,10 + enddo + + ! combined directives may be used with/without end + !$acc parallel loop + do i = 1,10 + enddo + !$acc parallel loop + do i = 1,10 + enddo + !$acc end parallel loop + !$acc kernels loop + do i = 1,10 + enddo + !$acc kernels loop + do i = 1,10 + enddo + !$acc end kernels loop + + !$acc kernels loop reduction(max:i) + do i = 1,10 + enddo + !$acc kernels + !$acc loop reduction(max:i) + do i = 1,10 + enddo + !$acc end kernels + + !$acc parallel loop collapse(0) ! { dg-error "constant positive integer" } + do i = 1,10 + enddo + + !$acc parallel loop collapse(-1) ! { dg-error "constant positive integer" } + do i = 1,10 + enddo + + !$acc parallel loop collapse(i) ! { dg-error "Constant expression required" } + do i = 1,10 + enddo + + !$acc parallel loop collapse(4) ! { dg-error "not enough DO loops for collapsed" } + do i = 1, 3 + do j = 4, 6 + do k = 5, 7 + a(i+j-k) = i + j + k + end do + end do + end do + !$acc parallel loop collapse(2) + do i = 1, 5, 2 + do j = i + 1, 7, i ! { dg-error "collapsed loops don.t form rectangular iteration space" } + end do + end do + !$acc parallel loop collapse(2) + do i = 1, 3 + do j = 4, 6 + end do + end do + !$acc parallel loop collapse(2) + do i = 1, 3 + do j = 4, 6 + end do + k = 4 + end do + !$acc parallel loop collapse(3-1) + do i = 1, 3 + do j = 4, 6 + end do + k = 4 + end do + !$acc parallel loop collapse(1+1) + do i = 1, 3 + do j = 4, 6 + end do + k = 4 + end do + !$acc parallel loop collapse(2) + do i = 1, 3 + do ! { dg-error "cannot be a DO WHILE or DO without loop control" } + end do + end do + !$acc parallel loop collapse(2) + do i = 1, 3 + do r = 4, 6 + end do + ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 151 } + ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 151 } + end do + + ! Both seq and independent are not allowed + !$acc loop independent seq ! { dg-error "SEQ conflicts with INDEPENDENT" } + do i = 1,10 + enddo + + + !$acc cache (a(1:10)) ! { dg-error "ACC CACHE directive must be inside of loop" } + + do i = 1,10 + !$acc cache(a(i:i+1)) + enddo + + do i = 1,10 + !$acc cache(a(i:i+1)) + a(i) = i + !$acc cache(a(i+2:i+2+1)) + enddo + +end subroutine test1 +end program test diff --git a/gcc/testsuite/gfortran.dg/goacc/loop-1.f95 b/gcc/testsuite/gfortran.dg/goacc/loop-1.f95 index b5f9e038145..5f81b7a1d19 100644 --- a/gcc/testsuite/gfortran.dg/goacc/loop-1.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/loop-1.f95 @@ -1,8 +1,10 @@ +! See also loop-1-2.f95. + module test implicit none contains -subroutine test1 +subroutine test1 integer :: i, j, k, b(10) integer, dimension (30) :: a double precision :: d @@ -30,15 +32,15 @@ subroutine test1 do 300 d = 1, 30, 6 i = d 300 a(i) = 1 - ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 30 } - ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 30 } + ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 32 } + ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 32 } !$acc loop do d = 1, 30, 5 i = d a(i) = 2 end do - ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 36 } - ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 36 } + ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 38 } + ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 38 } !$acc loop do i = 1, 30 if (i .eq. 16) exit ! { dg-error "EXIT statement" } @@ -53,7 +55,7 @@ subroutine test1 end do last ! different types of loop are allowed - !$acc loop + !$acc loop do i = 1,10 end do !$acc loop @@ -65,8 +67,8 @@ subroutine test1 a(1) = 1 ! { dg-error "Expected DO loop" } do i = 1,10 enddo - - ! combined directives may be used with/without end + + ! combined directives may be used with/without end !$acc parallel loop do i = 1,10 enddo @@ -82,11 +84,11 @@ subroutine test1 enddo !$acc end kernels loop - !$acc kernels loop reduction(max:i) + !$acc kernels loop reduction(max:i) do i = 1,10 enddo - !$acc kernels - !$acc loop reduction(max:i) + !$acc kernels + !$acc loop reduction(max:i) do i = 1,10 enddo !$acc end kernels @@ -118,7 +120,7 @@ subroutine test1 end do !$acc parallel loop collapse(2) do i = 1, 3 - do j = 4, 6 + do j = 4, 6 end do end do !$acc parallel loop collapse(2) @@ -148,8 +150,8 @@ subroutine test1 do i = 1, 3 do r = 4, 6 end do - ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 149 } - ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 149 } + ! { dg-warning "Deleted feature: Loop variable at .1. must be integer" "" { target *-*-* } 151 } + ! { dg-error "ACC LOOP iteration variable must be of type integer" "" { target *-*-* } 151 } end do ! Both seq and independent are not allowed @@ -158,15 +160,16 @@ subroutine test1 enddo - !$acc cache (a) ! { dg-error "inside of loop" } + !$acc cache (a(1:10)) ! { dg-error "ACC CACHE directive must be inside of loop" } do i = 1,10 - !$acc cache(a) + !$acc cache(a(i:i+1)) enddo do i = 1,10 + !$acc cache(a(i:i+1)) a(i) = i - !$acc cache(a) + !$acc cache(a(i+2:i+2+1)) enddo end subroutine test1 diff --git a/gcc/testsuite/gfortran.dg/goacc/loop-3-2.f95 b/gcc/testsuite/gfortran.dg/goacc/loop-3-2.f95 new file mode 100644 index 00000000000..9be74a85919 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/loop-3-2.f95 @@ -0,0 +1,58 @@ +! { dg-additional-options "-std=f2008" } +! See also loop-3.f95. + +program test + call test1 +contains +subroutine test1 + implicit none + integer :: i, j + + ! !$acc end loop not required by spec + !$acc loop + do i = 1,5 + enddo + !$acc end loop ! { dg-warning "Redundant" } + + !$acc loop + do i = 1,5 + enddo + j = 1 + !$acc end loop ! { dg-error "Unexpected" } + + !$acc parallel + !$acc loop + do i = 1,5 + enddo + !$acc end parallel + !$acc end loop ! { dg-error "Unexpected" } + + ! OpenACC supports Fortran 2008 do concurrent statement + !$acc loop + do concurrent (i = 1:5) + end do + + !$acc loop + outer_loop: do i = 1, 5 + inner_loop: do j = 1,5 + if (i .eq. j) cycle outer_loop + if (i .ne. j) exit outer_loop ! { dg-error "EXIT statement" } + end do inner_loop + end do outer_loop + + outer_loop1: do i = 1, 5 + !$acc loop + inner_loop1: do j = 1,5 + if (i .eq. j) cycle outer_loop1 ! { dg-error "CYCLE statement" } + end do inner_loop1 + end do outer_loop1 + + !$acc loop collapse(2) + outer_loop2: do i = 1, 5 + inner_loop2: do j = 1,5 + if (i .eq. j) cycle outer_loop2 ! { dg-error "CYCLE statement" } + if (i .ne. j) exit outer_loop2 ! { dg-error "EXIT statement" } + end do inner_loop2 + end do outer_loop2 +end subroutine test1 +end program test diff --git a/gcc/testsuite/gfortran.dg/goacc/loop-3.f95 b/gcc/testsuite/gfortran.dg/goacc/loop-3.f95 index 2a866c79234..30930f404f3 100644 --- a/gcc/testsuite/gfortran.dg/goacc/loop-3.f95 +++ b/gcc/testsuite/gfortran.dg/goacc/loop-3.f95 @@ -1,10 +1,10 @@ -! { dg-do compile } ! { dg-additional-options "-std=f2008" } +! See also loop-3-2.f95. subroutine test1 implicit none integer :: i, j - + ! !$acc end loop not required by spec !$acc loop do i = 1,5 @@ -23,7 +23,7 @@ subroutine test1 enddo !$acc end parallel !$acc end loop ! { dg-error "Unexpected" } - + ! OpenACC supports Fortran 2008 do concurrent statement !$acc loop do concurrent (i = 1:5) @@ -35,7 +35,7 @@ subroutine test1 if (i .eq. j) cycle outer_loop if (i .ne. j) exit outer_loop ! { dg-error "EXIT statement" } end do inner_loop - end do outer_loop + end do outer_loop outer_loop1: do i = 1, 5 !$acc loop @@ -50,6 +50,5 @@ subroutine test1 if (i .eq. j) cycle outer_loop2 ! { dg-error "CYCLE statement" } if (i .ne. j) exit outer_loop2 ! { dg-error "EXIT statement" } end do inner_loop2 - end do outer_loop2 + end do outer_loop2 end subroutine test1 - diff --git a/gcc/testsuite/gfortran.dg/goacc/nested-function-1.f90 b/gcc/testsuite/gfortran.dg/goacc/nested-function-1.f90 new file mode 100644 index 00000000000..2fcaa400ee3 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/nested-function-1.f90 @@ -0,0 +1,93 @@ +! Exercise nested function decomposition, gcc/tree-nested.c. +! See gcc/testsuite/gcc.dg/goacc/nested-function-1.c for the C version. + +program main + integer, parameter :: N = 100 + integer :: nonlocal_arg + integer :: nonlocal_a(N) + integer :: nonlocal_i + integer :: nonlocal_j + + nonlocal_a (:) = 5 + nonlocal_arg = 5 + + call local () + call nonlocal () + +contains + + subroutine local () + integer :: local_i + integer :: local_arg + integer :: local_a(N) + integer :: local_j + + local_a (:) = 5 + local_arg = 5 + + !$acc kernels loop & + !$acc gang(num:local_arg) worker(local_arg) vector(local_arg) & + !$acc wait async(local_arg) + do local_i = 1, N + !$acc cache (local_a(local_i:local_i + 5)) + local_a(local_i) = 100 + !$acc loop seq tile(*) + do local_j = 1, N + enddo + !$acc loop auto independent tile(1) + do local_j = 1, N + enddo + enddo + !$acc end kernels loop + + !$acc kernels loop & + !$acc gang(static:local_arg) worker(local_arg) vector(local_arg) & + !$acc wait(local_arg, local_arg + 1, local_arg + 2) async + do local_i = 1, N + !$acc cache (local_a(local_i:local_i + 4)) + local_a(local_i) = 100 + !$acc loop seq tile(1) + do local_j = 1, N + enddo + !$acc loop auto independent tile(*) + do local_j = 1, N + enddo + enddo + !$acc end kernels loop + end subroutine local + + subroutine nonlocal () + nonlocal_a (:) = 5 + nonlocal_arg = 5 + + !$acc kernels loop & + !$acc gang(num:nonlocal_arg) worker(nonlocal_arg) vector(nonlocal_arg) & + !$acc wait async(nonlocal_arg) + do nonlocal_i = 1, N + !$acc cache (nonlocal_a(nonlocal_i:nonlocal_i + 3)) + nonlocal_a(nonlocal_i) = 100 + !$acc loop seq tile(2) + do nonlocal_j = 1, N + enddo + !$acc loop auto independent tile(3) + do nonlocal_j = 1, N + enddo + enddo + !$acc end kernels loop + + !$acc kernels loop & + !$acc gang(static:nonlocal_arg) worker(nonlocal_arg) vector(nonlocal_arg) & + !$acc wait(nonlocal_arg, nonlocal_arg + 1, nonlocal_arg + 2) async + do nonlocal_i = 1, N + !$acc cache (nonlocal_a(nonlocal_i:nonlocal_i + 2)) + nonlocal_a(nonlocal_i) = 100 + !$acc loop seq tile(*) + do nonlocal_j = 1, N + enddo + !$acc loop auto independent tile(*) + do nonlocal_j = 1, N + enddo + enddo + !$acc end kernels loop + end subroutine nonlocal +end program main diff --git a/gcc/testsuite/gfortran.dg/goacc/pr71704.f90 b/gcc/testsuite/gfortran.dg/goacc/pr71704.f90 new file mode 100644 index 00000000000..0235e85d42a --- /dev/null +++ b/gcc/testsuite/gfortran.dg/goacc/pr71704.f90 @@ -0,0 +1,60 @@ +! PR fortran/71704 +! { dg-do compile } + +real function f1 () +!$acc routine (f1) + f1 = 1 +end + +real function f2 (a) + integer a + !$acc enter data copyin(a) + f2 = 1 +end + +real function f3 (a) + integer a +!$acc enter data copyin(a) + f3 = 1 +end + +real function f4 () +!$acc wait + f4 = 1 +end + +real function f5 (a) + integer a +!$acc update device(a) + f5 = 1 +end + +real function f6 () +!$acc parallel +!$acc end parallel + f6 = 1 +end + +real function f7 () +!$acc kernels +!$acc end kernels + f7 = 1 +end + +real function f8 () +!$acc data +!$acc end data + f8 = 1 +end + +real function f9 () +!$acc host_data +!$acc end host_data + f8 = 1 +end + +real function f10 (a) + integer a +!$acc declare present (a) + f8 = 1 +end diff --git a/gcc/testsuite/gfortran.dg/goacc/subroutines.f90 b/gcc/testsuite/gfortran.dg/goacc/subroutines.f90 deleted file mode 100644 index 6cab798d458..00000000000 --- a/gcc/testsuite/gfortran.dg/goacc/subroutines.f90 +++ /dev/null @@ -1,73 +0,0 @@ -! Exercise how tree-nested.c handles gang, worker vector and seq. - -! { dg-do compile } - -program main - integer, parameter :: N = 100 - integer :: nonlocal_arg - integer :: nonlocal_a(N) - integer :: nonlocal_i - integer :: nonlocal_j - - nonlocal_a (:) = 5 - nonlocal_arg = 5 - - call local () - call nonlocal () - -contains - - subroutine local () - integer :: local_i - integer :: local_arg - integer :: local_a(N) - integer :: local_j - - local_a (:) = 5 - local_arg = 5 - - !$acc kernels loop gang(num:local_arg) worker(local_arg) vector(local_arg) - do local_i = 1, N - local_a(local_i) = 100 - !$acc loop seq - do local_j = 1, N - enddo - enddo - !$acc end kernels loop - - !$acc kernels loop gang(static:local_arg) worker(local_arg) & - !$acc vector(local_arg) - do local_i = 1, N - local_a(local_i) = 100 - !$acc loop seq - do local_j = 1, N - enddo - enddo - !$acc end kernels loop - end subroutine local - - subroutine nonlocal () - nonlocal_a (:) = 5 - nonlocal_arg = 5 - - !$acc kernels loop gang(num:nonlocal_arg) worker(nonlocal_arg) & - !$acc vector(nonlocal_arg) - do nonlocal_i = 1, N - nonlocal_a(nonlocal_i) = 100 - !$acc loop seq - do nonlocal_j = 1, N - enddo - enddo - !$acc end kernels loop - - !$acc kernels loop gang(static:nonlocal_arg) worker(nonlocal_arg) & - !$acc vector(nonlocal_arg) - do nonlocal_i = 1, N - nonlocal_a(nonlocal_i) = 100 - !$acc loop seq - do nonlocal_j = 1, N - enddo - enddo - !$acc end kernels loop - end subroutine nonlocal -end program main diff --git a/gcc/testsuite/gfortran.dg/gomp/pr71687.f90 b/gcc/testsuite/gfortran.dg/gomp/pr71687.f90 new file mode 100644 index 00000000000..3971263752e --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr71687.f90 @@ -0,0 +1,11 @@ +! PR fortran/71687 +! { dg-do compile } +! { dg-additional-options "-fstack-arrays -O2" } + +subroutine s (n, x) + integer :: n + real :: x(n) +!$omp parallel + x(1:n) = x(n:1:-1) +!$omp end parallel +end diff --git a/gcc/testsuite/gfortran.dg/gomp/pr71704.f90 b/gcc/testsuite/gfortran.dg/gomp/pr71704.f90 new file mode 100644 index 00000000000..5c1c003ca57 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr71704.f90 @@ -0,0 +1,58 @@ +! PR fortran/71704 +! { dg-do compile } + +real function f0 () +!$omp declare simd (f0) + f0 = 1 +end + +real function f1 () +!$omp declare target (f1) + f1 = 1 +end + +real function f2 () +!$omp declare reduction (foo : integer : omp_out = omp_out + omp_in) & +!$omp & initializer (omp_priv = 0) + f2 = 1 +end + +real function f3 () + real, save :: t +!$omp threadprivate (t) + f3 = 1 +end + +real function f4 () +!$omp taskwait + f4 = 1 +end + +real function f5 () +!$omp barrier + f5 = 1 +end + +real function f6 () +!$omp parallel +!$omp end parallel + f6 = 1 +end + +real function f7 () +!$omp single +!$omp end single + f7 = 1 +end + +real function f8 () +!$omp critical +!$omp end critical + f8 = 1 +end + +real function f9 () +!$omp critical +!$omp end critical + f9 = 1 +end diff --git a/gcc/testsuite/gfortran.dg/gomp/pr71705.f90 b/gcc/testsuite/gfortran.dg/gomp/pr71705.f90 new file mode 100644 index 00000000000..4813aacfdc3 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr71705.f90 @@ -0,0 +1,7 @@ +! PR fortran/71705 +! { dg-do compile } + + real :: x + x = 0.0 + !$omp target update to(x) +end diff --git a/gcc/testsuite/gfortran.dg/gomp/pr71758.f90 b/gcc/testsuite/gfortran.dg/gomp/pr71758.f90 new file mode 100644 index 00000000000..47215ba5cd9 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/pr71758.f90 @@ -0,0 +1,10 @@ +! PR middle-end/71758 + +subroutine pr71758 (p) + integer(8) :: i + integer :: p(20) + i = 0 + !$omp target device(i) + !$omp end target + !$omp target update to(p(1:1)) device(i) +end subroutine diff --git a/gcc/testsuite/gfortran.dg/graphite/pr38083.f90 b/gcc/testsuite/gfortran.dg/graphite/pr38083.f90 index da8c3cc7914..34d6ca83ad9 100644 --- a/gcc/testsuite/gfortran.dg/graphite/pr38083.f90 +++ b/gcc/testsuite/gfortran.dg/graphite/pr38083.f90 @@ -8,7 +8,7 @@ SUBROUTINE IVSORT (IL,IH,NSEGS,IOUNIT) 10 IF (IL .GE. IH) GO TO 80 20 NSEGS = (IH + IL) / 2 IF (NSEGS .GT. MAXSGS) THEN - WRITE (IOUNIT),MAXSGS + WRITE (IOUNIT) MAXSGS ENDIF 80 NSEGS = NSEGS - 1 90 IF (IH - IL .GE. 11) GO TO 20 diff --git a/gcc/testsuite/gfortran.dg/guality/pr41558.f90 b/gcc/testsuite/gfortran.dg/guality/pr41558.f90 index 8a84de48a30..840b2384012 100644 --- a/gcc/testsuite/gfortran.dg/guality/pr41558.f90 +++ b/gcc/testsuite/gfortran.dg/guality/pr41558.f90 @@ -5,7 +5,7 @@ subroutine f (s) character(len=3) :: s - write (*,*), s ! { dg-final { gdb-test 7 "s" "'foo'" } } + write (*,*) s ! { dg-final { gdb-test 7 "s" "'foo'" } } end call f ('foo') end diff --git a/gcc/testsuite/gfortran.dg/integer_exponentiation_6.F90 b/gcc/testsuite/gfortran.dg/integer_exponentiation_6.F90 index 55c2543e705..4236ee61b65 100644 --- a/gcc/testsuite/gfortran.dg/integer_exponentiation_6.F90 +++ b/gcc/testsuite/gfortran.dg/integer_exponentiation_6.F90 @@ -1,4 +1,4 @@ ! { dg-options "-fno-range-check" } program test - write (*), (2_8 ** 64009999_8) / 2 + write (*,*) (2_8 ** 64009999_8) / 2 end program test diff --git a/gcc/testsuite/gfortran.dg/pr70673.f90 b/gcc/testsuite/gfortran.dg/pr70673.f90 new file mode 100644 index 00000000000..67856e0332e --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr70673.f90 @@ -0,0 +1,25 @@ +! { dg-do run } +! +! Test the fix for PR70673 +! +! Contributed by David Kinniburgh <davidgkinniburgh@yahoo.co.uk> +! +module m +contains + subroutine s(inp) + character(*), intent(in) :: inp + character(:), allocatable :: a + a = a ! This used to ICE. + a = inp + a = a ! This used to ICE too + if ((len (a) .ne. 5) .or. (a .ne. "hello")) call abort + a = a(2:3) ! Make sure that temporary creation is not broken. + if ((len (a) .ne. 2) .or. (a .ne. "el")) call abort + deallocate (a) + a = a ! This would ICE too. + end subroutine s +end module m + + use m + call s("hello") +end diff --git a/gcc/testsuite/gnat.dg/case_character.adb b/gcc/testsuite/gnat.dg/case_character.adb new file mode 100644 index 00000000000..59c9b66987d --- /dev/null +++ b/gcc/testsuite/gnat.dg/case_character.adb @@ -0,0 +1,19 @@ +-- { dg-do run } + +procedure Case_Character is + + function Test (C : Character) return Integer is + begin + case C is + when ASCII.HT | ' ' .. Character'Last => return 1; + when others => return 0; + end case; + end; + +begin + + if Test ('A') /= 1 then + raise Program_Error; + end if; + +end; diff --git a/gcc/testsuite/gnat.dg/renaming10.adb b/gcc/testsuite/gnat.dg/renaming10.adb new file mode 100644 index 00000000000..07d4312b060 --- /dev/null +++ b/gcc/testsuite/gnat.dg/renaming10.adb @@ -0,0 +1,12 @@ +-- { dg-do compile } + +package body Renaming10 is + + function F (Input : Rec) return Natural is + Position : Natural renames Input.Position; + Index : Natural renames Natural'Succ(Position); + begin + return Index; + end; + +end Renaming10; diff --git a/gcc/testsuite/gnat.dg/renaming10.ads b/gcc/testsuite/gnat.dg/renaming10.ads new file mode 100644 index 00000000000..aeb9fc1a201 --- /dev/null +++ b/gcc/testsuite/gnat.dg/renaming10.ads @@ -0,0 +1,9 @@ +package Renaming10 is + + type Rec is record + Position : Natural; + end record; + + function F (Input : Rec) return Natural; + +end Renaming10; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index df226b0f8a1..9310242abf4 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2309,6 +2309,40 @@ proc check_effective_target_has_q_floating_suffix { } { float dummy = 1.0q; } "$opts"] } + +# Return 1 if the target supports __float128, +# 0 otherwise. + +proc check_effective_target___float128 { } { + if { [istarget powerpc*-*-*] } { + return [check_ppc_float128_sw_available] + } + if { [istarget ia64-*-*] + || [istarget i?86-*-*] + || [istarget x86_64-*-*] } { + return 1 + } + return 0 +} + +proc add_options_for___float128 { flags } { + if { [istarget powerpc*-*-*] } { + return "$flags -mfloat128 -mvsx" + } + return "$flags" +} + +# Return 1 if the target supports any special run-time requirements +# for __float128 or _Float128, +# 0 otherwise. + +proc check_effective_target_base_quadfloat_support { } { + if { [istarget powerpc*-*-*] } { + return [check_vsx_hw_available] + } + return 1 +} + # Return 1 if the target supports compiling fixed-point, # 0 otherwise. diff --git a/gcc/tree-nested.c b/gcc/tree-nested.c index 8563687e9e5..3507d32c87a 100644 --- a/gcc/tree-nested.c +++ b/gcc/tree-nested.c @@ -1114,6 +1114,8 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_GANG: case OMP_CLAUSE_WORKER: case OMP_CLAUSE_VECTOR: + case OMP_CLAUSE_ASYNC: + case OMP_CLAUSE_WAIT: /* Several OpenACC clauses have optional arguments. Check if they are present. */ if (OMP_CLAUSE_OPERAND (clause, 0)) @@ -1197,8 +1199,22 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_SIMD: case OMP_CLAUSE_DEFAULTMAP: case OMP_CLAUSE_SEQ: + case OMP_CLAUSE_INDEPENDENT: + case OMP_CLAUSE_AUTO: break; + case OMP_CLAUSE_TILE: + /* OpenACC tile clauses are discarded during gimplification, so we + don't expect to see anything here. */ + gcc_unreachable (); + + case OMP_CLAUSE__CACHE_: + /* These clauses belong to the OpenACC cache directive, which is + discarded during gimplification, so we don't expect to see + anything here. */ + gcc_unreachable (); + + case OMP_CLAUSE_DEVICE_RESIDENT: default: gcc_unreachable (); } @@ -1332,7 +1348,7 @@ convert_nonlocal_reference_stmt (gimple_stmt_iterator *gsi, bool *handled_ops_p, { wi->val_only = true; wi->is_lhs = false; - *handled_ops_p = true; + *handled_ops_p = false; return NULL_TREE; } break; @@ -1790,6 +1806,8 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_GANG: case OMP_CLAUSE_WORKER: case OMP_CLAUSE_VECTOR: + case OMP_CLAUSE_ASYNC: + case OMP_CLAUSE_WAIT: /* Several OpenACC clauses have optional arguments. Check if they are present. */ if (OMP_CLAUSE_OPERAND (clause, 0)) @@ -1878,8 +1896,22 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) case OMP_CLAUSE_SIMD: case OMP_CLAUSE_DEFAULTMAP: case OMP_CLAUSE_SEQ: + case OMP_CLAUSE_INDEPENDENT: + case OMP_CLAUSE_AUTO: break; + case OMP_CLAUSE_TILE: + /* OpenACC tile clauses are discarded during gimplification, so we + don't expect to see anything here. */ + gcc_unreachable (); + + case OMP_CLAUSE__CACHE_: + /* These clauses belong to the OpenACC cache directive, which is + discarded during gimplification, so we don't expect to see + anything here. */ + gcc_unreachable (); + + case OMP_CLAUSE_DEVICE_RESIDENT: default: gcc_unreachable (); } diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c index 083f1ee413d..494a7fb9364 100644 --- a/gcc/tree-ssa-sccvn.c +++ b/gcc/tree-ssa-sccvn.c @@ -1976,11 +1976,7 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *vr_, /* We need to pre-pend vr->operands[0..i] to rhs. */ vec<vn_reference_op_s> old = vr->operands; if (i + 1 + rhs.length () > vr->operands.length ()) - { - vr->operands.safe_grow (i + 1 + rhs.length ()); - if (old == shared_lookup_references) - shared_lookup_references = vr->operands; - } + vr->operands.safe_grow (i + 1 + rhs.length ()); else vr->operands.truncate (i + 1 + rhs.length ()); FOR_EACH_VEC_ELT (rhs, j, vro) @@ -2131,8 +2127,7 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *vr_, { vec<vn_reference_op_s> old = vr->operands; vr->operands.safe_grow_cleared (2); - if (old == shared_lookup_references - && vr->operands != old) + if (old == shared_lookup_references) shared_lookup_references = vr->operands; } else diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index d27b60754d3..403464db256 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -859,6 +859,65 @@ find_equal_ptrs (tree ptr, int idx) } } +/* Return true if STMT is a call to a builtin function with the right + arguments and attributes that should be considered for optimization + by this pass. */ + +static bool +valid_builtin_call (gimple *stmt) +{ + if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL)) + return false; + + tree callee = gimple_call_fndecl (stmt); + switch (DECL_FUNCTION_CODE (callee)) + { + case BUILT_IN_MEMCMP: + case BUILT_IN_STRCHR: + case BUILT_IN_STRCHR_CHKP: + case BUILT_IN_STRLEN: + case BUILT_IN_STRLEN_CHKP: + /* The above functions should be pure. Punt if they aren't. */ + if (gimple_vdef (stmt) || gimple_vuse (stmt) == NULL_TREE) + return false; + break; + + case BUILT_IN_CALLOC: + case BUILT_IN_MALLOC: + case BUILT_IN_MEMCPY: + case BUILT_IN_MEMCPY_CHK: + case BUILT_IN_MEMCPY_CHKP: + case BUILT_IN_MEMCPY_CHK_CHKP: + case BUILT_IN_MEMPCPY: + case BUILT_IN_MEMPCPY_CHK: + case BUILT_IN_MEMPCPY_CHKP: + case BUILT_IN_MEMPCPY_CHK_CHKP: + case BUILT_IN_MEMSET: + case BUILT_IN_STPCPY: + case BUILT_IN_STPCPY_CHK: + case BUILT_IN_STPCPY_CHKP: + case BUILT_IN_STPCPY_CHK_CHKP: + case BUILT_IN_STRCAT: + case BUILT_IN_STRCAT_CHK: + case BUILT_IN_STRCAT_CHKP: + case BUILT_IN_STRCAT_CHK_CHKP: + case BUILT_IN_STRCPY: + case BUILT_IN_STRCPY_CHK: + case BUILT_IN_STRCPY_CHKP: + case BUILT_IN_STRCPY_CHK_CHKP: + /* The above functions should be neither const nor pure. Punt if they + aren't. */ + if (gimple_vdef (stmt) == NULL_TREE || gimple_vuse (stmt) == NULL_TREE) + return false; + break; + + default: + break; + } + + return true; +} + /* If the last .MEM setter statement before STMT is memcpy (x, y, strlen (y) + 1), the only .MEM use of it is STMT and STMT is known to overwrite x[strlen (x)], adjust the last memcpy to @@ -934,7 +993,7 @@ adjust_last_stmt (strinfo *si, gimple *stmt, bool is_strcat) return; } - if (!gimple_call_builtin_p (last.stmt, BUILT_IN_NORMAL)) + if (!valid_builtin_call (last.stmt)) return; callee = gimple_call_fndecl (last.stmt); @@ -1810,7 +1869,7 @@ handle_builtin_memset (gimple_stmt_iterator *gsi) if (!stmt1 || !is_gimple_call (stmt1)) return true; tree callee1 = gimple_call_fndecl (stmt1); - if (!gimple_call_builtin_p (stmt1, BUILT_IN_NORMAL)) + if (!valid_builtin_call (stmt1)) return true; enum built_in_function code1 = DECL_FUNCTION_CODE (callee1); tree size = gimple_call_arg (stmt2, 2); @@ -2055,7 +2114,7 @@ strlen_optimize_stmt (gimple_stmt_iterator *gsi) if (is_gimple_call (stmt)) { tree callee = gimple_call_fndecl (stmt); - if (gimple_call_builtin_p (stmt, BUILT_IN_NORMAL)) + if (valid_builtin_call (stmt)) switch (DECL_FUNCTION_CODE (callee)) { case BUILT_IN_STRLEN: diff --git a/gcc/tree-ssa-tail-merge.c b/gcc/tree-ssa-tail-merge.c index e95879fb8aa..3df41fd08fc 100644 --- a/gcc/tree-ssa-tail-merge.c +++ b/gcc/tree-ssa-tail-merge.c @@ -538,6 +538,9 @@ same_succ::equal (const same_succ *e1, const same_succ *e2) gimple *s1, *s2; basic_block bb1, bb2; + if (e1 == e2) + return 1; + if (e1->hashval != e2->hashval) return 0; diff --git a/gcc/tree-ssa-uninit.c b/gcc/tree-ssa-uninit.c index ea3ceb8f101..e644e6aee03 100644 --- a/gcc/tree-ssa-uninit.c +++ b/gcc/tree-ssa-uninit.c @@ -133,6 +133,29 @@ warn_uninit (enum opt_code wc, tree t, tree expr, tree var, if (!has_undefined_value_p (t)) return; + /* Anonymous SSA_NAMEs shouldn't be uninitialized, but ssa_undefined_value_p + can return true if the def stmt of anonymous SSA_NAME is COMPLEX_EXPR + created for conversion from scalar to complex. Use the underlying var of + the COMPLEX_EXPRs real part in that case. See PR71581. */ + if (expr == NULL_TREE + && var == NULL_TREE + && SSA_NAME_VAR (t) == NULL_TREE + && is_gimple_assign (SSA_NAME_DEF_STMT (t)) + && gimple_assign_rhs_code (SSA_NAME_DEF_STMT (t)) == COMPLEX_EXPR) + { + tree v = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (t)); + if (TREE_CODE (v) == SSA_NAME + && has_undefined_value_p (v) + && zerop (gimple_assign_rhs2 (SSA_NAME_DEF_STMT (t)))) + { + expr = SSA_NAME_VAR (v); + var = expr; + } + } + + if (expr == NULL_TREE) + return; + /* TREE_NO_WARNING either means we already warned, or the front end wishes to suppress the warning. */ if ((context diff --git a/gcc/tree-ssa.c b/gcc/tree-ssa.c index 6a16d268e69..a7c87332519 100644 --- a/gcc/tree-ssa.c +++ b/gcc/tree-ssa.c @@ -1342,6 +1342,18 @@ non_rewritable_lvalue_p (tree lhs) tree decl = TREE_OPERAND (TREE_OPERAND (lhs, 0), 0); if (DECL_P (decl) && DECL_SIZE (decl) == TYPE_SIZE (TREE_TYPE (lhs)) + /* If the dynamic type of the decl has larger precision than + the decl itself we can't use the decls type for SSA rewriting. */ + && ((! INTEGRAL_TYPE_P (TREE_TYPE (decl)) + || compare_tree_int (DECL_SIZE (decl), + TYPE_PRECISION (TREE_TYPE (decl))) == 0) + || (INTEGRAL_TYPE_P (TREE_TYPE (lhs)) + && (TYPE_PRECISION (TREE_TYPE (decl)) + >= TYPE_PRECISION (TREE_TYPE (lhs))))) + /* Make sure we are not re-writing non-float copying into float + copying as that can incur normalization. */ + && (! FLOAT_TYPE_P (TREE_TYPE (decl)) + || types_compatible_p (TREE_TYPE (lhs), TREE_TYPE (decl))) && (TREE_THIS_VOLATILE (decl) == TREE_THIS_VOLATILE (lhs))) return false; } @@ -1590,9 +1602,16 @@ execute_update_addresses_taken (void) if (gimple_assign_lhs (stmt) != lhs && !useless_type_conversion_p (TREE_TYPE (lhs), TREE_TYPE (rhs))) - rhs = fold_build1 (VIEW_CONVERT_EXPR, - TREE_TYPE (lhs), rhs); - + { + if (gimple_clobber_p (stmt)) + { + rhs = build_constructor (TREE_TYPE (lhs), NULL); + TREE_THIS_VOLATILE (rhs) = 1; + } + else + rhs = fold_build1 (VIEW_CONVERT_EXPR, + TREE_TYPE (lhs), rhs); + } if (gimple_assign_lhs (stmt) != lhs) gimple_assign_set_lhs (stmt, lhs); diff --git a/gcc/tree-vect-data-refs.c b/gcc/tree-vect-data-refs.c index 7652e216eb6..b472e2ee49b 100644 --- a/gcc/tree-vect-data-refs.c +++ b/gcc/tree-vect-data-refs.c @@ -692,6 +692,7 @@ vect_compute_data_ref_alignment (struct data_reference *dr) tree base, base_addr; tree misalign = NULL_TREE; tree aligned_to; + tree step; unsigned HOST_WIDE_INT alignment; if (dump_enabled_p ()) @@ -822,16 +823,20 @@ vect_compute_data_ref_alignment (struct data_reference *dr) DR_VECT_AUX (dr)->base_element_aligned = true; } + if (loop && nested_in_vect_loop_p (loop, stmt)) + step = STMT_VINFO_DR_STEP (stmt_info); + else + step = DR_STEP (dr); /* If this is a backward running DR then first access in the larger vectype actually is N-1 elements before the address in the DR. Adjust misalign accordingly. */ - if (tree_int_cst_sgn (DR_STEP (dr)) < 0) + if (tree_int_cst_sgn (step) < 0) { tree offset = ssize_int (TYPE_VECTOR_SUBPARTS (vectype) - 1); /* DR_STEP(dr) is the same as -TYPE_SIZE of the scalar type, otherwise we wouldn't be here. */ - offset = fold_build2 (MULT_EXPR, ssizetype, offset, DR_STEP (dr)); - /* PLUS because DR_STEP was negative. */ + offset = fold_build2 (MULT_EXPR, ssizetype, offset, step); + /* PLUS because STEP was negative. */ misalign = size_binop (PLUS_EXPR, misalign, offset); } @@ -2751,7 +2756,7 @@ vect_analyze_data_ref_accesses (vec_info *vinfo) /* Sorting has ensured that DR_INIT (dra) <= DR_INIT (drb). */ HOST_WIDE_INT init_a = TREE_INT_CST_LOW (DR_INIT (dra)); HOST_WIDE_INT init_b = TREE_INT_CST_LOW (DR_INIT (drb)); - gcc_assert (init_a < init_b); + gcc_assert (init_a <= init_b); /* If init_b == init_a + the size of the type * k, we have an interleaving, and DRA is accessed before DRB. */ diff --git a/gcc/tree-vect-slp.c b/gcc/tree-vect-slp.c index d71384881b7..b6a6fde40fb 100644 --- a/gcc/tree-vect-slp.c +++ b/gcc/tree-vect-slp.c @@ -3050,7 +3050,7 @@ vect_get_constant_vectors (tree op, slp_tree slp_node, if (integer_zerop (op)) op = build_int_cst (TREE_TYPE (vector_type), 0); else if (integer_onep (op)) - op = build_int_cst (TREE_TYPE (vector_type), 1); + op = build_all_ones_cst (TREE_TYPE (vector_type)); else gcc_unreachable (); } @@ -3065,8 +3065,14 @@ vect_get_constant_vectors (tree op, slp_tree slp_node, gimple *init_stmt; if (VECTOR_BOOLEAN_TYPE_P (vector_type)) { + tree true_val + = build_all_ones_cst (TREE_TYPE (vector_type)); + tree false_val + = build_zero_cst (TREE_TYPE (vector_type)); gcc_assert (INTEGRAL_TYPE_P (TREE_TYPE (op))); - init_stmt = gimple_build_assign (new_temp, NOP_EXPR, op); + init_stmt = gimple_build_assign (new_temp, COND_EXPR, + op, true_val, + false_val); } else { diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c index d5a237d81c5..6149f08c21d 100644 --- a/gcc/tree-vect-stmts.c +++ b/gcc/tree-vect-stmts.c @@ -1256,10 +1256,11 @@ vect_init_vector (gimple *stmt, tree val, tree type, gimple_stmt_iterator *gsi) gimple *init_stmt; tree new_temp; - if (TREE_CODE (type) == VECTOR_TYPE - && TREE_CODE (TREE_TYPE (val)) != VECTOR_TYPE) + /* We abuse this function to push sth to a SSA name with initial 'val'. */ + if (! useless_type_conversion_p (type, TREE_TYPE (val))) { - if (!types_compatible_p (TREE_TYPE (type), TREE_TYPE (val))) + gcc_assert (TREE_CODE (type) == VECTOR_TYPE); + if (! types_compatible_p (TREE_TYPE (type), TREE_TYPE (val))) { /* Scalar boolean value should be transformed into all zeros or all ones value before building a vector. */ @@ -1284,7 +1285,13 @@ vect_init_vector (gimple *stmt, tree val, tree type, gimple_stmt_iterator *gsi) else { new_temp = make_ssa_name (TREE_TYPE (type)); - init_stmt = gimple_build_assign (new_temp, NOP_EXPR, val); + if (! INTEGRAL_TYPE_P (TREE_TYPE (val))) + init_stmt = gimple_build_assign (new_temp, + fold_build1 (VIEW_CONVERT_EXPR, + TREE_TYPE (type), + val)); + else + init_stmt = gimple_build_assign (new_temp, NOP_EXPR, val); vect_init_vector_1 (stmt, init_stmt, gsi); val = new_temp; } @@ -5079,11 +5086,8 @@ vectorizable_operation (gimple *stmt, gimple_stmt_iterator *gsi, vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL, slp_node, -1); if (op_type == ternary_op) - { - vec_oprnds2.create (1); - vec_oprnds2.quick_push (vect_get_vec_def_for_operand (op2, - stmt)); - } + vect_get_vec_defs (op2, NULL_TREE, stmt, &vec_oprnds2, NULL, + slp_node, -1); } else { diff --git a/gcc/tree-vrp.c b/gcc/tree-vrp.c index f21a853c552..c68c84ea68c 100644 --- a/gcc/tree-vrp.c +++ b/gcc/tree-vrp.c @@ -2990,7 +2990,8 @@ extract_range_from_binary_expr_1 (value_range *vr, and divisor are available. */ if (vr1.type == VR_RANGE && !symbolic_range_p (&vr0) - && !symbolic_range_p (&vr1)) + && !symbolic_range_p (&vr1) + && compare_values (vr1.max, zero) != 0) min = int_const_binop (code, vr0.min, vr1.max); else min = zero; diff --git a/gcc/tree.c b/gcc/tree.c index 9aa2022ba4b..57587cc0152 100644 --- a/gcc/tree.c +++ b/gcc/tree.c @@ -5074,7 +5074,7 @@ attribute_value_equal (const_tree attr1, const_tree attr2) && TREE_CODE (TREE_VALUE (attr2)) == TREE_LIST) { /* Handle attribute format. */ - if (is_attribute_p ("format", TREE_PURPOSE (attr1))) + if (is_attribute_p ("format", get_attribute_name (attr1))) { attr1 = TREE_VALUE (attr1); attr2 = TREE_VALUE (attr2); diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index f1ae9fef698..934cddf8cfa 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,15 @@ +2016-07-14 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2016-07-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/_divkc3.c: New. + * config/rs6000/_mulkc3.c: New. + * config/rs6000/quad-float128.h: Define TFtype; declare _mulkc3 + and _divkc3. + * config/rs6000/t-float128: Add _mulkc3 and _divkc3 to + fp128_ppc_funcs. + 2016-05-17 Sebastian Huber <sebastian.huber@embedded-brains.de> Backport from mainline diff --git a/libgcc/config/rs6000/_divkc3.c b/libgcc/config/rs6000/_divkc3.c new file mode 100644 index 00000000000..9b9afd0a7b1 --- /dev/null +++ b/libgcc/config/rs6000/_divkc3.c @@ -0,0 +1,64 @@ +typedef float KFtype __attribute__ ((mode (KF))); +typedef __complex float KCtype __attribute__ ((mode (KC))); + +#define COPYSIGN(x,y) __builtin_copysignq (x, y) +#define INFINITY __builtin_infq () +#define FABS __builtin_fabsq +#define isnan __builtin_isnan +#define isinf __builtin_isinf +#define isfinite __builtin_isfinite + +KCtype +__divkc3 (KFtype a, KFtype b, KFtype c, KFtype d) +{ + KFtype denom, ratio, x, y; + KCtype res; + + /* ??? We can get better behavior from logarithmic scaling instead of + the division. But that would mean starting to link libgcc against + libm. We could implement something akin to ldexp/frexp as gcc builtins + fairly easily... */ + if (FABS (c) < FABS (d)) + { + ratio = c / d; + denom = (c * ratio) + d; + x = ((a * ratio) + b) / denom; + y = ((b * ratio) - a) / denom; + } + else + { + ratio = d / c; + denom = (d * ratio) + c; + x = ((b * ratio) + a) / denom; + y = (b - (a * ratio)) / denom; + } + + /* Recover infinities and zeros that computed as NaN+iNaN; the only cases + are nonzero/zero, infinite/finite, and finite/infinite. */ + if (isnan (x) && isnan (y)) + { + if (c == 0.0 && d == 0.0 && (!isnan (a) || !isnan (b))) + { + x = COPYSIGN (INFINITY, c) * a; + y = COPYSIGN (INFINITY, c) * b; + } + else if ((isinf (a) || isinf (b)) && isfinite (c) && isfinite (d)) + { + a = COPYSIGN (isinf (a) ? 1 : 0, a); + b = COPYSIGN (isinf (b) ? 1 : 0, b); + x = INFINITY * (a * c + b * d); + y = INFINITY * (b * c - a * d); + } + else if ((isinf (c) || isinf (d)) && isfinite (a) && isfinite (b)) + { + c = COPYSIGN (isinf (c) ? 1 : 0, c); + d = COPYSIGN (isinf (d) ? 1 : 0, d); + x = 0.0 * (a * c + b * d); + y = 0.0 * (b * c - a * d); + } + } + + __real__ res = x; + __imag__ res = y; + return res; +} diff --git a/libgcc/config/rs6000/_mulkc3.c b/libgcc/config/rs6000/_mulkc3.c new file mode 100644 index 00000000000..f89bf8c6368 --- /dev/null +++ b/libgcc/config/rs6000/_mulkc3.c @@ -0,0 +1,69 @@ +typedef float KFtype __attribute__ ((mode (KF))); +typedef __complex float KCtype __attribute__ ((mode (KC))); + +#define COPYSIGN(x,y) __builtin_copysignq (x, y) +#define INFINITY __builtin_infq () +#define isnan __builtin_isnan +#define isinf __builtin_isinf + +KCtype +__mulkc3 (KFtype a, KFtype b, KFtype c, KFtype d) +{ + KFtype ac, bd, ad, bc, x, y; + KCtype res; + + ac = a * c; + bd = b * d; + ad = a * d; + bc = b * c; + + x = ac - bd; + y = ad + bc; + + if (isnan (x) && isnan (y)) + { + /* Recover infinities that computed as NaN + iNaN. */ + _Bool recalc = 0; + if (isinf (a) || isinf (b)) + { + /* z is infinite. "Box" the infinity and change NaNs in + the other factor to 0. */ + a = COPYSIGN (isinf (a) ? 1 : 0, a); + b = COPYSIGN (isinf (b) ? 1 : 0, b); + if (isnan (c)) c = COPYSIGN (0, c); + if (isnan (d)) d = COPYSIGN (0, d); + recalc = 1; + } + if (isinf (c) || isinf (d)) + { + /* w is infinite. "Box" the infinity and change NaNs in + the other factor to 0. */ + c = COPYSIGN (isinf (c) ? 1 : 0, c); + d = COPYSIGN (isinf (d) ? 1 : 0, d); + if (isnan (a)) a = COPYSIGN (0, a); + if (isnan (b)) b = COPYSIGN (0, b); + recalc = 1; + } + if (!recalc + && (isinf (ac) || isinf (bd) + || isinf (ad) || isinf (bc))) + { + /* Recover infinities from overflow by changing NaNs to 0. */ + if (isnan (a)) a = COPYSIGN (0, a); + if (isnan (b)) b = COPYSIGN (0, b); + if (isnan (c)) c = COPYSIGN (0, c); + if (isnan (d)) d = COPYSIGN (0, d); + recalc = 1; + } + if (recalc) + { + x = INFINITY * (a * c - b * d); + y = INFINITY * (a * d + b * c); + } + } + + __real__ res = x; + __imag__ res = y; + return res; +} + diff --git a/libgcc/config/rs6000/quad-float128.h b/libgcc/config/rs6000/quad-float128.h index 62d198db20d..244a0475255 100644 --- a/libgcc/config/rs6000/quad-float128.h +++ b/libgcc/config/rs6000/quad-float128.h @@ -33,6 +33,10 @@ This define forces it to use KFmode (aka, ieee 128-bit floating point). */ #define TF KF +/* We also need TCtype to represent complex ieee 128-bit float for + __mulkc3 and __divkc3. */ +typedef __complex float TCtype __attribute__ ((mode (KC))); + /* Force the use of the VSX instruction set. */ #if defined(_ARCH_PPC) && (!defined(__VSX__) || !defined(__FLOAT128__)) #pragma GCC target ("vsx,float128") @@ -154,6 +158,10 @@ extern TFtype __floatundikf (UDItype_ppc); extern IBM128_TYPE __extendkftf2 (TFtype); extern TFtype __trunctfkf2 (IBM128_TYPE); +/* Complex __float128 built on __float128 interfaces. */ +extern TCtype __mulkc3 (TFtype, TFtype, TFtype, TFtype); +extern TCtype __divkc3 (TFtype, TFtype, TFtype, TFtype); + /* Implementation of conversions between __ibm128 and __float128, to allow the same code to be used on systems with IEEE 128-bit emulation and with IEEE 128-bit hardware support. */ diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128 index 82dab3639ea..2c52ca64b65 100644 --- a/libgcc/config/rs6000/t-float128 +++ b/libgcc/config/rs6000/t-float128 @@ -25,7 +25,7 @@ fp128_softfp_obj = $(fp128_softfp_static_obj) $(fp128_softfp_shared_obj) # New functions for software emulation fp128_ppc_funcs = floattikf floatuntikf fixkfti fixunskfti \ extendkftf2-sw trunctfkf2-sw \ - sfp-exceptions + sfp-exceptions _mulkc3 _divkc3 fp128_ppc_src = $(addprefix $(srcdir)/config/rs6000/,$(addsuffix \ .c,$(fp128_ppc_funcs))) diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog index 7b124eb562e..e8d865f7eac 100644 --- a/libgomp/ChangeLog +++ b/libgomp/ChangeLog @@ -1,3 +1,41 @@ +2016-07-02 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-07-01 Jakub Jelinek <jakub@redhat.com> + + PR fortran/71717 + * testsuite/libgomp.fortran/associate3.f90: New test. + +2016-06-21 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2016-06-17 Jakub Jelinek <jakub@redhat.com> + + * testsuite/libgomp.c++/target-21.C: New test. + + 2016-06-16 Jakub Jelinek <jakub@redhat.com> + + * testsuite/libgomp.c++/target-20.C: New test. + +2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/71373 + Backport from trunk r237291: + 2016-06-10 Thomas Schwinge <thomas@codesourcery.com> + Cesar Philippidis <cesar@codesourcery.com> + + * libgomp.oacc-c/nested-function-1.c: New file. + * libgomp.oacc-c/nested-function-2.c: Likewise. + * libgomp.oacc-fortran/nested-function-1.f90: Likewise. + * libgomp.oacc-fortran/nested-function-2.f90: Likewise. + * libgomp.oacc-fortran/nested-function-3.f90: Likewise. + + PR c/71381 + Backport from trunk r237290: + * testsuite/libgomp.oacc-c-c++-common/cache-1.c: #include + "../../../gcc/testsuite/c-c++-common/goacc/cache-1.c". + * testsuite/libgomp.oacc-fortran/cache-1.f95: New file. + 2016-05-23 Martin Jambor <mjambor@suse.cz> * testsuite/libgomp.hsa.c/switch-sbr-2.c: New test. diff --git a/libgomp/testsuite/libgomp.c++/target-20.C b/libgomp/testsuite/libgomp.c++/target-20.C new file mode 100644 index 00000000000..a722ec00c59 --- /dev/null +++ b/libgomp/testsuite/libgomp.c++/target-20.C @@ -0,0 +1,80 @@ +extern "C" void abort (); +struct S { int a, b, c, d; }; + +void +foo (S &s) +{ + int err; + #pragma omp target map (s.b, s.d) map (from: err) + { + err = s.b != 21 || s.d != 24; + s.b++; s.d++; + } + if (err || s.b != 22 || s.d != 25) + abort (); + #pragma omp target data map (s.b, s.d) + { + #pragma omp target map (alloc: s.b, s.d) map (from: err) + { + err = s.b != 22 || s.d != 25; + s.b++; s.d++; + } + } + if (err || s.b != 23 || s.d != 26) + abort (); + #pragma omp target data map (s) + { + #pragma omp target map (alloc: s.b, s.d) map (from: err) + { + err = s.b != 23 || s.d != 26; + s.b++; s.d++; + } + } + if (err || s.b != 24 || s.d != 27) + abort (); +} + +template <typename T, typename U> +void +bar (S &s, T &t, U u) +{ + int err; + #pragma omp target map (s.b, s.d, t.b, t.d, u.b, u.d) map (from: err) + { + err = s.b != 21 || s.d != 24 || t.b != 73 || t.d != 82 || u.b != 31 || u.d != 37; + s.b++; s.d++; t.b++; t.d++; u.b++; u.d++; + } + if (err || s.b != 22 || s.d != 25 || t.b != 74 || t.d != 83 || u.b != 32 || u.d != 38) + abort (); + #pragma omp target data map (s.b, s.d, t.b, t.d, u.b, u.d) + { + #pragma omp target map (alloc: s.b, s.d, t.b, t.d, u.b, u.d) map (from: err) + { + err = s.b != 22 || s.d != 25 || t.b != 74 || t.d != 83 || u.b != 32 || u.d != 38; + s.b++; s.d++; t.b++; t.d++; u.b++; u.d++; + } + } + if (err || s.b != 23 || s.d != 26 || t.b != 75 || t.d != 84 || u.b != 33 || u.d != 39) + abort (); + #pragma omp target data map (s, t, u) + { + #pragma omp target map (alloc: s.b, s.d, t.b, t.d, u.b, u.d) map (from: err) + { + err = s.b != 23 || s.d != 26 || t.b != 75 || t.d != 84 || u.b != 33 || u.d != 39; + s.b++; s.d++; t.b++; t.d++; u.b++; u.d++; + } + } + if (err || s.b != 24 || s.d != 27 || t.b != 76 || t.d != 85 || u.b != 34 || u.d != 40) + abort (); +} + +int +main () +{ + S s = { 1, 21, 2, 24 }; + foo (s); + S s2 = { 3, 21, 4, 24 }; + S t = { 5, 73, 6, 82 }; + S u = { 7, 31, 8, 37 }; + bar <S, S &> (s2, t, u); +} diff --git a/libgomp/testsuite/libgomp.c++/target-21.C b/libgomp/testsuite/libgomp.c++/target-21.C new file mode 100644 index 00000000000..21a2f299bbb --- /dev/null +++ b/libgomp/testsuite/libgomp.c++/target-21.C @@ -0,0 +1,173 @@ +extern "C" void abort (); +struct T { char t[270]; }; +struct S { int (&x)[10]; int *&y; T t; int &z; S (); ~S (); }; + +template <int N> +void +foo (S s) +{ + int err; + #pragma omp target map (s.x[0:N], s.y[0:N]) map (s.t.t[16:3]) map (from: err) + { + err = s.x[2] != 28 || s.y[2] != 37 || s.t.t[17] != 81; + s.x[2]++; + s.y[2]++; + s.t.t[17]++; + } + if (err || s.x[2] != 29 || s.y[2] != 38 || s.t.t[17] != 82) + abort (); +} + +template <int N> +void +bar (S s) +{ + int err; + #pragma omp target map (s.x, s.z)map(from:err) + { + err = s.x[2] != 29 || s.z != 6; + s.x[2]++; + s.z++; + } + if (err || s.x[2] != 30 || s.z != 7) + abort (); +} + +template <int N> +void +foo2 (S &s) +{ + int err; + #pragma omp target map (s.x[N:10], s.y[N:10]) map (from: err) map (s.t.t[N+16:N+3]) + { + err = s.x[2] != 30 || s.y[2] != 38 || s.t.t[17] != 81; + s.x[2]++; + s.y[2]++; + s.t.t[17]++; + } + if (err || s.x[2] != 31 || s.y[2] != 39 || s.t.t[17] != 82) + abort (); +} + +template <int N> +void +bar2 (S &s) +{ + int err; + #pragma omp target map (s.x, s.z)map(from:err) + { + err = s.x[2] != 31 || s.z != 7; + s.x[2]++; + s.z++; + } + if (err || s.x[2] != 32 || s.z != 8) + abort (); +} + +template <typename U> +void +foo3 (U s) +{ + int err; + #pragma omp target map (s.x[0:10], s.y[0:10]) map (from: err) map (s.t.t[16:3]) + { + err = s.x[2] != 32 || s.y[2] != 39 || s.t.t[17] != 82; + s.x[2]++; + s.y[2]++; + s.t.t[17]++; + } + if (err || s.x[2] != 33 || s.y[2] != 40 || s.t.t[17] != 83) + abort (); +} + +template <typename U> +void +bar3 (U s) +{ + int err; + #pragma omp target map (s.x, s.z)map(from:err) + { + err = s.x[2] != 33 || s.z != 8; + s.x[2]++; + s.z++; + } + if (err || s.x[2] != 34 || s.z != 9) + abort (); +} + +template <typename U> +void +foo4 (U &s) +{ + int err; + #pragma omp target map (s.x[0:10], s.y[0:10]) map (from: err) map (s.t.t[16:3]) + { + err = s.x[2] != 34 || s.y[2] != 40 || s.t.t[17] != 82; + s.x[2]++; + s.y[2]++; + s.t.t[17]++; + } + if (err || s.x[2] != 35 || s.y[2] != 41 || s.t.t[17] != 83) + abort (); +} + +template <typename U> +void +bar4 (U &s) +{ + int err; + #pragma omp target map (s.x, s.z)map(from:err) + { + err = s.x[2] != 35 || s.z != 9; + s.x[2]++; + s.z++; + } + if (err || s.x[2] != 36 || s.z != 10) + abort (); +} + +int xt[10] = { 1, 2, 28, 3, 4, 5, 6, 7, 8, 9 }; +int yt[10] = { 1, 2, 37, 3, 4, 5, 6, 7, 8, 9 }; +int *yp = yt; +int zt = 6; + +S::S () : x (xt), y (yp), z (zt) +{ +} + +S::~S () +{ +} + +int +main () +{ + S s; + s.t.t[16] = 5; + s.t.t[17] = 81; + s.t.t[18] = 9; + foo <10> (s); + if (s.t.t[17] != 81) + abort (); + bar <7> (s); + foo2 <0> (s); + if (s.t.t[17] != 82) + abort (); + bar2 <21> (s); + foo3 <S> (s); + if (s.t.t[17] != 82) + abort (); + bar3 <S> (s); + foo4 <S> (s); + if (s.t.t[17] != 83) + abort (); + bar4 <S> (s); + s.x[2] -= 4; + s.y[2] -= 2; + s.z -= 2; + s.t.t[17]--; + foo3 <S &> (s); + if (s.t.t[17] != 83) + abort (); + bar3 <S &> (s); +} diff --git a/libgomp/testsuite/libgomp.fortran/associate3.f90 b/libgomp/testsuite/libgomp.fortran/associate3.f90 new file mode 100644 index 00000000000..ec3d8dc33b9 --- /dev/null +++ b/libgomp/testsuite/libgomp.fortran/associate3.f90 @@ -0,0 +1,20 @@ +! PR fortran/71717 +! { dg-do run } + + type t + real, allocatable :: f(:) + end type + type (t) :: v + integer :: i, j + allocate (v%f(4)) + v%f = 19. + i = 5 + associate (u => v, k => i) + !$omp parallel do + do j = 1, 4 + u%f(j) = 21. + if (j.eq.1) k = 7 + end do + end associate + if (any (v%f(:).ne.21.) .or. i.ne.7) call abort +end diff --git a/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c b/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c index 3f1f0bb3764..16aaed5df70 100644 --- a/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c +++ b/libgomp/testsuite/libgomp.oacc-c-c++-common/cache-1.c @@ -1,48 +1,3 @@ -int -main (int argc, char **argv) -{ -#define N 2 - int a[N], b[N]; - int i; +/* OpenACC cache directive. */ - for (i = 0; i < N; i++) - { - a[i] = 3; - b[i] = 0; - } - -#pragma acc parallel copyin (a[0:N]) copyout (b[0:N]) -{ - int ii; - - for (ii = 0; ii < N; ii++) - { - const int idx = ii; - int n = 1; - const int len = n; - -#pragma acc cache (a[0:N]) - -#pragma acc cache (a[0:N], b[0:N]) - -#pragma acc cache (a[0]) - -#pragma acc cache (a[0], a[1], b[0:N]) - -#pragma acc cache (a[idx]) - -#pragma acc cache (a[idx:len]) - - b[ii] = a[ii]; - } -} - - - for (i = 0; i < N; i++) - { - if (a[i] != b[i]) - __builtin_abort (); - } - - return 0; -} +#include "../../../gcc/testsuite/c-c++-common/goacc/cache-1.c" diff --git a/libgomp/testsuite/libgomp.oacc-c/nested-function-1.c b/libgomp/testsuite/libgomp.oacc-c/nested-function-1.c new file mode 100644 index 00000000000..fb2a3acdfa9 --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-c/nested-function-1.c @@ -0,0 +1,52 @@ +/* Exercise nested function decomposition, gcc/tree-nested.c. */ + +int +main (void) +{ + void test1 () + { + int i, j, k; + int a[4][7][8]; + + __builtin_memset (a, 0, sizeof (a)); + +#pragma acc parallel +#pragma acc loop collapse(4 - 1) + for (i = 1; i <= 3; i++) + for (j = 4; j <= 6; j++) + for (k = 5; k <= 7; k++) + a[i][j][k] = i + j + k; + + for (i = 1; i <= 3; i++) + for (j = 4; j <= 6; j++) + for (k = 5; k <= 7; k++) + if (a[i][j][k] != i + j + k) + __builtin_abort(); + } + + void test2 () + { + int i, j, k; + int a[4][4][4]; + + __builtin_memset (a, 0, sizeof (a)); + +#pragma acc parallel +#pragma acc loop collapse(3) + for (i = 1; i <= 3; i++) + for (j = 1; j <= 3; j++) + for (k = 1; k <= 3; k++) + a[i][j][k] = 1; + + for (i = 1; i <= 3; i++) + for (j = 1; j <= 3; j++) + for (k = 1; k <= 3; k++) + if (a[i][j][k] != 1) + __builtin_abort (); + } + + test1 (); + test2 (); + + return 0; +} diff --git a/libgomp/testsuite/libgomp.oacc-c/nested-function-2.c b/libgomp/testsuite/libgomp.oacc-c/nested-function-2.c new file mode 100644 index 00000000000..2c3f3feb7f8 --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-c/nested-function-2.c @@ -0,0 +1,155 @@ +/* Exercise nested function decomposition, gcc/tree-nested.c. */ + +int +main (void) +{ + int p1 = 2, p2 = 6, p3 = 0, p4 = 4, p5 = 13, p6 = 18, p7 = 1, p8 = 1, p9 = 1; + + void test1 () + { + int i, j, k; + int a[4][4][4]; + + __builtin_memset (a, '\0', sizeof (a)); + +#pragma acc parallel +#pragma acc loop collapse(3) + for (i = 1; i <= 3; i++) + for (j = 1; j <= 3; j++) + for (k = 2; k <= 3; k++) + a[i][j][k] = 1; + + for (i = 1; i <= 3; i++) + for (j = 1; j <= 3; j++) + for (k = 2; k <= 3; k++) + if (a[i][j][k] != 1) + __builtin_abort(); + } + + void test2 (int v1, int v2, int v3, int v4, int v5, int v6) + { + int i, j, k, l = 0, r = 0; + int a[7][5][19]; + int b[7][5][19]; + + __builtin_memset (a, '\0', sizeof (a)); + __builtin_memset (b, '\0', sizeof (b)); + +#pragma acc parallel reduction (||:l) +#pragma acc loop reduction (||:l) collapse(3) + for (i = v1; i <= v2; i++) + for (j = v3; j <= v4; j++) + for (k = v5; k <= v6; k++) + { + l = l || i < 2 || i > 6 || j < 0 || j > 4 || k < 13 || k > 18; + if (!l) + a[i][j][k] += 1; + } + + for (i = v1; i <= v2; i++) + for (j = v3; j <= v4; j++) + for (k = v5; k <= v6; k++) + { + r = r || i < 2 || i > 6 || j < 0 || j > 4 || k < 13 || k > 18; + if (!r) + b[i][j][k] += 1; + } + + if (l != r) + __builtin_abort (); + + for (i = v1; i <= v2; i++) + for (j = v3; j <= v4; j++) + for (k = v5; k <= v6; k++) + if (b[i][j][k] != a[i][j][k]) + __builtin_abort (); + } + + void test3 (int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, + int v9) + { + int i, j, k, l = 0, r = 0; + int a[7][5][19]; + int b[7][5][19]; + + __builtin_memset (a, '\0', sizeof (a)); + __builtin_memset (b, '\0', sizeof (b)); + +#pragma acc parallel reduction (||:l) +#pragma acc loop reduction (||:l) collapse(3) + for (i = v1; i <= v2; i += v7) + for (j = v3; j <= v4; j += v8) + for (k = v5; k <= v6; k += v9) + { + l = l || i < 2 || i > 6 || j < 0 || j > 4 || k < 13 || k > 18; + if (!l) + a[i][j][k] += 1; + } + + for (i = v1; i <= v2; i += v7) + for (j = v3; j <= v4; j += v8) + for (k = v5; k <= v6; k += v9) + { + r = r || i < 2 || i > 6 || j < 0 || j > 4 || k < 13 || k > 18; + if (!r) + b[i][j][k] += 1; + } + + if (l != r) + __builtin_abort (); + + for (i = v1; i <= v2; i++) + for (j = v3; j <= v4; j++) + for (k = v5; k <= v6; k++) + if (b[i][j][k] != a[i][j][k]) + __builtin_abort (); + } + + void test4 () + { + int i, j, k, l = 0, r = 0; + int a[7][5][19]; + int b[7][5][19]; + int v1 = p1, v2 = p2, v3 = p3, v4 = p4, v5 = p5, v6 = p6, v7 = p7, v8 = p8, + v9 = p9; + + __builtin_memset (a, '\0', sizeof (a)); + __builtin_memset (b, '\0', sizeof (b)); + +#pragma acc parallel reduction (||:l) +#pragma acc loop reduction (||:l) collapse(3) + for (i = v1; i <= v2; i += v7) + for (j = v3; j <= v4; j += v8) + for (k = v5; k <= v6; k += v9) + { + l = l || i < 2 || i > 6 || j < 0 || j > 4 || k < 13 || k > 18; + if (!l) + a[i][j][k] += 1; + } + + for (i = v1; i <= v2; i += v7) + for (j = v3; j <= v4; j += v8) + for (k = v5; k <= v6; k += v9) + { + r = r || i < 2 || i > 6 || j < 0 || j > 4 || k < 13 || k > 18; + if (!r) + b[i][j][k] += 1; + } + + if (l != r) + __builtin_abort (); + + for (i = v1; i <= v2; i++) + for (j = v3; j <= v4; j++) + for (k = v5; k <= v6; k++) + if (b[i][j][k] != a[i][j][k]) + __builtin_abort (); + } + + test1 (); + test2 (p1, p2, p3, p4, p5, p6); + test3 (p1, p2, p3, p4, p5, p6, p7, p8, p9); + test4 (); + + return 0; +} diff --git a/libgomp/testsuite/libgomp.oacc-fortran/cache-1.f95 b/libgomp/testsuite/libgomp.oacc-fortran/cache-1.f95 new file mode 100644 index 00000000000..37313d8c44a --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-fortran/cache-1.f95 @@ -0,0 +1,6 @@ +! OpenACC cache directive. +! { dg-do run } +! { dg-additional-options "-std=f2008" } +! { dg-additional-options "-cpp" } + +#include "../../../gcc/testsuite/gfortran.dg/goacc/cache-1.f95" diff --git a/libgomp/testsuite/libgomp.oacc-fortran/nested-function-1.f90 b/libgomp/testsuite/libgomp.oacc-fortran/nested-function-1.f90 new file mode 100644 index 00000000000..fdbca4481f8 --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-fortran/nested-function-1.f90 @@ -0,0 +1,70 @@ +! Exercise nested function decomposition, gcc/tree-nested.c. + +! { dg-do run } + +program collapse2 + call test1 + call test2 +contains + subroutine test1 + integer :: i, j, k, a(1:3, 4:6, 5:7) + logical :: l + l = .false. + a(:, :, :) = 0 + !$acc parallel reduction (.or.:l) + !$acc loop worker vector collapse(4 - 1) + do 164 i = 1, 3 + do 164 j = 4, 6 + do 164 k = 5, 7 + a(i, j, k) = i + j + k +164 end do + !$acc loop worker vector reduction(.or.:l) collapse(2) +firstdo: do i = 1, 3 + do j = 4, 6 + do k = 5, 7 + if (a(i, j, k) .ne. (i + j + k)) l = .true. + end do + end do + end do firstdo + !$acc end parallel + if (l) call abort + end subroutine test1 + + subroutine test2 + integer :: a(3,3,3), k, kk, kkk, l, ll, lll + a = 0 + !$acc parallel + ! Use "gang(static:1)" here and below to effectively turn gang-redundant + ! execution mode into something like gang-single. + !$acc loop gang(static:1) collapse(1) + do 115 k=1,3 + !$acc loop collapse(2) + dokk: do kk=1,3 + do kkk=1,3 + a(k,kk,kkk) = 1 + enddo + enddo dokk +115 continue + !$acc loop gang(static:1) collapse(1) + do k=1,3 + if (any(a(k,1:3,1:3).ne.1)) call abort + enddo + ! Use "gang(static:1)" here and below to effectively turn gang-redundant + ! execution mode into something like gang-single. + !$acc loop gang(static:1) collapse(1) + dol: do 120 l=1,3 + !$acc loop collapse(2) + doll: do ll=1,3 + do lll=1,3 + a(l,ll,lll) = 2 + enddo + enddo doll +120 end do dol + !$acc loop gang(static:1) collapse(1) + do l=1,3 + if (any(a(l,1:3,1:3).ne.2)) call abort + enddo + !$acc end parallel + end subroutine test2 + +end program collapse2 diff --git a/libgomp/testsuite/libgomp.oacc-fortran/nested-function-2.f90 b/libgomp/testsuite/libgomp.oacc-fortran/nested-function-2.f90 new file mode 100644 index 00000000000..4e2819641ea --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-fortran/nested-function-2.f90 @@ -0,0 +1,173 @@ +! Exercise nested function decomposition, gcc/tree-nested.c. + +! { dg-do run } + +program collapse3 + integer :: p1, p2, p3, p4, p5, p6, p7, p8, p9 + p1 = 2 + p2 = 6 + p3 = -2 + p4 = 4 + p5 = 13 + p6 = 18 + p7 = 1 + p8 = 1 + p9 = 1 + call test1 + call test2 (p1, p2, p3, p4, p5, p6) + call test3 (p1, p2, p3, p4, p5, p6, p7, p8, p9) + call test4 +contains + subroutine test1 + integer :: a(3,3,3), k, kk, kkk, l, ll, lll + !$acc parallel + !$acc loop collapse(3) + do 115 k=1,3 +dokk: do kk=1,3 + do kkk=1,3 + a(k,kk,kkk) = 1 + enddo + enddo dokk +115 continue + !$acc end parallel + if (any(a(1:3,1:3,1:3).ne.1)) call abort + !$acc parallel + !$acc loop collapse(3) +dol: do 120 l=1,3 +doll: do ll=1,3 + do lll=1,3 + a(l,ll,lll) = 2 + enddo + enddo doll +120 end do dol + !$acc end parallel + if (any(a(1:3,1:3,1:3).ne.2)) call abort + end subroutine test1 + + subroutine test2(v1, v2, v3, v4, v5, v6) + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + !$acc parallel reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + end do + end do + end do + !$acc end parallel + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.l) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test2 + + subroutine test3(v1, v2, v3, v4, v5, v6, v7, v8, v9) + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6, v7, v8, v9 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + !$acc parallel reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + end do + end do + end do + !$acc end parallel + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.l) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test3 + + subroutine test4 + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6, v7, v8, v9 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + v1 = p1 + v2 = p2 + v3 = p3 + v4 = p4 + v5 = p5 + v6 = p6 + v7 = p7 + v8 = p8 + v9 = p9 + !$acc parallel reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + end do + end do + end do + !$acc end parallel + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.r) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test4 + +end program collapse3 diff --git a/libgomp/testsuite/libgomp.oacc-fortran/nested-function-3.f90 b/libgomp/testsuite/libgomp.oacc-fortran/nested-function-3.f90 new file mode 100644 index 00000000000..2f6485ef8cf --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-fortran/nested-function-3.f90 @@ -0,0 +1,244 @@ +! Exercise nested function decomposition, gcc/tree-nested.c. + +! { dg-do run } + +program sub_collapse_3 + call test1 + call test2 (2, 6, -2, 4, 13, 18) + call test3 (2, 6, -2, 4, 13, 18, 1, 1, 1) + call test4 + call test5 (2, 6, -2, 4, 13, 18) + call test6 (2, 6, -2, 4, 13, 18, 1, 1, 1) +contains + subroutine test1 + integer :: a(3,3,3), k, kk, kkk, l, ll, lll + !$acc parallel + !$acc loop collapse(3) + do 115 k=1,3 +dokk: do kk=1,3 + do kkk=1,3 + a(k,kk,kkk) = 1 + enddo + enddo dokk +115 continue + !$acc end parallel + if (any(a(1:3,1:3,1:3).ne.1)) call abort + !$acc parallel + !$acc loop collapse(3) +dol: do 120 l=1,3 +doll: do ll=1,3 + do lll=1,3 + a(l,ll,lll) = 2 + enddo + enddo doll +120 end do dol + !$acc end parallel + if (any(a(1:3,1:3,1:3).ne.2)) call abort + end subroutine test1 + + subroutine test2(v1, v2, v3, v4, v5, v6) + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + !$acc parallel pcopyin (v1, v2, v3, v4, v5, v6) reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + end do + end do + end do + !$acc end parallel + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.l) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test2 + + subroutine test3(v1, v2, v3, v4, v5, v6, v7, v8, v9) + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6, v7, v8, v9 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + !$acc parallel pcopyin (v1, v2, v3, v4, v5, v6, v7, v8, v9) reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + end do + end do + end do + !$acc end parallel + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.l) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test3 + + subroutine test4 + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6, v7, v8, v9 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + v1 = 2 + v2 = 6 + v3 = -2 + v4 = 4 + v5 = 13 + v6 = 18 + v7 = 1 + v8 = 1 + v9 = 1 + !$acc parallel pcopyin (v1, v2, v3, v4, v5, v6, v7, v8, v9) reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + end do + end do + end do + !$acc end parallel + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.r) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test4 + + subroutine test5(v1, v2, v3, v4, v5, v6) + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + !$acc parallel pcopyin (v1, v2, v3, v4, v5, v6) reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + end do + end do + end do + !$acc end parallel + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.r) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2 + do j = v3, v4 + do k = v5, v6 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test5 + + subroutine test6(v1, v2, v3, v4, v5, v6, v7, v8, v9) + integer :: i, j, k, a(1:7, -3:5, 12:19), b(1:7, -3:5, 12:19) + integer :: v1, v2, v3, v4, v5, v6, v7, v8, v9 + logical :: l, r + l = .false. + r = .false. + a(:, :, :) = 0 + b(:, :, :) = 0 + !$acc parallel pcopyin (v1, v2, v3, v4, v5, v6, v7, v8, v9) reduction (.or.:l) + !$acc loop reduction (.or.:l) collapse (3) + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + l = l.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + l = l.or.k.lt.13.or.k.gt.18 + if (.not.l) a(i, j, k) = a(i, j, k) + 1 + m = i * 100 + j * 10 + k + end do + end do + end do + !$acc end parallel + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + r = r.or.i.lt.2.or.i.gt.6.or.j.lt.-2.or.j.gt.4 + r = r.or.k.lt.13.or.k.gt.18 + if (.not.r) b(i, j, k) = b(i, j, k) + 1 + end do + end do + end do + if (l .neqv. r) call abort + do i = v1, v2, v7 + do j = v3, v4, v8 + do k = v5, v6, v9 + if (a(i, j, k) .ne. b(i, j, k)) call abort + end do + end do + end do + end subroutine test6 + +end program sub_collapse_3 diff --git a/libmpx/ChangeLog b/libmpx/ChangeLog index 47146d1cf7c..98bb5577de3 100644 --- a/libmpx/ChangeLog +++ b/libmpx/ChangeLog @@ -1,3 +1,10 @@ +2016-06-10 Ilya Enkovich <ilya.enkovich@intel.com> + + Backport from mainline r237292. + 2016-06-10 Ilya Enkovich <ilya.enkovich@intel.com> + + * mpxwrap/mpx_wrappers.c (move_bounds): Fix overflow bug. + 2016-04-27 Release Manager * GCC 6.1.0 released. diff --git a/libmpx/mpxwrap/mpx_wrappers.c b/libmpx/mpxwrap/mpx_wrappers.c index d4c83ef484c..171a780311d 100644 --- a/libmpx/mpxwrap/mpx_wrappers.c +++ b/libmpx/mpxwrap/mpx_wrappers.c @@ -27,6 +27,7 @@ #include "string.h" #include <sys/mman.h> #include <stdint.h> +#include <assert.h> #include "mpxrt/mpxrt.h" void * @@ -418,7 +419,16 @@ move_bounds (void *dst, const void *src, size_t n) else elems_to_copy -= src_bt_index_end + 1; } - src_bd_index_end--; + /* Go to previous table but beware of overflow. + We should have copied all required element + in case src_bd_index_end is 0. */ + if (src_bd_index_end) + src_bd_index_end--; + else + { + assert (!elems_to_copy); + return; + } /* For each bounds table we check if there are valid pointers inside. If there are some, we copy table in pre-counted portions. */ for (; src_bd_index_end > src_bd_index; src_bd_index_end--) diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 3c3fda9b582..4308c997c58 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,51 @@ +2016-07-06 Ville Voutilainen <ville.voutilainen@gmail.com> + + Implement LWG 2451, optional<T> should 'forward' T's + implicit conversions. + * include/experimental/optional (__is_optional_impl, __is_optional): + New. + (optional()): Make constexpr and default. + (optional(_Up&&), optional(const optional<_Up>&), + optional(optional<_Up>&& __t): New. + (operator=(_Up&&)): Constrain. + (operator=(const optional<_Up>&), operator=(optional<_Up>&&)): New. + * testsuite/experimental/optional/cons/value.cc: + Add tests for the functionality added by LWG 2451. + * testsuite/experimental/optional/cons/value_neg.cc: New. + +2016-07-05 Ville Voutilainen <ville.voutilainen@gmail.com> + + Implement LWG 2509, + any_cast doesn't work with rvalue reference targets and cannot + move with a value target. + * include/experimental/any (any(_ValueType&&)): Constrain and + add an overload that doesn't forward. + (any_cast(any&&)): Constrain and add an overload that moves. + * testsuite/experimental/any/misc/any_cast.cc: Add tests for + the functionality added by LWG 2509. + +2016-07-04 Ville Voutilainen <ville.voutilainen@gmail.com> + + PR libstdc++/71313 + * src/filesystem/ops.cc (remove_all(const path&, error_code&)): + Call remove_all for children of a directory. + * testsuite/experimental/filesystem/operations/create_directories.cc: + Adjust. + +2016-06-17 Jonathan Wakely <jwakely@redhat.com> + + PR libstdc++/71545 + * include/bits/stl_algobase.h (lower_bound, lexicographical_compare): + Remove irreflexive checks. + * include/bits/stl_algo.h (lower_bound, upper_bound, equal_range, + binary_search): Likewise. + * testsuite/25_algorithms/equal_range/partitioned.cc: New test. + * testsuite/25_algorithms/lexicographical_compare/71545.cc: New test. + * testsuite/25_algorithms/lower_bound/partitioned.cc: New test. + * testsuite/25_algorithms/upper_bound/partitioned.cc: New test. + * testsuite/util/testsuite_iterators.h (__gnu_test::test_container): + Add constructor from array. + 2016-05-26 Jonathan Wakely <jwakely@redhat.com> Backport from mainline diff --git a/libstdc++-v3/include/bits/stl_algo.h b/libstdc++-v3/include/bits/stl_algo.h index fbd03a79e1e..c2ac0317f17 100644 --- a/libstdc++-v3/include/bits/stl_algo.h +++ b/libstdc++-v3/include/bits/stl_algo.h @@ -2026,7 +2026,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION typename iterator_traits<_ForwardIterator>::value_type, _Tp>) __glibcxx_requires_partitioned_lower_pred(__first, __last, __val, __comp); - __glibcxx_requires_irreflexive_pred2(__first, __last, __comp); return std::__lower_bound(__first, __last, __val, __gnu_cxx::__ops::__iter_comp_val(__comp)); @@ -2080,7 +2079,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __glibcxx_function_requires(_LessThanOpConcept< _Tp, typename iterator_traits<_ForwardIterator>::value_type>) __glibcxx_requires_partitioned_upper(__first, __last, __val); - __glibcxx_requires_irreflexive2(__first, __last); return std::__upper_bound(__first, __last, __val, __gnu_cxx::__ops::__val_less_iter()); @@ -2112,7 +2110,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION _Tp, typename iterator_traits<_ForwardIterator>::value_type>) __glibcxx_requires_partitioned_upper_pred(__first, __last, __val, __comp); - __glibcxx_requires_irreflexive_pred2(__first, __last, __comp); return std::__upper_bound(__first, __last, __val, __gnu_cxx::__ops::__val_comp_iter(__comp)); @@ -2186,7 +2183,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION _Tp, typename iterator_traits<_ForwardIterator>::value_type>) __glibcxx_requires_partitioned_lower(__first, __last, __val); __glibcxx_requires_partitioned_upper(__first, __last, __val); - __glibcxx_requires_irreflexive2(__first, __last); return std::__equal_range(__first, __last, __val, __gnu_cxx::__ops::__iter_less_val(), @@ -2225,7 +2221,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __val, __comp); __glibcxx_requires_partitioned_upper_pred(__first, __last, __val, __comp); - __glibcxx_requires_irreflexive_pred2(__first, __last, __comp); return std::__equal_range(__first, __last, __val, __gnu_cxx::__ops::__iter_comp_val(__comp), @@ -2255,7 +2250,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION _Tp, typename iterator_traits<_ForwardIterator>::value_type>) __glibcxx_requires_partitioned_lower(__first, __last, __val); __glibcxx_requires_partitioned_upper(__first, __last, __val); - __glibcxx_requires_irreflexive2(__first, __last); _ForwardIterator __i = std::__lower_bound(__first, __last, __val, @@ -2291,7 +2285,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __val, __comp); __glibcxx_requires_partitioned_upper_pred(__first, __last, __val, __comp); - __glibcxx_requires_irreflexive_pred2(__first, __last, __comp); _ForwardIterator __i = std::__lower_bound(__first, __last, __val, diff --git a/libstdc++-v3/include/bits/stl_algobase.h b/libstdc++-v3/include/bits/stl_algobase.h index d95ea513a59..210b1734545 100644 --- a/libstdc++-v3/include/bits/stl_algobase.h +++ b/libstdc++-v3/include/bits/stl_algobase.h @@ -989,7 +989,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __glibcxx_function_requires(_LessThanOpConcept< typename iterator_traits<_ForwardIterator>::value_type, _Tp>) __glibcxx_requires_partitioned_lower(__first, __last, __val); - __glibcxx_requires_irreflexive2(__first, __last); return std::__lower_bound(__first, __last, __val, __gnu_cxx::__ops::__iter_less_val()); @@ -1214,9 +1213,7 @@ _GLIBCXX_BEGIN_NAMESPACE_ALGO __glibcxx_function_requires(_LessThanOpConcept<_ValueType1, _ValueType2>) __glibcxx_function_requires(_LessThanOpConcept<_ValueType2, _ValueType1>) __glibcxx_requires_valid_range(__first1, __last1); - __glibcxx_requires_irreflexive2(__first1, __last1); __glibcxx_requires_valid_range(__first2, __last2); - __glibcxx_requires_irreflexive2(__first2, __last2); return std::__lexicographical_compare_aux(std::__niter_base(__first1), std::__niter_base(__last1), @@ -1246,9 +1243,7 @@ _GLIBCXX_BEGIN_NAMESPACE_ALGO __glibcxx_function_requires(_InputIteratorConcept<_II1>) __glibcxx_function_requires(_InputIteratorConcept<_II2>) __glibcxx_requires_valid_range(__first1, __last1); - __glibcxx_requires_irreflexive_pred2(__first1, __last1, __comp); __glibcxx_requires_valid_range(__first2, __last2); - __glibcxx_requires_irreflexive_pred2(__first2, __last2, __comp); return std::__lexicographical_compare_impl (__first1, __last1, __first2, __last2, diff --git a/libstdc++-v3/include/experimental/any b/libstdc++-v3/include/experimental/any index ae40091fbb4..96ad5762f66 100644 --- a/libstdc++-v3/include/experimental/any +++ b/libstdc++-v3/include/experimental/any @@ -158,7 +158,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION /// Construct with a copy of @p __value as the contained object. template <typename _ValueType, typename _Tp = _Decay<_ValueType>, - typename _Mgr = _Manager<_Tp>> + typename _Mgr = _Manager<_Tp>, + typename enable_if<is_constructible<_Tp, _ValueType&&>::value, + bool>::type = true> any(_ValueType&& __value) : _M_manager(&_Mgr::_S_manage) { @@ -167,6 +169,19 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION "The contained object must be CopyConstructible"); } + /// Construct with a copy of @p __value as the contained object. + template <typename _ValueType, typename _Tp = _Decay<_ValueType>, + typename _Mgr = _Manager<_Tp>, + typename enable_if<!is_constructible<_Tp, _ValueType&&>::value, + bool>::type = false> + any(_ValueType&& __value) + : _M_manager(&_Mgr::_S_manage) + { + _Mgr::_S_create(_M_storage, __value); + static_assert(is_copy_constructible<_Tp>::value, + "The contained object must be CopyConstructible"); + } + /// Destructor, calls @c clear() ~any() { clear(); } @@ -377,7 +392,10 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __throw_bad_any_cast(); } - template<typename _ValueType> + template<typename _ValueType, + typename enable_if<!is_move_constructible<_ValueType>::value + || is_lvalue_reference<_ValueType>::value, + bool>::type = true> inline _ValueType any_cast(any&& __any) { static_assert(any::__is_valid_cast<_ValueType>(), @@ -387,6 +405,20 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION return *__p; __throw_bad_any_cast(); } + + template<typename _ValueType, + typename enable_if<is_move_constructible<_ValueType>::value + && !is_lvalue_reference<_ValueType>::value, + bool>::type = false> + inline _ValueType any_cast(any&& __any) + { + static_assert(any::__is_valid_cast<_ValueType>(), + "Template argument must be a reference or CopyConstructible type"); + auto __p = any_cast<remove_reference_t<_ValueType>>(&__any); + if (__p) + return std::move(*__p); + __throw_bad_any_cast(); + } // @} template<typename _Tp> diff --git a/libstdc++-v3/include/experimental/optional b/libstdc++-v3/include/experimental/optional index 7524a7e1357..b6425b7d00e 100644 --- a/libstdc++-v3/include/experimental/optional +++ b/libstdc++-v3/include/experimental/optional @@ -470,6 +470,23 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION bool _M_engaged = false; }; + template<typename _Tp> + class optional; + + template<typename> + struct __is_optional_impl : false_type + { }; + + template<typename _Tp> + struct __is_optional_impl<optional<_Tp>> : true_type + { }; + + template<typename _Tp> + struct __is_optional + : public __is_optional_impl<std::remove_cv_t<std::remove_reference_t<_Tp>>> + { }; + + /** * @brief Class template for optional values. */ @@ -502,6 +519,78 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION // _Optional_base has the responsibility for construction. using _Base::_Base; + constexpr optional() = default; + // Converting constructors for engaged optionals. + template <typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>, + is_constructible<_Tp, _Up&&>, + is_convertible<_Up&&, _Tp> + >::value, bool> = true> + constexpr optional(_Up&& __t) + : _Base(_Tp(std::forward<_Up>(__t))) { } + + template <typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>, + is_constructible<_Tp, _Up&&>, + __not_<is_convertible<_Up&&, _Tp>> + >::value, bool> = false> + explicit constexpr optional(_Up&& __t) + : _Base(_Tp(std::forward<_Up>(__t))) { } + + template <typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>, + __not_<is_constructible< + _Tp, const optional<_Up>&>>, + __not_<is_convertible< + const optional<_Up>&, _Tp>>, + is_constructible<_Tp, const _Up&>, + is_convertible<const _Up&, _Tp> + >::value, bool> = true> + constexpr optional(const optional<_Up>& __t) + : _Base(__t ? optional<_Tp>(*__t) : optional<_Tp>()) { } + + template <typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>, + __not_<is_constructible< + _Tp, const optional<_Up>&>>, + __not_<is_convertible< + const optional<_Up>&, _Tp>>, + is_constructible<_Tp, const _Up&>, + __not_<is_convertible<const _Up&, _Tp>> + >::value, bool> = false> + explicit constexpr optional(const optional<_Up>& __t) + : _Base(__t ? optional<_Tp>(*__t) : optional<_Tp>()) { } + + template <typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>, + __not_<is_constructible< + _Tp, optional<_Up>&&>>, + __not_<is_convertible< + optional<_Up>&&, _Tp>>, + is_constructible<_Tp, _Up&&>, + is_convertible<_Up&&, _Tp> + >::value, bool> = true> + constexpr optional(optional<_Up>&& __t) + : _Base(__t ? optional<_Tp>(std::move(*__t)) : optional<_Tp>()) { } + + template <typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>, + __not_<is_constructible< + _Tp, optional<_Up>&&>>, + __not_<is_convertible< + optional<_Up>&&, _Tp>>, + is_constructible<_Tp, _Up&&>, + __not_<is_convertible<_Up&&, _Tp>> + >::value, bool> = false> + explicit constexpr optional(optional<_Up>&& __t) + : _Base(__t ? optional<_Tp>(std::move(*__t)) : optional<_Tp>()) { } + // [X.Y.4.3] (partly) Assignment. optional& operator=(nullopt_t) noexcept @@ -510,8 +599,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION return *this; } - template<typename _Up> - enable_if_t<is_same<_Tp, decay_t<_Up>>::value, optional&> + template<typename _Up, + enable_if_t<__and_< + __not_<is_same<_Up, nullopt_t>>, + __not_<__is_optional<_Up>>>::value, + bool> = true> + optional& operator=(_Up&& __u) { static_assert(__and_<is_constructible<_Tp, _Up>, @@ -526,6 +619,57 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION return *this; } + template<typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>>::value, + bool> = true> + optional& + operator=(const optional<_Up>& __u) + { + static_assert(__and_<is_constructible<_Tp, _Up>, + is_assignable<_Tp&, _Up>>(), + "Cannot assign to value type from argument"); + + if (__u) + { + if (this->_M_is_engaged()) + this->_M_get() = *__u; + else + this->_M_construct(*__u); + } + else + { + this->_M_reset(); + } + return *this; + } + + template<typename _Up, + enable_if_t<__and_< + __not_<is_same<_Tp, _Up>>>::value, + bool> = true> + optional& + operator=(optional<_Up>&& __u) + { + static_assert(__and_<is_constructible<_Tp, _Up>, + is_assignable<_Tp&, _Up>>(), + "Cannot assign to value type from argument"); + + if (__u) + { + if (this->_M_is_engaged()) + this->_M_get() = std::move(*__u); + else + this->_M_construct(std::move(*__u)); + } + else + { + this->_M_reset(); + } + + return *this; + } + template<typename... _Args> void emplace(_Args&&... __args) diff --git a/libstdc++-v3/src/filesystem/ops.cc b/libstdc++-v3/src/filesystem/ops.cc index 5b82088891e..668c7051c42 100644 --- a/libstdc++-v3/src/filesystem/ops.cc +++ b/libstdc++-v3/src/filesystem/ops.cc @@ -1172,7 +1172,7 @@ fs::remove_all(const path& p, error_code& ec) noexcept uintmax_t count = 0; if (ec.value() == 0 && fs.type() == file_type::directory) for (directory_iterator d(p, ec), end; ec.value() == 0 && d != end; ++d) - count += fs::remove(d->path(), ec); + count += fs::remove_all(d->path(), ec); if (ec.value()) return -1; return fs::remove(p, ec) ? ++count : -1; // fs:remove() calls ec.clear() diff --git a/libstdc++-v3/testsuite/25_algorithms/binary_search/partitioned.cc b/libstdc++-v3/testsuite/25_algorithms/binary_search/partitioned.cc new file mode 100644 index 00000000000..63a6cada97e --- /dev/null +++ b/libstdc++-v3/testsuite/25_algorithms/binary_search/partitioned.cc @@ -0,0 +1,67 @@ +// Copyright (C) 2016 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" } + +#include <algorithm> +#include <functional> +#include <testsuite_iterators.h> +#include <testsuite_hooks.h> + +using __gnu_test::test_container; +using __gnu_test::forward_iterator_wrapper; + +struct X +{ + int val; + + bool odd() const { return val % 2; } + + // Partitioned so that all odd values come before even values: + bool operator<(const X& x) const { return this->odd() && !x.odd(); } +}; + +void +test01() +{ + bool test __attribute((unused)) = true; + + // Test with range that is partitioned, but not sorted. + X seq[] = { 1, 3, 5, 7, 1, 6, 4 }; + test_container<X, forward_iterator_wrapper> c(seq); + + auto b1 = std::binary_search(c.begin(), c.end(), X{2}); + VERIFY( b1 ); + auto b2 = std::binary_search(c.begin(), c.end(), X{2}, std::less<X>{}); + VERIFY( b2 ); + + auto b3 = std::binary_search(c.begin(), c.end(), X{9}); + VERIFY( b3 ); + auto b4 = std::binary_search(c.begin(), c.end(), X{9}, std::less<X>{}); + VERIFY( b4 ); + + auto b5 = std::binary_search(seq, seq+5, X{2}); + VERIFY( !b5 ); + auto b6 = std::binary_search(seq, seq+5, X{2}, std::less<X>{}); + VERIFY( !b6 ); +} + +int +main() +{ + test01(); +} diff --git a/libstdc++-v3/testsuite/25_algorithms/equal_range/partitioned.cc b/libstdc++-v3/testsuite/25_algorithms/equal_range/partitioned.cc new file mode 100644 index 00000000000..d3a43d06a58 --- /dev/null +++ b/libstdc++-v3/testsuite/25_algorithms/equal_range/partitioned.cc @@ -0,0 +1,66 @@ +// Copyright (C) 2016 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" } + +#include <algorithm> +#include <functional> +#include <testsuite_iterators.h> +#include <testsuite_hooks.h> + +using __gnu_test::test_container; +using __gnu_test::forward_iterator_wrapper; + +struct X +{ + int val; + + bool odd() const { return val % 2; } + + // Partitioned so that all odd values come before even values: + bool operator<(const X& x) const { return this->odd() && !x.odd(); } +}; + +void +test01() +{ + bool test __attribute((unused)) = true; + + // Test with range that is partitioned, but not sorted. + X seq[] = { 1, 3, 5, 7, 1, 6, 4, 2 }; + test_container<X, forward_iterator_wrapper> c(seq); + + auto part1 = std::equal_range(c.begin(), c.end(), X{2}); + VERIFY( part1.first != c.end() && part1.second == c.end() ); + VERIFY( part1.first->val == 6 ); + auto part2 = std::equal_range(c.begin(), c.end(), X{2}, std::less<X>{}); + VERIFY( part2.first != c.end() && part1.second == c.end() ); + VERIFY( part2.first->val == 6 ); + + auto part3 = std::equal_range(c.begin(), c.end(), X{9}); + VERIFY( part3.first == c.begin() && part3.second != c.end() ); + VERIFY( part3.second->val == 6 ); + auto part4 = std::equal_range(c.begin(), c.end(), X{9}, std::less<X>{}); + VERIFY( part4.first == c.begin() && part4.second != c.end() ); + VERIFY( part4.second->val == 6 ); +} + +int +main() +{ + test01(); +} diff --git a/libstdc++-v3/testsuite/25_algorithms/lexicographical_compare/71545.cc b/libstdc++-v3/testsuite/25_algorithms/lexicographical_compare/71545.cc new file mode 100644 index 00000000000..6c9cd12cfef --- /dev/null +++ b/libstdc++-v3/testsuite/25_algorithms/lexicographical_compare/71545.cc @@ -0,0 +1,35 @@ +// Copyright (C) 2016 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" } +// { dg-do link } + +#include <algorithm> + +struct X { }; + +bool operator<(X, int) { return true; } +bool operator<(int, X) { return false; } + +bool operator<(X, X); // undefined (PR libstdc++/71545) + +int main() +{ + X x[1]; + int i[1]; + std::lexicographical_compare(x, x+1, i, i+1); +} diff --git a/libstdc++-v3/testsuite/25_algorithms/lower_bound/partitioned.cc b/libstdc++-v3/testsuite/25_algorithms/lower_bound/partitioned.cc new file mode 100644 index 00000000000..bba0b66ea80 --- /dev/null +++ b/libstdc++-v3/testsuite/25_algorithms/lower_bound/partitioned.cc @@ -0,0 +1,100 @@ +// Copyright (C) 2016 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" } + +#include <algorithm> +#include <functional> +#include <testsuite_iterators.h> +#include <testsuite_hooks.h> + +using __gnu_test::test_container; +using __gnu_test::forward_iterator_wrapper; + +struct X +{ + int val; + + bool odd() const { return val % 2; } + + // Partitioned so that all odd values come before even values: + bool operator<(const X& x) const { return this->odd() && !x.odd(); } +}; + +void +test01() +{ + bool test __attribute((unused)) = true; + + // Test with range that is partitioned, but not sorted. + X seq[] = { 1, 3, 5, 7, 1, 6, 4, 2 }; + test_container<X, forward_iterator_wrapper> c(seq); + + auto part1 = std::lower_bound(c.begin(), c.end(), X{2}); + VERIFY( part1 != c.end() ); + VERIFY( part1->val == 6 ); + auto part2 = std::lower_bound(c.begin(), c.end(), X{2}, std::less<X>{}); + VERIFY( part2 != c.end() ); + VERIFY( part2->val == 6 ); + + auto part3 = std::lower_bound(c.begin(), c.end(), X{9}); + VERIFY( part3 != c.end() ); + VERIFY( part3->val == 1 ); + auto part4 = std::lower_bound(c.begin(), c.end(), X{9}, std::less<X>{}); + VERIFY( part4 != c.end() ); + VERIFY( part4->val == 1 ); +} + +struct Y +{ + double val; + + // Not irreflexive, so not a strict weak order. + bool operator<(const Y& y) const { return val < int(y.val); } +}; + +void +test02() +{ + bool test __attribute((unused)) = true; + + // Test that Debug Mode checks don't fire (libstdc++/71545) + + Y seq[] = { -0.1, 1.2, 5.0, 5.2, 5.1, 5.9, 5.5, 6.0 }; + test_container<Y, forward_iterator_wrapper> c(seq); + + auto part1 = std::lower_bound(c.begin(), c.end(), Y{5.5}); + VERIFY( part1 != c.end() ); + VERIFY( part1->val == 5.0 ); + auto part2 = std::lower_bound(c.begin(), c.end(), Y{5.5}, std::less<Y>{}); + VERIFY( part2 != c.end() ); + VERIFY( part2->val == 5.0 ); + + auto part3 = std::lower_bound(c.begin(), c.end(), Y{1.0}); + VERIFY( part3 != c.end() ); + VERIFY( part3->val == 1.2 ); + auto part4 = std::lower_bound(c.begin(), c.end(), Y{1.0}, std::less<Y>{}); + VERIFY( part4 != c.end() ); + VERIFY( part4->val == 1.2 ); +} + +int +main() +{ + test01(); + test02(); +} diff --git a/libstdc++-v3/testsuite/25_algorithms/upper_bound/partitioned.cc b/libstdc++-v3/testsuite/25_algorithms/upper_bound/partitioned.cc new file mode 100644 index 00000000000..96cfb2e2ded --- /dev/null +++ b/libstdc++-v3/testsuite/25_algorithms/upper_bound/partitioned.cc @@ -0,0 +1,98 @@ +// Copyright (C) 2016 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// { dg-options "-std=gnu++11 -D_GLIBCXX_DEBUG" } + +#include <algorithm> +#include <functional> +#include <testsuite_iterators.h> +#include <testsuite_hooks.h> + +using __gnu_test::test_container; +using __gnu_test::forward_iterator_wrapper; + +struct X +{ + int val; + + bool odd() const { return val % 2; } + + // Partitioned so that all odd values come before even values: + bool operator<(const X& x) const { return this->odd() && !x.odd(); } +}; + +void +test01() +{ + bool test __attribute((unused)) = true; + + // Test with range that is partitioned, but not sorted. + X seq[] = { 1, 3, 5, 7, 1, 6, 4, 2 }; + test_container<X, forward_iterator_wrapper> c(seq); + + auto part1 = std::upper_bound(c.begin(), c.end(), X{2}); + VERIFY( part1 == c.end() ); + auto part2 = std::upper_bound(c.begin(), c.end(), X{2}, std::less<X>{}); + VERIFY( part2 == c.end() ); + + auto part3 = std::upper_bound(c.begin(), c.end(), X{9}); + VERIFY( part3 != c.end() ); + VERIFY( part3->val == 6 ); + auto part4 = std::upper_bound(c.begin(), c.end(), X{9}, std::less<X>{}); + VERIFY( part3 != c.end() ); + VERIFY( part4->val == 6 ); +} + +struct Y +{ + double val; + + // Not irreflexive, so not a strict weak order. + bool operator<(const Y& y) const { return val < (int)y.val; } +}; + +void +test02() +{ + bool test __attribute((unused)) = true; + + // Test that Debug Mode checks don't fire (libstdc++/71545) + + Y seq[] = { -0.1, 1.2, 5.0, 5.2, 5.1, 5.9, 5.5, 6.0 }; + test_container<Y, forward_iterator_wrapper> c(seq); + + auto part1 = std::upper_bound(c.begin(), c.end(), Y{5.5}); + VERIFY( part1 != c.end() ); + VERIFY( part1->val == 6.0 ); + auto part2 = std::upper_bound(c.begin(), c.end(), Y{5.5}, std::less<Y>{}); + VERIFY( part2 != c.end() ); + VERIFY( part2->val == 6.0 ); + + auto part3 = std::upper_bound(c.begin(), c.end(), Y{1.0}); + VERIFY( part3 != c.end() ); + VERIFY( part3->val == 5.0 ); + auto part4 = std::upper_bound(c.begin(), c.end(), Y{1.0}, std::less<Y>{}); + VERIFY( part4 != c.end() ); + VERIFY( part4->val == 5.0 ); +} + +int +main() +{ + test01(); + test02(); +} diff --git a/libstdc++-v3/testsuite/experimental/any/misc/any_cast.cc b/libstdc++-v3/testsuite/experimental/any/misc/any_cast.cc index ce3f2135889..bb0f754f549 100644 --- a/libstdc++-v3/testsuite/experimental/any/misc/any_cast.cc +++ b/libstdc++-v3/testsuite/experimental/any/misc/any_cast.cc @@ -77,8 +77,38 @@ void test02() } } +static int move_count = 0; + +void test03() +{ + struct MoveEnabled + { + MoveEnabled(MoveEnabled&&) + { + ++move_count; + } + MoveEnabled() = default; + MoveEnabled(const MoveEnabled&) = default; + }; + MoveEnabled m; + MoveEnabled m2 = any_cast<MoveEnabled>(any(m)); + VERIFY(move_count == 1); + MoveEnabled&& m3 = any_cast<MoveEnabled&&>(any(m)); + VERIFY(move_count == 1); + struct MoveDeleted + { + MoveDeleted(MoveDeleted&&) = delete; + MoveDeleted() = default; + MoveDeleted(const MoveDeleted&) = default; + }; + MoveDeleted md; + MoveDeleted&& md2 = any_cast<MoveDeleted>(any(std::move(md))); + MoveDeleted&& md3 = any_cast<MoveDeleted&&>(any(std::move(md))); +} + int main() { test01(); test02(); + test03(); } diff --git a/libstdc++-v3/testsuite/experimental/any/misc/any_cast_neg.cc b/libstdc++-v3/testsuite/experimental/any/misc/any_cast_neg.cc index 1361db89d4c..82957a1f544 100644 --- a/libstdc++-v3/testsuite/experimental/any/misc/any_cast_neg.cc +++ b/libstdc++-v3/testsuite/experimental/any/misc/any_cast_neg.cc @@ -26,5 +26,5 @@ void test01() using std::experimental::any_cast; const any y(1); - any_cast<int&>(y); // { dg-error "qualifiers" "" { target { *-*-* } } 353 } + any_cast<int&>(y); // { dg-error "qualifiers" "" { target { *-*-* } } 368 } } diff --git a/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directories.cc b/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directories.cc index 4be41a6c47c..a52efe4ce5c 100644 --- a/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directories.cc +++ b/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directories.cc @@ -65,7 +65,8 @@ test01() VERIFY( b ); VERIFY( is_directory(p/"./d4/../d5") ); - remove_all(p, ec); + std::uintmax_t count = remove_all(p, ec); + VERIFY( count == 6 ); } int diff --git a/libstdc++-v3/testsuite/experimental/optional/cons/value.cc b/libstdc++-v3/testsuite/experimental/optional/cons/value.cc index a916951b874..123a89ede04 100644 --- a/libstdc++-v3/testsuite/experimental/optional/cons/value.cc +++ b/libstdc++-v3/testsuite/experimental/optional/cons/value.cc @@ -22,6 +22,7 @@ #include <testsuite_hooks.h> #include <vector> +#include <string> struct tracker { @@ -236,4 +237,22 @@ int main() VERIFY( result == caught ); } + + { + std::experimental::optional<std::string> os = "foo"; + struct X + { + explicit X(int) {} + X& operator=(int) {return *this;} + }; + std::experimental::optional<X> ox{42}; + std::experimental::optional<int> oi{42}; + std::experimental::optional<X> ox2{oi}; + std::experimental::optional<std::string> os2; + os2 = "foo"; + std::experimental::optional<X> ox3; + ox3 = 42; + std::experimental::optional<X> ox4; + ox4 = oi; + } } diff --git a/libstdc++-v3/testsuite/experimental/optional/cons/value_neg.cc b/libstdc++-v3/testsuite/experimental/optional/cons/value_neg.cc new file mode 100644 index 00000000000..c862a04986a --- /dev/null +++ b/libstdc++-v3/testsuite/experimental/optional/cons/value_neg.cc @@ -0,0 +1,39 @@ +// { dg-options "-std=gnu++14" } +// { dg-do compile } + +// Copyright (C) 2013-2016 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a moved_to of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +#include <experimental/optional> +#include <testsuite_hooks.h> + +#include <string> +#include <memory> + +int main() +{ + { + struct X + { + explicit X(int) {} + }; + std::experimental::optional<X> ox{42}; + std::experimental::optional<X> ox2 = 42; // { dg-error "conversion" } + std::experimental::optional<std::unique_ptr<int>> oup{new int}; + std::experimental::optional<std::unique_ptr<int>> oup2 = new int; // { dg-error "conversion" } + } +} diff --git a/libstdc++-v3/testsuite/util/testsuite_iterators.h b/libstdc++-v3/testsuite/util/testsuite_iterators.h index f7491659233..19b7cdc32a0 100644 --- a/libstdc++-v3/testsuite/util/testsuite_iterators.h +++ b/libstdc++-v3/testsuite/util/testsuite_iterators.h @@ -542,6 +542,13 @@ namespace __gnu_test test_container(T* _first, T* _last):bounds(_first, _last) { } +#if __cplusplus >= 201103L + template<std::size_t N> + explicit + test_container(T (&arr)[N]) : test_container(arr, arr+N) + { } +#endif + ItType<T> it(int pos) { diff --git a/maintainer-scripts/ChangeLog b/maintainer-scripts/ChangeLog index 1014033e332..485a48c64f0 100644 --- a/maintainer-scripts/ChangeLog +++ b/maintainer-scripts/ChangeLog @@ -1,3 +1,8 @@ +2016-06-13 Jonathan Wakely <jwakely@redhat.com> + + * generate_libstdcxx_web_docs: Use realpath to get absolute path. + Add comment about LaTeX errors. + 2016-04-27 Release Manager * GCC 6.1.0 released. diff --git a/maintainer-scripts/generate_libstdcxx_web_docs b/maintainer-scripts/generate_libstdcxx_web_docs index 700e522e25c..00ebcbf7f67 100755 --- a/maintainer-scripts/generate_libstdcxx_web_docs +++ b/maintainer-scripts/generate_libstdcxx_web_docs @@ -3,7 +3,7 @@ # i.e. http://gcc.gnu.org/onlinedocs/gcc-x.y.z/libstdc++* SRCDIR=${1} -DOCSDIR=${2} +DOCSDIR=$(realpath ${2}) if ! [ $# -eq 2 -a -x "${SRCDIR}/configure" -a -d "${DOCSDIR}" ] then @@ -34,6 +34,9 @@ set -x ${SRCDIR}/configure --enable-languages=c,c++ --disable-gcc $disabled_libs --docdir=/docs eval `grep '^target=' config.log` make configure-target +# If the following step fails with an error like +# ! LaTeX Error: File `xtab.sty' not found. +# then you need to install the relevant TeX package e.g. texlive-xtab make -C $target/libstdc++-v3 doc-install-html doc-install-xml doc-install-pdf DESTDIR=$DESTDIR cd $DESTDIR/docs mkdir libstdc++ |