Add new fusion patchesibm/addr3

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/addr3@265898 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 24 insertions, 22 deletions

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index ec9c86f2ef5..89c0384424e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,16 @@
 2018-11-07  Michael Meissner  <meissner@linux.ibm.com>
 
+	* config/rs6000/predicates.md (fusion_gpr_addis): ADDIS for power8
+	must have the top 12 bits all 0/-1, not 11 bits.
+	(fusion_addis_mem_combo_load): Don't allow FLOAT_EXTEND.
+	* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_NO_FUSION): Delete.
+	(ISA_2_7_MASKS_SERVER): Define without power8 fusion.
+	* config/rs6000/rs6000.c (rs6000_option_override_internal): Set
+	power8 fusion only if we are tuning for power8.
+	* config/rs6000/rs6000.opt (-mpower9-fusion): Delete.
+
+2018-11-07  Michael Meissner  <meissner@linux.ibm.com>
+
 	* config/rs6000/rs6000-addr.c (get_toc_ref): Don't optimize
 	references to the constant pool.
 	(toc_refs::add): If we have exhuasted the number of base pointers,
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index e02978d41a7..abb94dca6e1 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1649,9 +1649,9 @@
   if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
     return 0;
 
-  /* Power8 currently will only do the fusion if the top 11 bits of the addis
-     value are all 1's or 0's.  */
-  return (IN_RANGE (value >> 16, -32, 31));
+  /* Power8 only does the fusion if the top 12 bits of the addis value are all
+     1's or 0's.  */
+  return (IN_RANGE (value >> 16, -16, 15));
 })
 
 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
@@ -1719,7 +1719,7 @@
 ;; memory field with both the addis and the memory offset.  Sign extension
 ;; is not handled here, since lha and lwa are not fused.
 (define_predicate "fusion_addis_mem_combo_load"
-  (match_code "mem,zero_extend,float_extend")
+  (match_code "mem,zero_extend")
 {
   rtx addr, base, offset;
 
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 39cd6c0ddbc..b980ae4f445 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -44,10 +44,10 @@
 				 | OPTION_MASK_ALTIVEC			\
 				 | OPTION_MASK_VSX)
 
-/* For now, don't provide an embedded version of ISA 2.07.  Power9 does not
-   support power8 fusion.  Provide a version of the masks with fusion set and
-   one without.  */
-#define ISA_2_7_MASKS_NO_FUSION	(ISA_2_6_MASKS_SERVER			\
+/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
+   fusion here, instead set it in rs6000.c if we are tuning for a power8
+   system.  */
+#define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
 				 | OPTION_MASK_P8_VECTOR		\
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_DIRECT_MOVE		\
@@ -56,13 +56,9 @@
 				 | OPTION_MASK_QUAD_MEMORY		\
 				 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
 
-#define ISA_2_7_MASKS_SERVER	(ISA_2_7_MASKS_NO_FUSION		\
-  				 | OPTION_MASK_P8_FUSION)
-
 /* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
-   FLOAT128_HW here until we are ready to make -mfloat128 on by default.
-   Power9 did not support power8 fusion, so disable it by default.  */
-#define ISA_3_0_MASKS_SERVER	(ISA_2_7_MASKS_NO_FUSION		\
+   FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
+#define ISA_3_0_MASKS_SERVER	(ISA_2_7_MASKS_SERVER			\
 				 | OPTION_MASK_ISEL			\
 				 | OPTION_MASK_MODULO			\
 				 | OPTION_MASK_P9_MINMAX		\
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 61458c29fab..22e37b1cf89 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4166,13 +4166,11 @@ rs6000_option_override_internal (bool global_init_p)
     rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
 
   /* Enable power8 fusion if we are tuning for power8, even if we aren't
-     generating power8 instructions.  The power9 cpu does not set the power8
-     fusion option mask, so if you tune for power9 it will not add fusion
-     support.  */
+     generating power8 instructions.  Power9 does not optimize power8 fusion
+     cases.  */
   if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
     {
-      if (processor_target_table[tune_index].target_enable
-	  & OPTION_MASK_P8_FUSION)
+      if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
 	rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
       else
 	rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 5f8e925b803..05d773d0377 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -498,9 +498,6 @@ moptimize-swaps
 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
 Analyze and remove doubleword swaps from VSX computations.
 
-mpower9-fusion
-Target Undocumented Mask(P9_FUSION) Var(rs6000_isa_flags) Deprecated
-
 mpower9-misc
 Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
 Use certain scalar instructions added in ISA 3.0.