fixed one compile error but others remain because I need to bounce off of trunkibm/restart-rfc2464

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/restart-rfc2464@238006 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 200 insertions, 0 deletions

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 5fb051af636..f71e6af2578 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -147,6 +147,11 @@
   (and (match_code "const_int")
        (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
 
+;; Return 1 if op is an unsigned 7-bit constant integer.
+(define_predicate "u7bit_cint_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) >= 0 && UINTVAL (op) <= 127")))
+
 ;; Return 1 if op is a signed 8-bit constant integer.
 ;; Integer multiplication complete more quickly
 (define_predicate "s8bit_cint_operand"
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index a67b2d91b4e..83dd9af4f5f 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -69,6 +69,7 @@
 				 | OPTION_MASK_MODULO			\
 				 | OPTION_MASK_P9_FUSION		\
 				 | OPTION_MASK_P9_DFORM_SCALAR		\
+				 | OPTION_MASK_P9_MISC			\
 				 | OPTION_MASK_P9_VECTOR)
 
 #define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
@@ -108,6 +109,7 @@
 				 | OPTION_MASK_P9_DFORM_VECTOR		\
 				 | OPTION_MASK_P9_FUSION		\
 				 | OPTION_MASK_P9_MINMAX		\
+				 | OPTION_MASK_P9_MISC			\
 				 | OPTION_MASK_P9_VECTOR		\
 				 | OPTION_MASK_POPCNTB			\
 				 | OPTION_MASK_POPCNTD			\
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4762c21b7a1..b753264ac4a 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -13391,6 +13391,20 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
 	  return const0_rtx;
 	}
     }
+  else if (icode == CODE_FOR_xststdcdp
+	   || icode == CODE_FOR_xststdcsp
+	   || icode == CODE_FOR_xvtstdcdp
+	   || icode == CODE_FOR_xvtstdcsp)
+    {
+      /* Only allow 7-bit unsigned literals. */
+      STRIP_NOPS (arg1);
+      if (TREE_CODE (arg1) != INTEGER_CST
+	  || TREE_INT_CST_LOW (arg1) & ~0x7f)
+	{
+	  error ("argument 2 must be a 7-bit unsigned literal");
+	  return CONST0_RTX (tmode);
+	}
+    }
 
   if (target == 0
       || GET_MODE (target) != tmode
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a07d66e17f0..320c4f1a1ef 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -18,6 +18,9 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
+;; Iterator for comparison types
+(define_code_iterator CMP_TEST [eq lt gt unordered])
+
 ;; Iterator for both scalar and vector floating point types supported by VSX
 (define_mode_iterator VSX_B [DF V4SF V2DF])
 
@@ -43,6 +46,10 @@
 ;; Iterator for vector floating point types supported by VSX
 (define_mode_iterator VSX_F [V4SF V2DF])
 
+(define_mode_attr vsx_f_suffix [(V4SF "dp") (V2DF "sp")])
+;; (define_mode_attr VSX_F_SUFFIX [(V4SF "DP") (V2DF "SP")])
+(define_mode_attr VSX_F_INTEGER [(V4SF "V4SI") (V2DF "V2DI")])
+
 ;; Iterator for logical types supported by VSX
 (define_mode_iterator VSX_L [V16QI
 			     V8HI
@@ -293,6 +300,21 @@
    UNSPEC_VSX_XVCVDPSXDS
    UNSPEC_VSX_XVCVDPUXDS
    UNSPEC_VSX_SIGN_EXTEND
+;; kelvin's new unspecs for rfc02464
+   UNSPEC_VSX_SXEXPDP
+   UNSPEC_VSX_SXSIGDP
+   UNSPEC_VSX_SIEXPDP
+   UNSPEC_VSX_SCMPEXPDP
+;; vsx scalar test data class double- and single-precision
+   UNSPEC_VSX_STSTDC
+;; vsx vector extract exponent double- and single-precision
+   UNSPEC_VSX_VXEXP
+;; vsx vector extract significand double- and single-precision
+   UNSPEC_VSX_VXSIG
+;; vsx vector insert exponent double- and single-precision
+   UNSPEC_VSX_VIEXP
+;; vsx vector test data class double- and single-precision
+   UNSPEC_VSX_VTSTDC
   ])
 
 ;; VSX moves
@@ -2721,3 +2743,160 @@
   "TARGET_P9_VECTOR"
   "vextsw2d %0,%1"
   [(set_attr "type" "vecsimple")])
+
+;; ISA 3.0 Binary Floating-Point Support
+
+;; VSX Scalar Extract Exponent Double-Precision
+(define_insn "xsxexpdp"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+  	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")] 
+        UNSPEC_VSX_SXEXPDP))]
+  "TARGET_P9_VECTOR"
+  "xsxexpdp %0,%x1"
+  [(set_attr "type" "fp")])
+
+;; VSX Scalar Extract Significand Double-Precision
+(define_insn "xsxsigdp"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+  	(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")] 
+        UNSPEC_VSX_SXSIGDP))]
+  "TARGET_P9_VECTOR"
+  "xsxsigdp %0,%x1"
+  [(set_attr "type" "fp")])
+
+;; VSX Scalar Insert Exponent Double-Precision
+(define_insn "xsiexpdp"
+  [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
+  	(unspec:DF [(match_operand:DI 1 "register_operand" "r")
+		    (match_operand:DI 2 "register_operand" "r")]
+        UNSPEC_VSX_SIEXPDP))]
+  "TARGET_P9_VECTOR"
+  "xsxsigdp %x0,%1"
+  [(set_attr "type" "fp")])
+
+(define_insn "*xsiexpdp"
+  [(set (match_operand:CCFP 0 "" "=y")
+        (compare:CCFP
+         (unspec:DF [(match_operand:DF 1 "vsx_register_operand" "wa")
+                     (match_operand:DF 2 "vsx_register_operand" "wa")]
+	  UNSPEC_VSX_SIEXPDP)
+         (match_operand:SI 3 "zero_constant" "j")))]
+  "TARGET_P9_VECTOR"
+  "xsiexpdp %0,%x1,%x2"
+  [(set_attr "type" "fp")])
+
+;; VSX Scalar Compare Exponents Double-Precision
+(define_expand "xscmpexpdp_<code>"
+  [(set (match_dup 3)
+        (compare:CCFP
+         (unspec:DF
+          [(match_operand:DF 1 "vsx_register_operand" "wa")
+           (match_operand:DF 2 "vsx_register_operand" "wa")]
+	  UNSPEC_VSX_SCMPEXPDP)
+        (match_dup 4)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+        (CMP_TEST:SI (match_dup 3)
+                     (const_int 0)))
+  ]
+  "TARGET_P9_VECTOR"
+{
+  operands[3] = gen_reg_rtx (CCFPmode);
+  operands[4] = CONST0_RTX (SImode);
+})
+
+;; VSX Scalar Test Data Class Double- and Single-Precision
+;;  (The lt bit is set if operand 1 is negative.  The eq bit is set 
+;;   if any of the conditions tested by operand 2 are satisfied.  
+;;   The gt and unordered bits are cleared to zero.)
+(define_expand "xststdc<vsx_f_suffix>"
+  [(set (match_dup 3)
+        (compare:CCFP
+         (unspec:VSX_F
+          [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
+           (match_operand:SI 2 "u7bit_cint_operand" "n")]
+          UNSPEC_VSX_STSTDC)
+        (match_dup 4)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+        (eq:SI (match_dup 3)
+               (const_int 0)))
+  ]
+  "TARGET_P9_VECTOR"
+{
+  operands[3] = gen_reg_rtx (CCFPmode);
+  operands[4] = CONST0_RTX (SImode);
+})
+
+;; The VSX Scalar Test Data Class Double- and Single-Precision
+;; instruction may also be used to test for negative value.
+(define_expand "xststdc<vsx_f_suffix>_neg"
+  [(set (match_dup 2)
+        (compare:CCFP
+         (unspec:VSX_F
+          [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
+           (const_int 0)]
+          UNSPEC_VSX_STSTDC)
+        (match_dup 3)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+        (lt:SI (match_dup 2)
+               (const_int 0)))
+  ]
+  "TARGET_P9_VECTOR"
+{
+  operands[2] = gen_reg_rtx (CCFPmode);
+  operands[3] = CONST0_RTX (SImode);
+})
+
+(define_insn "*xststdc<vsx_f_suffix>"
+  [(set (match_operand:CCFP 0 "" "=y")
+        (compare:CCFP
+         (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
+                     (match_operand:SI 2 "u7bit_cint_operand" "n")]
+          UNSPEC_VSX_STSTDC)
+         (match_operand:SI 3 "zero_constant" "j")))]
+  "TARGET_P9_VECTOR"
+  "xststdc<vsx_f_suffix> %0,%x1,%2"
+  [(set_attr "type" "fp")])
+
+;; VSX Vector Extract Exponent Double and Single Precision
+(define_insn "xvxexp<vsx_f_suffix>"
+  [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+        (unspec:VSX_F 
+         [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
+         UNSPEC_VSX_VXEXP))]
+  "TARGET_P9_VECTOR"
+  "xvxexp<vsx_f_suffix> %x0,%x1"
+  [(set_attr "type" "fp")])
+
+;; VSX Vector Extract Significand Double and Single Precision
+(define_insn "xvxsig<vsx_f_suffix>"
+  [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+        (unspec:VSX_F 
+         [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
+         UNSPEC_VSX_VXSIG))]
+  "TARGET_P9_VECTOR"
+  "xvxsig<vsx_f_suffix> %x0,%x1"
+  [(set_attr "type" "fp")])
+
+;; VSX Vector Insert Exponent Double and Single Precision
+(define_insn "xviexp<vsx_f_suffix>"
+  [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+        (unspec:VSX_F 
+         [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
+          (match_operand:VSX_F 2 "vsx_register_operand" "wa")]
+         UNSPEC_VSX_VIEXP))]
+  "TARGET_P9_VECTOR"
+  "xviexp<vsx_f_suffix> %x0,%x1,%x2"
+  [(set_attr "type" "fp")])
+
+;; VSX Vector Test Data Class Double and Single Precision
+;;  The corresponding elements of the result vector are all ones
+;;   if any of the conditions tested by operand 3 are satisfied.  
+(define_insn "xvtstdc<vsx_f_suffix>"
+  [(set (match_operand:<VSX_F_INTEGER> 0 "vsx_register_operand" "=wa")
+        (unspec:<VSX_F_INTEGER>
+         [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
+          (match_operand:SI 2 "u7bit_cint_operand" "n")]
+         UNSPEC_VSX_VTSTDC))]
+  "TARGET_P9_VECTOR"
+  "xvtstdc<vsx_f_suffix> %x0,%x1,%x2"
+  [(set_attr "type" "fp")])