* ChangeLog.2, ChangeLog.3, ChangeLog.5, ChangeLog, alias.c,

	cfgbuild.c, expmed.c, expr.c, final.c, flow.c, fold-const.c,
	function.c, config/alpha/alpha.md, config/alpha/vms-ld.c,
	config/arm/arm.c, config/arm/arm.h, config/c4x/libgcc.S,
	config/i370/i370.c, config/i386/i386.c,
	config/i386/i386-interix.h, config/i386/i386.md,
	config/i386/i386.h, config/i386/netbsd-elf.h, config/ia64/ia64.c,
	config/m32r/m32r-protos.h, config/mcore/mcore.h,
	config/rs6000/rs6000.h, config/sparc/linux64.h,
	config/sparc/sparc.c, config/v850/v850-protos.h,
	config/cris/cris.h, config/s390/s390.md, config/elfos.h: Fix
	spelling errors.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@47815 138bc75d-0d04-0410-961f-82ee72b054a4

33 files changed, 90 insertions, 75 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a94566044f3..44ddefb025a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2001-12-09  Joseph S. Myers  <jsm28@cam.ac.uk>
+
+	* ChangeLog.2, ChangeLog.3, ChangeLog.5, ChangeLog, alias.c,
+	cfgbuild.c, expmed.c, expr.c, final.c, flow.c, fold-const.c,
+	function.c, config/alpha/alpha.md, config/alpha/vms-ld.c,
+	config/arm/arm.c, config/arm/arm.h, config/c4x/libgcc.S,
+	config/i370/i370.c, config/i386/i386.c,
+	config/i386/i386-interix.h, config/i386/i386.md,
+	config/i386/i386.h, config/i386/netbsd-elf.h, config/ia64/ia64.c,
+	config/m32r/m32r-protos.h, config/mcore/mcore.h,
+	config/rs6000/rs6000.h, config/sparc/linux64.h,
+	config/sparc/sparc.c, config/v850/v850-protos.h,
+	config/cris/cris.h, config/s390/s390.md, config/elfos.h: Fix
+	spelling errors.
+
 2001-12-09  Daniel Berlin  <dan@cgsoftware.com>
 
 	* config/rs6000/rs6000.h (enum rs6000_builtins): Add remaining
@@ -101,7 +116,7 @@
 	* arm.h (arm_builtins): Delete ARM_BUILTIN_PREFETCH).
 	* arm.c (arm_init_builtins): Don't initialize a builtin for
 	__builtin_prefetch here.
-	(arm_expand_builtin): Dont expand __builtin_prefetch here.
+	(arm_expand_builtin): Don't expand __builtin_prefetch here.
 
 2001-12-08  Richard Earnshaw  <rearnsha@arm.com>
 
@@ -1104,11 +1119,11 @@ objc:
 
 	* config/rs6000/rs6000.md: Add attribute types vecsimple,
 	veccomplex, vecfloat, and vecperm, for altivec instructions.
-	Modify altivec patterns to use approriate attribute type.
-	Modify altivec patterns to match RTL operations where approriate
+	Modify altivec patterns to use appropriate attribute type.
+	Modify altivec patterns to match RTL operations where appropriate
 	(IE no unspec where we can avoid it).
 	Add vector unit scheduling for ppc7450.
-	Rename patterns to what they are where approriate
+	Rename patterns to what they are where appropriate
 	(altivec_vaddfp->addv4sf3, etc)
 
 	* config/rs6000/rs6000.h (enum rs6000_builtins): Change VRS->VSR.
diff --git a/gcc/ChangeLog.2 b/gcc/ChangeLog.2
index 95138e6bda3..e49d764994a 100644
--- a/gcc/ChangeLog.2
+++ b/gcc/ChangeLog.2
@@ -5307,7 +5307,7 @@ Thu Oct 14 01:49:54 1999  Richard Henderson  <rth@cygnus.com>
 	(NUM_SPECIAL_MODE_PREDS): New.
 	(find_operand): New.
 	(validate_pattern): New argument `insn'.  Warn for assignment to
-	any predicate accepting non-lvalues.  Conditionaly warn for
+	any predicate accepting non-lvalues.  Conditionally warn for
 	match_operand without a mode.  Try much harder to match source
 	and destination modes on a set.
 	* tm.texi (SPECIAL_MODE_PREDICATES): Document.
@@ -14051,7 +14051,7 @@ Fri Jun  4 03:20:40 1999  J"orn Rennecke <amylaar@cygnus.co.uk>
 	* sh.h (PREDICATE_CODES): Remove braf_label_ref_operand.
 	* sh.md (casesi_jump_2): Operand1 is now the inside of a
 	label_ref, and has no predicate.
-	The patten has a predicate to guard against invalid substitutions.
+	The pattern has a predicate to guard against invalid substitutions.
 	(dummy_jump): Delete.
 	(casesi): Update use of casesi_jump_2.
 
diff --git a/gcc/ChangeLog.3 b/gcc/ChangeLog.3
index 5cbfcaada1d..c3a4461d4af 100644
--- a/gcc/ChangeLog.3
+++ b/gcc/ChangeLog.3
@@ -2667,7 +2667,7 @@ Thu May 25 02:09:10 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
 2000-05-24  Mark Mitchell  <mark@codesourcery.com>
 
 	* calls.c (expand_call): Handle cleanups in tail-recursion
-	arguments analagously to cleanups in sibling calls.
+	arguments analogously to cleanups in sibling calls.
 
 2000-05-24  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
diff --git a/gcc/ChangeLog.5 b/gcc/ChangeLog.5
index b44afad2ec6..40eccd1ef84 100644
--- a/gcc/ChangeLog.5
+++ b/gcc/ChangeLog.5
@@ -12298,7 +12298,7 @@ Tue Jan 16 17:20:43 2001  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 2001-01-14  Ralf Baechle <ralf@gnu.org>
 
 	* config/mips/linux.h (SUBTARGET_CPP_SPEC): Default ABI is 32; change
-	SUBTARGET_CPP_SPEC apropriatly.
+	SUBTARGET_CPP_SPEC appropriately.
 
 2001-01-12  Mark Mitchell  <mark@codesourcery.com>
 
diff --git a/gcc/alias.c b/gcc/alias.c
index 21563ec565e..b39be731173 100644
--- a/gcc/alias.c
+++ b/gcc/alias.c
@@ -1751,7 +1751,7 @@ nonoverlapping_component_refs_p (x, y)
   do
     {
       /* The comparison has to be done at a common type, since we don't
-	 know how the inheritance heirarchy works.  */
+	 know how the inheritance hierarchy works.  */
       orig_y = y;
       do
 	{
diff --git a/gcc/cfgbuild.c b/gcc/cfgbuild.c
index d96911f2f9c..4d57917eeca 100644
--- a/gcc/cfgbuild.c
+++ b/gcc/cfgbuild.c
@@ -133,7 +133,7 @@ control_flow_insn_p (insn)
 
       case BARRIER:
 	/* It is nonsence to reach barrier when looking for the
-	   end of basic block, but before dead code is elliminated
+	   end of basic block, but before dead code is eliminated
 	   this may happen.  */
 	return false;
 
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index f55ed6bce38..c9dbbaea737 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -6633,7 +6633,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   [(set_attr "length" "16")
    (set_attr "type" "multi")])
 
-;; Close the trap shadow of preceeding instructions.  This is generated
+;; Close the trap shadow of preceding instructions.  This is generated
 ;; by alpha_reorg.
 
 (define_insn "trapb"
diff --git a/gcc/config/alpha/vms-ld.c b/gcc/config/alpha/vms-ld.c
index f28b7c79687..c02fe406d91 100644
--- a/gcc/config/alpha/vms-ld.c
+++ b/gcc/config/alpha/vms-ld.c
@@ -82,7 +82,7 @@ static char *search_dirs;
 /* Local function declarations.  */
 
 /* Add STR to the list of arguments to pass to the linker. Expand the list as
-   necessary to accomodate.  */
+   necessary to accommodate.  */
 static void addarg PARAMS ((const char *));
 
 /* Check to see if NAME is a regular file, i.e. not a directory */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c9e20d39088..98b9230a8e6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2132,8 +2132,8 @@ current_file_function_operand (sym_ref)
     return 1;
 
   /* The current function is always defined within the current compilation
-     unit.  if it s a weak defintion however, then this may not be the real
-     defintion of the function, and so we have to say no.  */
+     unit.  if it s a weak definition however, then this may not be the real
+     definition of the function, and so we have to say no.  */
   if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
       && !DECL_WEAK (current_function_decl))
     return 1;
@@ -5348,7 +5348,7 @@ move_minipool_fix_forward_ref (mp, max_mp, max_address)
   /* Save the new entry.  */
   max_mp = mp;
 
-  /* Scan over the preceeding entries and adjust their addresses as
+  /* Scan over the preceding entries and adjust their addresses as
      required.  */
   while (mp->prev != NULL
 	 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
@@ -5454,7 +5454,7 @@ add_minipool_forward_ref (fix)
   /* Save the new entry.  */
   max_mp = mp;
 
-  /* Scan over the preceeding entries and adjust their addresses as
+  /* Scan over the preceding entries and adjust their addresses as
      required.  */
   while (mp->prev != NULL
 	 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 4cb0954db21..b27192e9d21 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -908,7 +908,7 @@ extern const char * structure_size_string;
 #if 0 /* FIXME: The ARM backend has special code to handle structure
 	 returns, and will reserve its own hidden first argument.  So
 	 if this macro is enabled a *second* hidden argument will be
-	 reserved, which will break binary compatability with old
+	 reserved, which will break binary compatibility with old
 	 toolchains and also thunk handling.  One day this should be
 	 fixed.  */
 /* RTX for structure returns.  NULL means use a hidden first argument.  */
@@ -1044,7 +1044,7 @@ extern const char * structure_size_string;
 /* Register and constant classes.  */
 
 /* Register classes: used to be simple, just all ARM regs or all FPU regs
-   Now that the Thumb is involved it has become more compilcated.  */
+   Now that the Thumb is involved it has become more complicated.  */
 enum reg_class
 {
   NO_REGS,
@@ -1626,7 +1626,7 @@ typedef struct
    pointer register.  Secondly, the pseudo frame pointer register can always
    be eliminated; it is replaced with either the stack or the real frame
    pointer.  Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
-   because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant.  */
+   because the definition of HARD_FRAME_POINTER_REGNUM is not a constant.  */
 
 #define ELIMINABLE_REGS						\
 {{ ARG_POINTER_REGNUM,        STACK_POINTER_REGNUM            },\
diff --git a/gcc/config/c4x/libgcc.S b/gcc/config/c4x/libgcc.S
index c3b3c7e56ae..96b27d862ca 100644
--- a/gcc/config/c4x/libgcc.S
+++ b/gcc/config/c4x/libgcc.S
@@ -1021,7 +1021,7 @@ mod3:
 #endif
 
 ;
-; double to signed long long converion
+; double to signed long long conversion
 ; input in r2
 ; result in r0,r1
 ;
@@ -1049,7 +1049,7 @@ ___fix_truncqfhi2:
 #endif
 
 ;
-; double to unsigned long long converion
+; double to unsigned long long conversion
 ; input in r2
 ; result in r0,r1
 ;
@@ -1095,7 +1095,7 @@ ufix1:
 #endif
 
 ;
-; signed long long to double converion
+; signed long long to double conversion
 ; input on stack
 ; result in r0
 ;
@@ -1116,7 +1116,7 @@ ___floathiqf2:
 #endif
 
 ;
-; unsigned long long to double converion
+; unsigned long long to double conversion
 ; input on stack
 ; result in r0
 ;
@@ -1166,7 +1166,7 @@ uflt2:
 #endif
 
 ;
-; long double to signed long long converion
+; long double to signed long long conversion
 ; input in r2
 ; result in r0,r1
 ;
@@ -1195,7 +1195,7 @@ ___fix_trunchfhi2:
 #endif
 
 ;
-; long double to unsigned long long converion
+; long double to unsigned long long conversion
 ; input in r2
 ; result in r0,r1
 ;
@@ -1242,7 +1242,7 @@ ufixh1:
 #endif
 
 ;
-; signed long long to long double converion
+; signed long long to long double conversion
 ; input on stack
 ; result in r0
 ;
@@ -1263,7 +1263,7 @@ ___floathihf2:
 #endif
 
 ;
-; unsigned long long to double converion
+; unsigned long long to double conversion
 ; input on stack
 ; result in r0
 ;
diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index a31a93f0e84..d4ed6bc1053 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -1603,7 +1603,7 @@ struct cum_args {int regs;};
    tricks with the symbol type.  Not good if other tools than binutils
    are used on the object files.  Since ".global ... .lcomm ..." works, we
    use that.  Use .._ALIGNED_COMMON, since gcc whines when we only have
-   ..._COMMON, and we prefer to whine outselves; BIGGEST_ALIGNMENT is not
+   ..._COMMON, and we prefer to whine ourselves; BIGGEST_ALIGNMENT is not
    the one to check.  This done for a.out only.  */
 /* FIXME: I suspect a bug in gcc with alignment.  Do not warn until
    investigated; it mucks up the testsuite results.  */
diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h
index c4a1b299665..33e88154af3 100644
--- a/gcc/config/elfos.h
+++ b/gcc/config/elfos.h
@@ -358,7 +358,7 @@ const_section ()						\
      relocations, so they get grouped together and dynamic linker
      will visit fewer pages in memory.
    .ro
-     Marks data read only otherwise.  This is usefull with prelinking
+     Marks data read only otherwise.  This is useful with prelinking
      as most of relocations won't be dynamically linked and thus
      stay read only.
    .local
diff --git a/gcc/config/i370/i370.c b/gcc/config/i370/i370.c
index 16dc9a93d48..bbe27823e0a 100644
--- a/gcc/config/i370/i370.c
+++ b/gcc/config/i370/i370.c
@@ -504,7 +504,7 @@ i370_label_scan ()
                else 
                  {
 /* XXX hack alert.
-   Compiling the execption handling (L_eh) in libgcc2.a will trip
+   Compiling the exception handling (L_eh) in libgcc2.a will trip
    up right here, with something that looks like
    (set (pc) (mem:SI (plus:SI (reg/v:SI 1 r1) (const_int 4))))
       {indirect_jump} 
diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h
index f94d9c87353..1eae0863827 100644
--- a/gcc/config/i386/i386-interix.h
+++ b/gcc/config/i386/i386-interix.h
@@ -26,7 +26,7 @@ Boston, MA 02111-1307, USA.  */
 
 #define YES_UNDERSCORES
 
-/* YES_UNDERSCORES must preceed gas.h */
+/* YES_UNDERSCORES must precede gas.h */
 #include <i386/gas.h>
 /* The rest must follow.  */
 
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 760a15c86b0..703023acbdf 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1603,13 +1603,13 @@ classify_argument (mode, type, classes, bit_offset)
 	  if (classes[i] == X86_64_MEMORY_CLASS)
 	    return 0;
 
-	  /* The X86_64_SSEUP_CLASS should be always preceeded by
+	  /* The X86_64_SSEUP_CLASS should be always preceded by
 	     X86_64_SSE_CLASS.  */
 	  if (classes[i] == X86_64_SSEUP_CLASS
 	      && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
 	    classes[i] = X86_64_SSE_CLASS;
 
-	  /*  X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS.  */
+	  /*  X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS.  */
 	  if (classes[i] == X86_64_X87UP_CLASS
 	      && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
 	    classes[i] = X86_64_SSE_CLASS;
@@ -2579,7 +2579,7 @@ x86_64_general_operand (op, mode)
 }
 
 /* Return nonzero if OP is general operand representable on x86_64
-   as eighter sign extended or zero extended constant.  */
+   as either sign extended or zero extended constant.  */
 
 int
 x86_64_szext_general_operand (op, mode)
@@ -3475,7 +3475,7 @@ x86_64_sign_extended_value (value)
 		  /* For CM_KERNEL we know that all object resist in the
 		     negative half of 32bits address space.  We may not
 		     accept negative offsets, since they may be just off
-		     and we may accept pretty large possitive ones.  */
+		     and we may accept pretty large positive ones.  */
 		  if (ix86_cmodel == CM_KERNEL
 		      && offset > 0
 		      && trunc_int_for_mode (offset, SImode) == offset)
@@ -3545,7 +3545,7 @@ x86_64_zero_extended_value (value)
 	      {
 		case SYMBOL_REF:
 		    return 0;
-		  /* For small code model we may accept pretty large possitive
+		  /* For small code model we may accept pretty large positive
 		     offsets, since one bit is available for free.  Negative
 		     offsets are limited by the size of NULL pointer area
 		     specified by the ABI.  */
@@ -3557,7 +3557,7 @@ x86_64_zero_extended_value (value)
 		    return 1;
 	          /* ??? For the kernel, we may accept adjustment of
 		     -0x10000000, since we know that it will just convert
-		     negative address space to possitive, but perhaps this
+		     negative address space to positive, but perhaps this
 		     is not worthwhile.  */
 		  break;
 		case LABEL_REF:
@@ -6635,7 +6635,7 @@ ix86_binary_operator_ok (code, mode, operands)
 		&& rtx_equal_p (operands[0], operands[2]))))
     return 0;
   /* If the operation is not commutable and the source 1 is memory, we must
-     have a matching destionation.  */
+     have a matching destination.  */
   if (GET_CODE (operands[1]) == MEM
       && GET_RTX_CLASS (code) != 'c'
       && ! rtx_equal_p (operands[0], operands[1]))
@@ -7572,7 +7572,7 @@ ix86_split_fp_branch (code, op1, op2, target1, target2, tmp)
 	 for UNORDERED.  */
       probability = split_branch_probability;
 
-      /* Value of 1 is low enought to make no need for probability
+      /* Value of 1 is low enough to make no need for probability
 	 to be updated.  Later we may run some experiments and see
 	 if unordered values are more frequent in practice.  */
       if (bypass)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index a7d7702971c..1b24b2fc1da 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1058,7 +1058,7 @@ extern int ix86_arch;
 /* Register to hold the addressing base for position independent
    code access to data items.
    We don't use PIC pointer for 64bit mode.  Define the regnum to
-   dummy value to prevent gcc from pesimizing code dealing with EBX.
+   dummy value to prevent gcc from pessimizing code dealing with EBX.
  */
 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 783aad0c71a..2ca29e0351f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5754,7 +5754,7 @@
 ; case of overflows,  the result is messed up.
 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
 ; when negated.
-; Also carry flag is reversed compared to cmp, so this converison is valid
+; Also carry flag is reversed compared to cmp, so this conversion is valid
 ; only for comparisons not depending on it.
 (define_insn "*adddi_4_rex64"
   [(set (reg 17)
@@ -6182,7 +6182,7 @@
 ; case of overflows,  the result is messed up.
 ; This pattern also don't hold of 0x80000000, since the value overflows
 ; when negated.
-; Also carry flag is reversed compared to cmp, so this converison is valid
+; Also carry flag is reversed compared to cmp, so this conversion is valid
 ; only for comparisons not depending on it.
 (define_insn "*addsi_4"
   [(set (reg 17)
@@ -16306,7 +16306,7 @@
    (set_attr "mode" "DI")])
 
 
-;; Placeholder for the conditional moves.  This one is split eighter to SSE
+;; Placeholder for the conditional moves.  This one is split either to SSE
 ;; based moves emulation or to usual cmove sequence.  Little bit unfortunate
 ;; fact is that compares supported by the cmp??ss instructions are exactly
 ;; swapped of those supported by cmove sequence.
@@ -17149,7 +17149,7 @@
 ;; many CPUs it is also faster, since special hardware to avoid esp
 ;; dependencies is present.
 
-;; While some of these converisons may be done using splitters, we use peepholes
+;; While some of these conversions may be done using splitters, we use peepholes
 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
 
 ;; Convert prologue esp subtractions to push.
diff --git a/gcc/config/i386/netbsd-elf.h b/gcc/config/i386/netbsd-elf.h
index 4f6df1d56ca..cc6f3948539 100644
--- a/gcc/config/i386/netbsd-elf.h
+++ b/gcc/config/i386/netbsd-elf.h
@@ -44,7 +44,7 @@ Boston, MA 02111-1307, USA.  */
         %{!p:crt0%O%s}}} \
    %{!shared:crtbegin%O%s} %{shared:crtbeginS%O%s}"
 
-/* Provide an ENDFILE_SPEC approrpiate for NetBSD ELF targets.  Here we
+/* Provide an ENDFILE_SPEC appropriate for NetBSD ELF targets.  Here we
    add crtend.o, which provides part of the support for getting C++
    file-scope static objects deconstructed after exiting `main'.  */
 
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 52b3ba6c0da..d282b70aebc 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -1673,7 +1673,7 @@ ia64_initial_elimination_offset (from, to)
 
 struct spill_fill_data
 {
-  rtx init_after;		/* point at which to emit intializations */
+  rtx init_after;		/* point at which to emit initializations */
   rtx init_reg[2];		/* initial base register */
   rtx iter_reg[2];		/* the iterator registers */
   rtx *prev_addr[2];		/* address of last memory use */
diff --git a/gcc/config/m32r/m32r-protos.h b/gcc/config/m32r/m32r-protos.h
index 8b51ea16b85..f76e6b918e2 100644
--- a/gcc/config/m32r/m32r-protos.h
+++ b/gcc/config/m32r/m32r-protos.h
@@ -19,7 +19,7 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 /* Function prototypes that cannot exist in v850.h due to dependency
-   compilcations.  */
+   complications.  */
 #define Mmode enum machine_mode
 
 extern void   sbss_section			PARAMS ((void));
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index c788f10dffb..09371c47a16 100644
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -66,7 +66,7 @@ Boston, MA 02111-1307, USA.  */
 %{!mbig-endian: -D__MCORELE__}						\
 %{!m210: -D__M340__}							\
 "
-/* If -m4align is ever re-enabled then add this line to the defintion of CPP_SPEC
+/* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
    %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */
 
 /* We don't have a -lg library, so don't put it in the list.  */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 14f38a166c8..5ccc0aac614 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -700,7 +700,7 @@ extern int rs6000_altivec_abi;
 
 #define FIRST_PSEUDO_REGISTER 110
 
-/* This must be included for pre gcc 3.0 glibc compatability.  */
+/* This must be included for pre gcc 3.0 glibc compatibility.  */
 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
 
 /* 1 for registers that have pervasive standard uses
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 23ab209c25f..ea0edac4929 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -57,7 +57,7 @@
   (const_string "integer"))
 
 ;; Insn are devide in two classes:
-;;   mem: Insn accesssing memory
+;;   mem: Insn accessing memory
 ;;   reg: Insn operands all in registers
 
 (define_attr "atype" "reg,mem"
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
index 62f0c742160..b82b31fcdd7 100644
--- a/gcc/config/sparc/linux64.h
+++ b/gcc/config/sparc/linux64.h
@@ -362,7 +362,7 @@ do {									\
 /* DWARF bits.  */
 
 /* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets. 
-   Obviously the Dwarf2 folks havn't tried to actually build systems
+   Obviously the Dwarf2 folks haven't tried to actually build systems
    with their spec.  On a 64-bit system, only 64-bit relocs become
    RELATIVE relocations.  */
 
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index dec8b8c9389..2807add2849 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2868,7 +2868,7 @@ load_pic_register ()
   if (! flag_pic)
     abort ();
 
-  /* If we havn't emitted the special get_pc helper function, do so now.  */
+  /* If we haven't emitted the special get_pc helper function, do so now.  */
   if (get_pc_symbol_name[0] == 0)
     {
       int align;
diff --git a/gcc/config/v850/v850-protos.h b/gcc/config/v850/v850-protos.h
index 83622d4932d..a6fb8b92694 100644
--- a/gcc/config/v850/v850-protos.h
+++ b/gcc/config/v850/v850-protos.h
@@ -19,7 +19,7 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 /* Function prototypes that cannot exist in v850.h due to dependency
-   compilcations.  */
+   complications.  */
 #ifndef GCC_V850_PROTOS_H
 #define GCC_V850_PROTOS_H
 
diff --git a/gcc/expmed.c b/gcc/expmed.c
index cb21cf5d277..8a7b6b91d55 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -3915,8 +3915,8 @@ expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
       if (rem_flag)
 	{
 	  /* Try to produce the remainder without producing the quotient.
-	     If we seem to have a divmod patten that does not require widening,
-	     don't try windening here.  We should really have an WIDEN argument
+	     If we seem to have a divmod pattern that does not require widening,
+	     don't try widening here.  We should really have an WIDEN argument
 	     to expand_twoval_binop, since what we'd really like to do here is
 	     1) try a mod insn in compute_mode
 	     2) try a divmod insn in compute_mode
diff --git a/gcc/expr.c b/gcc/expr.c
index 26ee720ac42..051dc20a71b 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -1924,7 +1924,7 @@ move_block_from_reg (regno, x, nregs, size)
 /* Emit code to move a block SRC to a block DST, where DST is non-consecutive
    registers represented by a PARALLEL.  SSIZE represents the total size of
    block SRC in bytes, or -1 if not known.  */
-/* ??? If SSIZE % UNITS_PER_WORD != 0, we make the blatent assumption that
+/* ??? If SSIZE % UNITS_PER_WORD != 0, we make the blatant assumption that
    the balance will be in what would be the low-order memory addresses, i.e.
    left justified for big endian, right justified for little endian.  This
    happens to be true for the targets currently using this support.  If this
diff --git a/gcc/final.c b/gcc/final.c
index fcaaf374f35..1653138ff9e 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -475,7 +475,7 @@ int insn_current_address;
 /* Address of insn being processed in previous iteration.  */
 int insn_last_address;
 
-/* konwn invariant alignment of insn being processed.  */
+/* known invariant alignment of insn being processed.  */
 int insn_current_align;
 
 /* After shorten_branches, for any insn, uid_align[INSN_UID (insn)]
@@ -717,7 +717,7 @@ label_to_alignment (label)
    For casesi tables, we also want to know worst case minimum amounts of
    address difference, in case a machine description wants to introduce
    some common offset that is added to all offsets in a table.
-   For this purpose, align_fuzz with a growth argument of 0 comuptes the
+   For this purpose, align_fuzz with a growth argument of 0 computes the
    appropriate adjustment.  */
 
 /* Compute the maximum delta by which the difference of the addresses of
@@ -851,7 +851,7 @@ compute_alignments ()
 
       /* There are two purposes to align block with no fallthru incoming edge:
 	 1) to avoid fetch stalls when branch destination is near cache boundary
-	 2) to improve cache effciency in case the previous block is not executed
+	 2) to improve cache efficiency in case the previous block is not executed
 	    (so it does not need to be in the cache).
 
 	 We to catch first case, we align frequently executed blocks.
@@ -903,7 +903,7 @@ compute_alignments ()
    port splits out-of-range conditional branches in MACHINE_DEPENDENT_REORG.
    In order to do this, it needs proper length information, which it obtains
    by calling shorten_branches.  This cannot be collapsed with
-   shorten_branches itself into a single pass unless we also want to intergate
+   shorten_branches itself into a single pass unless we also want to integrate
    reorg.c, since the branch splitting exposes new instructions with delay
    slots.  */
 
diff --git a/gcc/flow.c b/gcc/flow.c
index 2e0f6ecdc15..69147f34090 100644
--- a/gcc/flow.c
+++ b/gcc/flow.c
@@ -1035,7 +1035,7 @@ calculate_global_regs_live (blocks_in, blocks_out, flags)
   new_live_at_end = INITIALIZE_REG_SET (new_live_at_end_head);
   call_used = INITIALIZE_REG_SET (call_used_head);
 
-  /* Inconveniently, this is only redily available in hard reg set form.  */
+  /* Inconveniently, this is only readily available in hard reg set form.  */
   for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
     if (call_used_regs[i])
       SET_REGNO_REG_SET (call_used, i);
@@ -1374,7 +1374,7 @@ initialize_uninitialized_subregs ()
 	     Its preferable to have an instance of the register's rtl since
 	     there may be various flags set which we need to duplicate.  
 	     If we can't find it, its probably an automatic whose initial
-	     value doesnt matter, or hopefully something we dont care about. */
+	     value doesn't matter, or hopefully something we don't care about. */
 	  for (i = get_insns (); i && INSN_UID (i) != uid; i = NEXT_INSN (i))
 	    ;
 	  if (i != NULL_RTX)
@@ -2797,7 +2797,7 @@ mark_regno_cond_dead (pbi, regno, cond)
 
 	  SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
 
-	  /* Not unconditionaly dead.  */
+	  /* Not unconditionally dead.  */
 	  return 0;
 	}
       else
@@ -2829,7 +2829,7 @@ mark_regno_cond_dead (pbi, regno, cond)
 
 	      SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
 
-	      /* Not unconditionaly dead.  */
+	      /* Not unconditionally dead.  */
 	      return 0;
 	    }
 	}
diff --git a/gcc/fold-const.c b/gcc/fold-const.c
index 2083c55abfa..edf934db9bc 100644
--- a/gcc/fold-const.c
+++ b/gcc/fold-const.c
@@ -2087,7 +2087,7 @@ struct fc_args
 {
   tree arg1;			/* Input: value to convert.  */
   tree type;			/* Input: type to convert value to.  */
-  tree t;			/* Ouput: result of conversion.  */
+  tree t;			/* Output: result of conversion.  */
 };
 
 /* Function to convert floating-point constants, protected by floating
@@ -4834,7 +4834,7 @@ fold_binary_op_with_conditional_arg (code, type, cond, arg, cond_first_p)
      side of the expression to be executed if the condition is true
      will be pointed to by TRUE_LHS.  Similarly, the right-hand side
      of the expression to be executed if the condition is true will be
-     pointed to by TRUE_RHS.  FALSE_LHS and FALSE_RHS are analagous --
+     pointed to by TRUE_RHS.  FALSE_LHS and FALSE_RHS are analogous --
      but apply to the expression to be executed if the conditional is
      false.  */
   tree *true_lhs;
diff --git a/gcc/function.c b/gcc/function.c
index dbd76c0121c..d0e5fd39e17 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -887,7 +887,7 @@ combine_temp_slots ()
     return;
 
   /* If there are a lot of temp slots, don't do anything unless
-     high levels of optimizaton.  */
+     high levels of optimization.  */
   if (! flag_expensive_optimizations)
     for (p = temp_slots, num_slots = 0; p; p = p->next, num_slots++)
       if (num_slots > 100 || (num_slots > 10 && optimize == 0))
@@ -3068,7 +3068,7 @@ purge_addressof_1 (loc, insn, force, store, ht)
 		 example when the original insn was a MEM in a wider mode,
 		 and the note is part of a sign extension of a narrowed
 		 version of that MEM.  Gcc testcase compile/990829-1.c can
-		 generate an example of this siutation.  Rather than complain
+		 generate an example of this situation.  Rather than complain
 		 we return false, which will prompt our caller to remove the
 		 offending note.  */
 	      return false;
@@ -3245,7 +3245,7 @@ struct insns_for_mem_walk_info
      MEMs.  */
   struct hash_table *ht;
 
-  /* The INSN we are currently proessing.  */
+  /* The INSN we are currently processing.  */
   rtx insn;
 
   /* Zero if we are walking to find ADDRESSOFs, one if we are walking
@@ -3396,7 +3396,7 @@ purge_addressof (insns)
   unshare_all_rtl_again (get_insns ());
 }
 
-/* Convert a SET of a hard subreg to a set of the appropriet hard
+/* Convert a SET of a hard subreg to a set of the appropriate hard
    register.  A subroutine of purge_hard_subreg_sets.  */
 
 static void
@@ -3644,7 +3644,7 @@ instantiate_decl (x, size, valid_only)
 }
 
 /* Given a piece of RTX and a pointer to a HOST_WIDE_INT, if the RTX
-   is a virtual register, return the requivalent hard register and set the
+   is a virtual register, return the equivalent hard register and set the
    offset indirectly through the pointer.  Otherwise, return 0.  */
 
 static rtx
@@ -4927,7 +4927,7 @@ assign_parms (fndecl)
 	    {
 	      /* If we end up putting something into the stack,
 		 fixup_var_refs_insns will need to make a pass over
-		 all the instructions.  It looks throughs the pending
+		 all the instructions.  It looks through the pending
 		 sequences -- but it can't see the ones in the
 		 CONVERSION_INSNS, if they're not on the sequence
 		 stack.  So, we go back to that sequence, just so that
@@ -7095,7 +7095,7 @@ emit_return_into_block (bb, line_note)
 
 /* These functions convert the epilogue into a variant that does not modify the
    stack pointer.  This is used in cases where a function returns an object
-   whose size is not known until it is computed.  The called function leavs the
+   whose size is not known until it is computed.  The called function leaves the
    object on the stack, leaves the stack depressed, and returns a pointer to
    the object.
 
@@ -7308,7 +7308,7 @@ keep_stack_depressed (seq)
   return seq;
 }
 
-/* SET is a SET from an insn in the epilogue.  P is a pointr to the epi_info
+/* SET is a SET from an insn in the epilogue.  P is a pointer to the epi_info
    structure that contains information about what we've seen so far.  We
    process this SET by either updating that data or by emitting one or 
    more insns.  */
@@ -7428,7 +7428,7 @@ thread_prologue_and_epilogue_insns (f)
       seq = gen_sequence ();
       end_sequence ();
 
-      /* Can't deal with multiple successsors of the entry block
+      /* Can't deal with multiple successors of the entry block
          at the moment.  Function should always have at least one
          entry point.  */
       if (!ENTRY_BLOCK_PTR->succ || ENTRY_BLOCK_PTR->succ->succ_next)