diff options
author | David Edelsohn <edelsohn@gnu.org> | 2004-11-06 03:35:49 +0000 |
---|---|---|
committer | David Edelsohn <edelsohn@gnu.org> | 2004-11-06 03:35:49 +0000 |
commit | 798904487ece13b15a19b4ad2a3052e08b157619 (patch) | |
tree | b37337cd6c4c34abe4a31e3be3402724ae1f3347 | |
parent | 3227bc70589b3f02d096ffe229f8f60a4ae086df (diff) |
* config/rs6000/rs6000.md (scc patterns): Replace subfc with subf
when carry not used. Suggested by Torbjorn Granlund.
* config/rs6000/rs6000.c (rs6000_emit_move): Don't force_reg
operand[1] unnecessarily. Suggested by Eric Christopher.
(rs6000_adjust_cost): Increase latency of store to wider load.
(rs6000_rtx_costs): mulli only allows 16-bit constants.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@90159 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/ChangeLog | 10 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.c | 17 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.md | 56 |
3 files changed, 55 insertions, 28 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b8efd0516d1..cdc6831889d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2004-11-05 David Edelsohn <edelsohn@gnu.org> + + * config/rs6000/rs6000.md (scc patterns): Replace subfc with subf + when carry not used. Suggested by Torbjorn Granlund. + + * config/rs6000/rs6000.c (rs6000_emit_move): Don't force_reg + operand[1] unnecessarily. Suggested by Eric Christopher. + (rs6000_adjust_cost): Increase latency of store to wider load. + (rs6000_rtx_costs): mulli only allows 16-bit constants. + 2004-11-05 Stan Shebs <shebs@apple.com> * config/rs6000/rs6000.c (machopic_output_stub): Output diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 51577b281ca..fffdf0ca3fd 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4264,7 +4264,8 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) return; } - if (!no_new_pseudos && GET_CODE (operands[0]) != REG) + if (!no_new_pseudos && GET_CODE (operands[0]) != REG + && !gpc_reg_operand (operands[1], mode)) operands[1] = force_reg (mode, operands[1]); if (mode == SFmode && ! TARGET_POWERPC @@ -15735,6 +15736,17 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) { /* Data dependency; DEP_INSN writes a register that INSN reads some cycles later. */ + + /* Separate a load from a narrower, dependent store. */ + if (rs6000_sched_groups + && GET_CODE (PATTERN (insn)) == SET + && GET_CODE (PATTERN (dep_insn)) == SET + && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM + && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM + && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) + > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) + return cost + 14; + switch (get_attr_type (insn)) { case TYPE_JMPREG: @@ -17831,7 +17843,8 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) return false; case MULT: - if (GET_CODE (XEXP (x, 1)) == CONST_INT) + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) { if (INTVAL (XEXP (x, 1)) >= -256 && INTVAL (XEXP (x, 1)) <= 255) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c9b53256133..37f5883239a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -12623,14 +12623,16 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") - (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) + (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))] "TARGET_32BIT" "@ - {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 - {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -12643,8 +12645,8 @@ (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] "TARGET_32BIT" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 + {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 + {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 # #" [(set_attr "type" "compare") @@ -12678,8 +12680,8 @@ (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_32BIT" "@ - {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 - {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 # #" [(set_attr "type" "compare") @@ -13539,26 +13541,28 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") - (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_short_operand" "I,rI")) - (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r") + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") + (match_operand:SI 2 "reg_or_short_operand" "I,rI,rI")) + (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))] "TARGET_32BIT" "@ {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 - {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" - [(set_attr "length" "8,12")]) + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3" + [(set_attr "length" "8,12,12")]) (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") - (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_short_operand" "I,rI")) - (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r") + (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r") + (match_operand:DI 2 "reg_or_short_operand" "I,rI,rI")) + (match_operand:DI 3 "reg_or_short_operand" "r,r,I")))] "TARGET_64BIT" "@ addic %0,%1,%k2\;addze %0,%3 - subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" - [(set_attr "length" "8,12")]) + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf %0,%0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfic %0,%0,%3" + [(set_attr "length" "8,12,12")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") @@ -13571,7 +13575,7 @@ "TARGET_32BIT" "@ {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 + {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 # #" [(set_attr "type" "compare") @@ -13605,7 +13609,7 @@ "TARGET_64BIT" "@ addic %4,%1,%k2\;addze. %4,%3 - subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 + subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3 # #" [(set_attr "type" "compare") @@ -13640,7 +13644,7 @@ "TARGET_32BIT" "@ {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 - {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 # #" [(set_attr "type" "compare") @@ -13675,7 +13679,7 @@ "TARGET_64BIT" "@ addic %0,%1,%k2\;addze. %0,%3 - subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3 # #" [(set_attr "type" "compare") |