working, but need to backpatch the Power9 mask fixes

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/kelvin-rfc2469@234907 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 54 insertions, 0 deletions

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 436e9eae847..cd90b3655b2 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -393,6 +393,11 @@
 #define vec_vctzh __builtin_vec_vctzh
 #define vec_vctzw __builtin_vec_vctzw
 
+#define vec_adu __builtin_vec_vadu
+#define vec_adub __builtin_vec_vadub
+#define vec_aduh __builtin_vec_vaduh
+#define fec_aduw __builtin_vec_vaduw
+
 /* Non-Vector additions added in ISA 3.0. */
 #define darn __builtin_darn
 #define darn_32 __builtin_darn_32
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 16b7cb82ebe..1e0d26d0a49 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -114,6 +114,7 @@
    UNSPEC_STVLXL
    UNSPEC_STVRX
    UNSPEC_STVRXL
+   UNSPEC_VADU
    UNSPEC_VMULWHUB
    UNSPEC_VMULWLUB
    UNSPEC_VMULWHSB
@@ -3396,6 +3397,26 @@
   [(set_attr "length" "4")
    (set_attr "type" "vecsimple")])
 
+
+;; Vector absolute difference unsigned
+(define_expand "vadu<mode>3"
+  [(set (match_operand:VI 0 "register_operand" "")
+        (unspec:VI [(match_operand:VI 1 "register_operand" "")
+		    (match_operand:VI 2 "register_operand" "")]
+         UNSPEC_VADU))]
+  "TARGET_P9_VECTOR")
+
+;; Vector absolute difference unsigned
+(define_insn "*p9_vadu<mode>3"
+  [(set (match_operand:VI 0 "register_operand" "=v")
+        (unspec:VI [(match_operand:VI 1 "register_operand" "v")
+		    (match_operand:VI 2 "register_operand" "v")]
+         UNSPEC_VADU))]
+  "TARGET_P9_VECTOR"
+  "vabsdu<wd> %0, %1, %2"
+  [(set_attr "type" "add")  
+   (set_attr "length" "4")])
+
 ;; Vector count trailing zeros
 (define_insn "*p9v_ctz<mode>2"
   [(set (match_operand:VI2 0 "register_operand" "=v")
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index ad03251555c..2e78762ac9f 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1773,6 +1773,22 @@ BU_P9V_OVERLOAD_1 (VCTZH,	"vctzh")
 BU_P9V_OVERLOAD_1 (VCTZW,	"vctzw")
 BU_P9V_OVERLOAD_1 (VCTZD,	"vctzd")
 
+/* kelvin enhancements */
+/* 2 argument vector functions added in ISA 3.0 (power9). */
+BU_P9V_AV_2 (VADUB,		"vadub",		CONST,  vaduv16qi3)
+BU_P9V_AV_2 (VADUH,		"vaduh",		CONST,  vaduv8hi3)
+BU_P9V_AV_2 (VADUW,		"vaduw",		CONST,  vaduv4si3)
+
+/* kelvin enhancements: copying pattern of vctz.  do these need to "expand"? */
+/*  kelvin not sure what happens to the "vadu" pattern - it doesn't really
+ *  have an expansion.
+ */
+/* ISA 3.0 vector overloaded 2 argument functions. */
+BU_P9V_OVERLOAD_2 (VADU,	"vadu")
+BU_P9V_OVERLOAD_2 (VADUB,	"vadub")
+BU_P9V_OVERLOAD_2 (VADUH,	"vaduh")
+BU_P9V_OVERLOAD_2 (VADUW,	"vaduw")
+
 
 /* 1 argument crypto functions.  */
 BU_CRYPTO_1 (VSBOX,		"vsbox",	  CONST, crypto_vsbox)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 76b90f4092d..88459592a03 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -4160,6 +4160,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
 
+  { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
+    RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+    RS6000_BTI_unsigned_V16QI, 0 },
+
+  { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
+    RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
+    RS6000_BTI_unsigned_V8HI, 0 },
+
+  { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
+    RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
+    RS6000_BTI_unsigned_V4SI, 0 },
+
   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,