Fix previous commit: forgot to commit all new files.

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@207657 138bc75d-0d04-0410-961f-82ee72b054a4

140 files changed, 3003 insertions, 0 deletions

diff --git a/gcc/config/arm/arm_acle.h b/gcc/config/arm/arm_acle.h
new file mode 100644
index 00000000000..aaa7affeeb7
--- /dev/null
+++ b/gcc/config/arm/arm_acle.h
@@ -0,0 +1,100 @@
+/* ARM Non-NEON ACLE intrinsics include file.
+
+   Copyright (C) 2013-2014 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _GCC_ARM_ACLE_H
+#define _GCC_ARM_ACLE_H
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __ARM_FEATURE_CRC32
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32b (uint32_t __a, uint8_t __b)
+{
+  return __builtin_arm_crc32b (__a, __b);
+}
+
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32h (uint32_t __a, uint16_t __b)
+{
+  return __builtin_arm_crc32h (__a, __b);
+}
+
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32w (uint32_t __a, uint32_t __b)
+{
+  return __builtin_arm_crc32w (__a, __b);
+}
+
+#ifdef __ARM_32BIT_STATE
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32d (uint32_t __a, uint64_t __b)
+{
+  uint32_t __d;
+
+  __d = __crc32w (__crc32w (__a, __b & 0xffffffffULL), __b >> 32);
+  return __d;
+}
+#endif
+
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32cb (uint32_t __a, uint8_t __b)
+{
+  return __builtin_arm_crc32cb (__a, __b);
+}
+
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32ch (uint32_t __a, uint16_t __b)
+{
+  return __builtin_arm_crc32ch (__a, __b);
+}
+
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32cw (uint32_t __a, uint32_t __b)
+{
+  return __builtin_arm_crc32cw (__a, __b);
+}
+
+#ifdef __ARM_32BIT_STATE
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+__crc32cd (uint32_t __a, uint64_t __b)
+{
+  uint32_t __d;
+
+  __d = __crc32cw (__crc32cw (__a, __b & 0xffffffffULL), __b >> 32);
+  return __d;
+}
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/gcc/config/arm/crypto.def b/gcc/config/arm/crypto.def
new file mode 100644
index 00000000000..dc805d9ec64
--- /dev/null
+++ b/gcc/config/arm/crypto.def
@@ -0,0 +1,34 @@
+/* Cryptographic instruction builtin definitions.
+   Copyright (C) 2013-2014 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+CRYPTO2 (aesd, AESD, v16uqi, v16uqi, v16uqi)
+CRYPTO2 (aese, AESE, v16uqi, v16uqi, v16uqi)
+CRYPTO1 (aesimc, AESIMC, v16uqi, v16uqi)
+CRYPTO1 (aesmc, AESMC, v16uqi, v16uqi)
+CRYPTO1 (sha1h, SHA1H, v4usi, v4usi)
+CRYPTO2 (sha1su1, SHA1SU1, v4usi, v4usi, v4usi)
+CRYPTO2 (sha256su0, SHA256SU0, v4usi, v4usi, v4usi)
+CRYPTO3 (sha1c, SHA1C, v4usi, v4usi, v4usi, v4usi)
+CRYPTO3 (sha1m, SHA1M, v4usi, v4usi, v4usi, v4usi)
+CRYPTO3 (sha1p, SHA1P, v4usi, v4usi, v4usi, v4usi)
+CRYPTO3 (sha1su0, SHA1SU0, v4usi, v4usi, v4usi, v4usi)
+CRYPTO3 (sha256h, SHA256H, v4usi, v4usi, v4usi, v4usi)
+CRYPTO3 (sha256h2, SHA256H2, v4usi, v4usi, v4usi, v4usi)
+CRYPTO3 (sha256su1, SHA256SU1, v4usi, v4usi, v4usi, v4usi)
+CRYPTO2 (vmullp64, VMULLP64, uti, udi, udi)
diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md
new file mode 100644
index 00000000000..a77db3f122d
--- /dev/null
+++ b/gcc/config/arm/crypto.md
@@ -0,0 +1,86 @@
+;; ARMv8-A crypto patterns.
+;; Copyright (C) 2013-2014 Free Software Foundation, Inc.
+;; Contributed by ARM Ltd.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_insn "crypto_<crypto_pattern>"
+  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
+        (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1
+                       "register_operand" "w")]
+         CRYPTO_UNARY))]
+  "TARGET_CRYPTO"
+  "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1"
+  [(set_attr "neon_type" "<crypto_type>")]
+)
+
+(define_insn "crypto_<crypto_pattern>"
+  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
+        (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1 "register_operand" "0")
+                      (match_operand:<crypto_mode> 2 "register_operand" "w")]
+         CRYPTO_BINARY))]
+  "TARGET_CRYPTO"
+  "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2"
+  [(set_attr "neon_type" "<crypto_type>")]
+)
+
+(define_insn "crypto_<crypto_pattern>"
+  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
+        (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1 "register_operand" "0")
+                      (match_operand:<crypto_mode> 2 "register_operand" "w")
+                      (match_operand:<crypto_mode> 3 "register_operand" "w")]
+         CRYPTO_TERNARY))]
+  "TARGET_CRYPTO"
+  "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2, %q3"
+  [(set_attr "neon_type" "<crypto_type>")]
+)
+
+(define_insn "crypto_sha1h"
+  [(set (match_operand:V4SI 0 "register_operand" "=w")
+        (zero_extend:V4SI
+          (unspec:SI [(vec_select:SI
+                        (match_operand:V4SI 1 "register_operand" "w")
+                        (parallel [(match_operand:SI 2 "immediate_operand" "i")]))]
+           UNSPEC_SHA1H)))]
+  "TARGET_CRYPTO"
+  "sha1h.32\\t%q0, %q1"
+  [(set_attr "neon_type" "neon_crypto_sha1_fast")]
+)
+
+(define_insn "crypto_vmullp64"
+  [(set (match_operand:TI 0 "register_operand" "=w")
+        (unspec:TI [(match_operand:DI 1 "register_operand" "w")
+                    (match_operand:DI 2 "register_operand" "w")]
+         UNSPEC_VMULLP64))]
+  "TARGET_CRYPTO"
+  "vmull.p64\\t%q0, %P1, %P2"
+  [(set_attr "neon_type" "neon_mul_d_long")]
+)
+
+(define_insn "crypto_<crypto_pattern>"
+  [(set (match_operand:V4SI 0 "register_operand" "=w")
+        (unspec:<crypto_mode>
+                     [(match_operand:<crypto_mode> 1 "register_operand" "0")
+                      (vec_select:SI
+                        (match_operand:<crypto_mode> 2 "register_operand" "w")
+                        (parallel [(match_operand:SI 4 "immediate_operand" "i")]))
+                      (match_operand:<crypto_mode> 3 "register_operand" "w")]
+         CRYPTO_SELECTING))]
+  "TARGET_CRYPTO"
+  "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q2, %q3"
+  [(set_attr "neon_type" "<crypto_type>")]
+)
diff --git a/gcc/doc/arm-acle-intrinsics.texi b/gcc/doc/arm-acle-intrinsics.texi
new file mode 100644
index 00000000000..e68f4cd2017
--- /dev/null
+++ b/gcc/doc/arm-acle-intrinsics.texi
@@ -0,0 +1,55 @@
+@c Copyright (C) 2013-2014 Free Software Foundation, Inc.
+@c This is part of the GCC manual.
+@c For copying conditions, see the file gcc.texi.
+
+@subsubsection CRC32 intrinsics
+
+@itemize @bullet
+@item uint32_t __crc32b (uint32_t, uint8_t)
+@*@emph{Form of expected instruction(s):} @code{crc32b @var{r0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32_t __crc32h (uint32_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{crc32h @var{r0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32_t __crc32w (uint32_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{crc32w @var{r0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32_t __crc32d (uint32_t, uint64_t)
+@*@emph{Form of expected instruction(s):} Two @code{crc32w @var{r0}, @var{r0}, @var{r0}}
+instructions for AArch32. One @code{crc32w @var{w0}, @var{w0}, @var{x0}} instruction for
+AArch64.
+@end itemize
+
+@itemize @bullet
+@item uint32_t __crc32cb (uint32_t, uint8_t)
+@*@emph{Form of expected instruction(s):} @code{crc32cb @var{r0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32_t __crc32ch (uint32_t, uint16_t)
+@*@emph{Form of expected instruction(s):} @code{crc32ch @var{r0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32_t __crc32cw (uint32_t, uint32_t)
+@*@emph{Form of expected instruction(s):} @code{crc32cw @var{r0}, @var{r0}, @var{r0}}
+@end itemize
+
+
+@itemize @bullet
+@item uint32_t __crc32cd (uint32_t, uint64_t)
+@*@emph{Form of expected instruction(s):} Two @code{crc32cw @var{r0}, @var{r0}, @var{r0}}
+instructions for AArch32. One @code{crc32cw @var{w0}, @var{w0}, @var{x0}} instruction for
+AArch64.
+@end itemize
diff --git a/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc/testsuite/gcc.target/aarch64/aes_1.c
new file mode 100644
index 00000000000..5fa61379ea6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/aes_1.c
@@ -0,0 +1,40 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint8x16_t
+test_vaeseq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return vaeseq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesdq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return vaesdq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aesd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesmcq_u8 (uint8x16_t data)
+{
+  return vaesmcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesmc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesimcq_u8 (uint8x16_t data)
+{
+  return vaesimcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesimc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/pmull_1.c b/gcc/testsuite/gcc.target/aarch64/pmull_1.c
new file mode 100644
index 00000000000..bccaec1750e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pmull_1.c
@@ -0,0 +1,23 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+poly128_t
+test_vmull_p64 (poly64_t a, poly64_t b)
+{
+  return vmull_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pmull\\tv" 1 } } */
+
+poly128_t
+test_vmull_high_p64 (poly64x2_t a, poly64x2_t b)
+{
+  return vmull_high_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pmull2\\tv" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha1_1.c b/gcc/testsuite/gcc.target/aarch64/sha1_1.c
new file mode 100644
index 00000000000..776753dcd5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha1_1.c
@@ -0,0 +1,55 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint32x4_t
+test_vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+  return vsha1cq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1c\\tq" 1 } } */
+
+uint32x4_t
+test_vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+  return vsha1mq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1m\\tq" 1 } } */
+
+uint32x4_t
+test_vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+  return vsha1pq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1p\\tq" 1 } } */
+
+uint32_t
+test_vsha1h_u32 (uint32_t hash_e)
+{
+  return vsha1h_u32 (hash_e);
+}
+
+/* { dg-final { scan-assembler-times "sha1h\\ts" 1 } } */
+
+uint32x4_t
+test_vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
+{
+  return vsha1su0q_u32 (w0_3, w4_7, w8_11);
+}
+
+/* { dg-final { scan-assembler-times "sha1su0\\tv" 1 } } */
+
+uint32x4_t
+test_vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
+{
+  return vsha1su1q_u32 (tw0_3, w12_15);
+}
+
+/* { dg-final { scan-assembler-times "sha1su1\\tv" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc/testsuite/gcc.target/aarch64/sha256_1.c
new file mode 100644
index 00000000000..569817eb083
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sha256_1.c
@@ -0,0 +1,40 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint32x4_t
+test_vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
+{
+  return vsha256hq_u32 (hash_abcd, hash_efgh, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha256h\\tq" 1 } } */
+
+uint32x4_t
+test_vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
+{
+  return vsha256h2q_u32 (hash_efgh, hash_abcd, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha256h2\\tq" 1 } } */
+
+uint32x4_t
+test_vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
+{
+  return vsha256su0q_u32 (w0_3, w4_7);
+}
+
+/* { dg-final { scan-assembler-times "sha256su0\\tv" 1 } } */
+
+uint32x4_t
+test_vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
+{
+  return vsha256su1q_u32 (tw0_3, w8_11, w12_15);
+}
+
+/* { dg-final { scan-assembler-times "sha256su1\\tv" 1 } } */
+
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/acle.exp b/gcc/testsuite/gcc.target/arm/acle/acle.exp
new file mode 100644
index 00000000000..c8622697ee3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/acle.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 2013-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32b.c b/gcc/testsuite/gcc.target/arm/acle/crc32b.c
new file mode 100644
index 00000000000..d6f35e9fd8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32b.c
@@ -0,0 +1,20 @@
+/* Test the crc32b ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32b (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint8_t arg1_uint8_t;
+
+  out_uint32_t = __crc32b (arg0_uint32_t, arg1_uint8_t);
+}
+
+/* { dg-final { scan-assembler "crc32b\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32cb.c b/gcc/testsuite/gcc.target/arm/acle/crc32cb.c
new file mode 100644
index 00000000000..44aea21fcf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32cb.c
@@ -0,0 +1,20 @@
+/* Test the crc32cb ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32cb (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint8_t arg1_uint8_t;
+
+  out_uint32_t = __crc32cb (arg0_uint32_t, arg1_uint8_t);
+}
+
+/* { dg-final { scan-assembler "crc32cb\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32cd.c b/gcc/testsuite/gcc.target/arm/acle/crc32cd.c
new file mode 100644
index 00000000000..cb7ee0df0a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32cd.c
@@ -0,0 +1,20 @@
+/* Test the crc32cd ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32cd (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint64_t arg1_uint64_t;
+
+  out_uint32_t = __crc32cd (arg0_uint32_t, arg1_uint64_t);
+}
+
+/* { dg-final { scan-assembler-times "crc32cw\t...?, ...?, ...?\n" 2 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32ch.c b/gcc/testsuite/gcc.target/arm/acle/crc32ch.c
new file mode 100644
index 00000000000..d8e73389433
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32ch.c
@@ -0,0 +1,20 @@
+/* Test the crc32ch ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32ch (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32_t = __crc32ch (arg0_uint32_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "crc32ch\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32cw.c b/gcc/testsuite/gcc.target/arm/acle/crc32cw.c
new file mode 100644
index 00000000000..84384c5d540
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32cw.c
@@ -0,0 +1,20 @@
+/* Test the crc32cw ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32cw (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32_t = __crc32cw (arg0_uint32_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "crc32cw\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32d.c b/gcc/testsuite/gcc.target/arm/acle/crc32d.c
new file mode 100644
index 00000000000..c90fad9a7a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32d.c
@@ -0,0 +1,20 @@
+/* Test the crc32d ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32d (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint64_t arg1_uint64_t;
+
+  out_uint32_t = __crc32d (arg0_uint32_t, arg1_uint64_t);
+}
+
+/* { dg-final { scan-assembler-times "crc32w\t...?, ...?, ...?\n" 2 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32h.c b/gcc/testsuite/gcc.target/arm/acle/crc32h.c
new file mode 100644
index 00000000000..c21a4ae3e31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32h.c
@@ -0,0 +1,20 @@
+/* Test the crc32h ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32h (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32_t = __crc32h (arg0_uint32_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "crc32h\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/acle/crc32w.c b/gcc/testsuite/gcc.target/arm/acle/crc32w.c
new file mode 100644
index 00000000000..60cd09e4be5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/acle/crc32w.c
@@ -0,0 +1,20 @@
+/* Test the crc32w ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32w (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32_t = __crc32w (arg0_uint32_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "crc32w\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c
new file mode 100644
index 00000000000..e0b25b93cf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b, c;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = i;
+      b[i] = 15 - i;
+    }
+  c = vaesdq_u8 (a, b);
+  return c[0];
+}
+
+/* { dg-final { scan-assembler "aesd.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c
new file mode 100644
index 00000000000..f47864662eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b, c;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = i;
+      b[i] = 15 - i;
+    }
+  c = vaeseq_u8 (a, b);
+  return c[0];
+}
+
+/* { dg-final { scan-assembler "aese.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c
new file mode 100644
index 00000000000..fbbfda609fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    a[i] = i;
+
+  b = vaesimcq_u8 (a);
+  return b[0];
+}
+
+/* { dg-final { scan-assembler "aesimc.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c b/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c
new file mode 100644
index 00000000000..cae8bd096b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    a[i] = i;
+
+  b = vaesmcq_u8 (a);
+  return b[0];
+}
+
+/* { dg-final { scan-assembler "aesmc.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c b/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c
new file mode 100644
index 00000000000..96c0e9a755a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (poly128_t* ptr)
+{
+  return vldrq_p128 (ptr);
+}
+
+/* { dg-final { scan-assembler "vld1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c b/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c
new file mode 100644
index 00000000000..1290f31a6a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (void)
+{
+  poly64x2_t a = { 0xdeadbeef, 0xadabcaca };
+  poly64x2_t b = { 0xdcdcdcdc, 0xbdbdbdbd };
+  return vmull_high_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmull.p64.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c b/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c
new file mode 100644
index 00000000000..b788dca52ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (void)
+{
+  poly64_t a = 0xdeadbeef;
+  poly64_t b = 0xadadadad;
+  return vmull_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmull.p64.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
new file mode 100644
index 00000000000..4dc9dee6617
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1cq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1c.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
new file mode 100644
index 00000000000..dee27748524
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t val = 0xdeadbeef;
+  return vsha1h_u32 (val);
+}
+
+/* { dg-final { scan-assembler "sha1h.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
new file mode 100644
index 00000000000..672b93a9747
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1mq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1m.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
new file mode 100644
index 00000000000..ff508e0dc7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1pq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1p.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c
new file mode 100644
index 00000000000..4435d1800b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1su0q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1su0.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c
new file mode 100644
index 00000000000..8610c4de269
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+
+  uint32x4_t res = vsha1su1q_u32 (a, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1su1.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c
new file mode 100644
index 00000000000..4a3e2e15835
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256h2q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256h2.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c
new file mode 100644
index 00000000000..49577f2b724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256hq_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256h.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c
new file mode 100644
index 00000000000..cc4305d38b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+
+  uint32x4_t res = vsha256su0q_u32 (a, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256su0.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c
new file mode 100644
index 00000000000..430f38adc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256su1q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256su1.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c b/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c
new file mode 100644
index 00000000000..acd8af34f66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void
+foo (poly128_t* ptr, poly128_t val)
+{
+  vstrq_p128 (ptr, val);
+}
+
+/* { dg-final { scan-assembler "vst1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c b/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c
new file mode 100644
index 00000000000..21a6a78a221
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+  uint64_t args[] = { 0x0, 0xdeadbeef, ~0xdeadbeef, 0xffff,
+                      ~0xffff, 0xffffffff, ~0xffffffff, ~0x0 };
+  int i, j;
+
+  for (i = 0; i < sizeof (args) / sizeof (args[0]); ++i)
+    {
+       for (j = 0; j < sizeof (args) / sizeof (args[0]); ++j)
+         {
+           uint64_t a1 = args[i];
+           uint64_t a2 = args[j];
+           uint64_t res = vceq_p64 (vreinterpret_p64_u64 (a1),
+                                    vreinterpret_p64_u64 (a2));
+           uint64_t exp = (a1 == a2) ? ~0x0 : 0x0;
+
+           if (res != exp)
+             {
+               fprintf (stderr, "vceq_p64 (a1= %lx, a2= %lx)"
+                                " returned %lx, expected %lx\n",
+                                 a1, a2, res, exp);
+               abort ();
+             }
+         }
+    }
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c b/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c
new file mode 100644
index 00000000000..3a0b117c261
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+  uint64_t args[] = { 0x0, 0xdeadbeef, ~0xdeadbeef, 0xffff,
+                      ~0xffff, 0xffffffff, ~0xffffffff, ~0x0 };
+  int i, j;
+
+  for (i = 0; i < sizeof (args) / sizeof (args[0]); ++i)
+    {
+       for (j = 0; j < sizeof (args) / sizeof (args[0]); ++j)
+         {
+           uint64_t a1 = args[i];
+           uint64_t a2 = args[j];
+           uint64_t res = vtst_p64 (vreinterpret_p64_u64 (a1),
+                                    vreinterpret_p64_u64 (a2));
+           uint64_t exp = (a1 & a2) ? ~0x0 : 0x0;
+
+           if (res != exp)
+             {
+               fprintf (stderr, "vtst_p64 (a1= %lx, a2= %lx)"
+                                " returned %lx, expected %lx\n",
+                                 a1, a2, res, exp);
+               abort ();
+             }
+         }
+    }
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
new file mode 100644
index 00000000000..519ee370d1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+  poly64x2_t arg2_poly64x2_t;
+
+  out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp64.c b/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
new file mode 100644
index 00000000000..51929274dbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+  poly64x1_t arg2_poly64x1_t;
+
+  out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
new file mode 100644
index 00000000000..d5e156bdf34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
@@ -0,0 +1,20 @@
+/* Test the `vcombinep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcombinep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
new file mode 100644
index 00000000000..7aedb73fcc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
@@ -0,0 +1,19 @@
+/* Test the `vcreatep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcreatep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly64x1_t = vcreate_p64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
new file mode 100644
index 00000000000..6211413c76c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
new file mode 100644
index 00000000000..68a1d746bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
new file mode 100644
index 00000000000..ab263f17080
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
new file mode 100644
index 00000000000..3b6b7ec312c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x1_t = vdup_n_p64 (arg0_poly64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp64.c b/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
new file mode 100644
index 00000000000..bc5e08aa783
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
@@ -0,0 +1,21 @@
+/* Test the `vextQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp64.c b/gcc/testsuite/gcc.target/arm/neon/vextp64.c
new file mode 100644
index 00000000000..aa1e91f59bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextp64.c
@@ -0,0 +1,21 @@
+/* Test the `vextp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
new file mode 100644
index 00000000000..f2b1b7a9e38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_highp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
new file mode 100644
index 00000000000..94cd3a8ab75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
new file mode 100644
index 00000000000..2d504c163ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
new file mode 100644
index 00000000000..d19267a4ff8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
new file mode 100644
index 00000000000..99ef8767321
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
new file mode 100644
index 00000000000..f2b05c5d1e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
new file mode 100644
index 00000000000..cf09f6cd641
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p64.c b/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
new file mode 100644
index 00000000000..9f182d4419f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1p64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
new file mode 100644
index 00000000000..0531a732dea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p64.c b/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
new file mode 100644
index 00000000000..0a39b37f01a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2p64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
new file mode 100644
index 00000000000..23bf88aa6d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p64.c b/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
new file mode 100644
index 00000000000..cc799289246
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3p64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
new file mode 100644
index 00000000000..bb15964af0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p64.c b/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
new file mode 100644
index 00000000000..b11fb938432
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4p64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
new file mode 100644
index 00000000000..91cac4df5c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p128 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
new file mode 100644
index 00000000000..96909f677d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p64 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
new file mode 100644
index 00000000000..aa7d2e7e7de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_f32 (void)
+{
+  poly128_t out_poly128_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
new file mode 100644
index 00000000000..94f2e9b4afa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p16 (void)
+{
+  poly128_t out_poly128_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
new file mode 100644
index 00000000000..d32007547e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p64 (void)
+{
+  poly128_t out_poly128_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
new file mode 100644
index 00000000000..112b0c6e3cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p8 (void)
+{
+  poly128_t out_poly128_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
new file mode 100644
index 00000000000..4fa06b2382b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s16 (void)
+{
+  poly128_t out_poly128_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
new file mode 100644
index 00000000000..5f17cb81309
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s32 (void)
+{
+  poly128_t out_poly128_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
new file mode 100644
index 00000000000..9b83912b979
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s64 (void)
+{
+  poly128_t out_poly128_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
new file mode 100644
index 00000000000..49e8b74b45a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s8 (void)
+{
+  poly128_t out_poly128_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
new file mode 100644
index 00000000000..d47429aeb5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u16 (void)
+{
+  poly128_t out_poly128_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
new file mode 100644
index 00000000000..57abf79a92e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u32 (void)
+{
+  poly128_t out_poly128_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
new file mode 100644
index 00000000000..4d04daaaa11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u64 (void)
+{
+  poly128_t out_poly128_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
new file mode 100644
index 00000000000..ba07bbc8ac3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u8 (void)
+{
+  poly128_t out_poly128_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
new file mode 100644
index 00000000000..27d0d0afb51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p128 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
new file mode 100644
index 00000000000..a0a3aaff49e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
new file mode 100644
index 00000000000..9f9b1a4ea1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_f32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
new file mode 100644
index 00000000000..3f712951359
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p128 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
new file mode 100644
index 00000000000..897b7cd9d00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
new file mode 100644
index 00000000000..772b268bf8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
new file mode 100644
index 00000000000..29f3f6c1cdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
new file mode 100644
index 00000000000..fae22f65ef2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
new file mode 100644
index 00000000000..8769bc8e6b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
new file mode 100644
index 00000000000..1163cc2b7c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
new file mode 100644
index 00000000000..f2b53260e03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
new file mode 100644
index 00000000000..6b6179ba41f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
new file mode 100644
index 00000000000..655ffd4fafb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
new file mode 100644
index 00000000000..40b40dd11dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
new file mode 100644
index 00000000000..b517a6fdfa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p128 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
new file mode 100644
index 00000000000..9e70b8a0756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
new file mode 100644
index 00000000000..77bfe3882ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p128 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
new file mode 100644
index 00000000000..41890f32aad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p64 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
new file mode 100644
index 00000000000..9a179ae3beb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p128 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
new file mode 100644
index 00000000000..cc7ad95ea9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p64 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
new file mode 100644
index 00000000000..adc1b9bbf0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p128 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
new file mode 100644
index 00000000000..89ab9ccb4b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p64 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
new file mode 100644
index 00000000000..d94090068e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p128 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
new file mode 100644
index 00000000000..a9adec38704
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p64 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
new file mode 100644
index 00000000000..792609246c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p128 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
new file mode 100644
index 00000000000..7a9b538f232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
new file mode 100644
index 00000000000..ce716b0ab1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p128 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
new file mode 100644
index 00000000000..a8b709e0298
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
new file mode 100644
index 00000000000..789973e0a27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p128 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
new file mode 100644
index 00000000000..38071503eaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
new file mode 100644
index 00000000000..54a832cf41c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p128 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
new file mode 100644
index 00000000000..3336e6c24e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
new file mode 100644
index 00000000000..e9714658fc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p64 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
new file mode 100644
index 00000000000..4cd6818db83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
new file mode 100644
index 00000000000..d9ecd6f88c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_f32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
new file mode 100644
index 00000000000..db437279b5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
new file mode 100644
index 00000000000..1fb0131d8d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
new file mode 100644
index 00000000000..528db2d57fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
new file mode 100644
index 00000000000..c6887d7e089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
new file mode 100644
index 00000000000..f2b04164903
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
new file mode 100644
index 00000000000..1866d19fb69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
new file mode 100644
index 00000000000..7903ec26f38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
new file mode 100644
index 00000000000..3d8e9e40f3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
new file mode 100644
index 00000000000..caa0464aac1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
new file mode 100644
index 00000000000..47e1dfa5f4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
new file mode 100644
index 00000000000..f5eff21abb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
new file mode 100644
index 00000000000..127865d169b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p64 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
new file mode 100644
index 00000000000..f8be30b9246
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p64 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
new file mode 100644
index 00000000000..5f7c17bd33e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p64 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
new file mode 100644
index 00000000000..8345963ef3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p64 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
new file mode 100644
index 00000000000..34f920bbd7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
new file mode 100644
index 00000000000..b5f24fbc4b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
new file mode 100644
index 00000000000..741912a4ebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
new file mode 100644
index 00000000000..907b67c157d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
new file mode 100644
index 00000000000..cbb47285e46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
new file mode 100644
index 00000000000..801add49be1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsli_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
new file mode 100644
index 00000000000..d2e48165aa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
new file mode 100644
index 00000000000..0abffc2e0e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsri_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
new file mode 100644
index 00000000000..74a198baf81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
new file mode 100644
index 00000000000..7d1e020f111
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
new file mode 100644
index 00000000000..f8c70c35952
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p64.c b/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
new file mode 100644
index 00000000000..7329fba9d0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_p64 (arg0_poly64_t, arg1_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p64.c b/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
new file mode 100644
index 00000000000..3ccaa5464f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst2p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x2_t arg1_poly64x1x2_t;
+
+  vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p64.c b/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
new file mode 100644
index 00000000000..73ced95448f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst3p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x3_t arg1_poly64x1x3_t;
+
+  vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p64.c b/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
new file mode 100644
index 00000000000..b9f7b168d2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst4p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x4_t arg1_poly64x1x4_t;
+
+  vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */