diff options
| author | Tamar Christina <tamar.christina@arm.com> | 2017-10-05 15:17:39 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2017-10-05 15:17:39 +0000 |
| commit | a4fad638de0afc609133971f0d5cdbfc248d62b1 (patch) | |
| tree | 6d9f349b4ed51457480f7641b70972032810c6ae /gcc | |
| parent | 72eeaa623bf8bfa6cc390074364ca6786c722b14 (diff) | |
gcc/testsuite/
2017-10-05 Tamar Christina <tamar.christina@arm.com>
* gcc.dg/vect/slp-perm-9.c: Use vect_sizes_16B_8B.
* lib/target-supports.exp (vect_sizes_16B_8B): New.
gcc/
2017-10-05 Tamar Christina <tamar.christina@arm.com>
* doc/sourcebuild.texi (vect_sizes_16B_8B, vect_sizes_32B_16B): New.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@253452 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/slp-perm-9.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 13 |
5 files changed, 31 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 43bb1473551..777340cdce7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-10-05 Tamar Christina <tamar.christina@arm.com> + + * doc/sourcebuild.texi (vect_sizes_16B_8B, vect_sizes_32B_16B): New. + 2017-10-05 Jan Hubicka <hubicka@ucw.cz> * i386.c (znver1_cost): Set branch_cost to 3 (instead of 2) diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 1646d0a9991..a2f04291194 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1519,6 +1519,12 @@ Target supports conversion from @code{double} to @code{signed int}. @item vect_max_reduc Target supports max reduction for vectors. + +@item vect_sizes_16B_8B +Target supports 16- and 8-bytes vectors. + +@item vect_sizes_32B_16B +Target supports 32- and 16-bytes vectors. @end table @subsubsection Thread Local Storage attributes diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index bfb82c075e2..5b7919fc956 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,9 @@ -2017-09-28 Tamar Christina <tamar.christina@arm.com> +2017-10-05 Tamar Christina <tamar.christina@arm.com> + + * gcc.dg/vect/slp-perm-9.c: Use vect_sizes_16B_8B. + * lib/target-supports.exp (vect_sizes_16B_8B): New. + +2017-10-05 Tamar Christina <tamar.christina@arm.com> * gcc.dg/vect/vect-align-1.c: Fix vect_hw_misalign condition. * gcc.dg/vect/vect-align-2.c: Likewise. diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c index 4d9c11dcc47..b9b5a3b87ad 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c +++ b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c @@ -54,8 +54,8 @@ int main (int argc, const char* argv[]) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_16B_8B } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_16B_8B } } } } } */ /* { dg-final { scan-tree-dump-times "permutation requires at least three vectors" 1 "vect" { target vect_perm_short } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index b6f9e51c481..fbe8f2a76af 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7671,6 +7671,19 @@ proc check_effective_target_vect_sizes_32B_16B { } { } } +# Return true if 16- and 8-bytes vectors are available. + +proc check_effective_target_vect_sizes_16B_8B { } { + if { [check_avx_available] + || [is-effective-target arm_neon] + || [istarget aarch64*-*-*] } { + return 1; + } else { + return 0; + } +} + + # Return true if 128-bits vectors are preferred even if 256-bits vectors # are available. |