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-rw-r--r--gcc/config/aarch64/aarch64-elf.h1
-rw-r--r--gcc/config/aarch64/aarch64-simd.md36
-rw-r--r--gcc/config/aarch64/aarch64.c24
-rw-r--r--gcc/config/aarch64/aarch64.md96
-rw-r--r--gcc/config/aarch64/t-aarch64-linux2
5 files changed, 143 insertions, 16 deletions
diff --git a/gcc/config/aarch64/aarch64-elf.h b/gcc/config/aarch64/aarch64-elf.h
index db08031b178..3f3ae526a2a 100644
--- a/gcc/config/aarch64/aarch64-elf.h
+++ b/gcc/config/aarch64/aarch64-elf.h
@@ -106,7 +106,6 @@
#define ASM_COMMENT_START "//"
-#define REGISTER_PREFIX ""
#define LOCAL_LABEL_PREFIX "."
#define USER_LABEL_PREFIX ""
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 0f0009505d8..92dcfc0c57b 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -44,6 +44,7 @@
; simd_dup duplicate element.
; simd_dupgp duplicate general purpose register.
; simd_ext bitwise extract from pair.
+; simd_fabd floating absolute difference and accumulate.
; simd_fadd floating point add/sub.
; simd_fcmp floating point compare.
; simd_fcvti floating point convert to integer.
@@ -147,6 +148,7 @@
simd_dup,\
simd_dupgp,\
simd_ext,\
+ simd_fabd,\
simd_fadd,\
simd_fcmp,\
simd_fcvti,\
@@ -520,6 +522,40 @@
(set_attr "simd_mode" "<MODE>")]
)
+(define_insn "abd<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "sabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "aba<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))
+ (match_operand:VDQ_BHSI 3 "register_operand" "0")))]
+ "TARGET_SIMD"
+ "saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "fabd<mode>_3"
+ [(set (match_operand:VDQF 0 "register_operand" "=w")
+ (abs:VDQF (minus:VDQF
+ (match_operand:VDQF 1 "register_operand" "w")
+ (match_operand:VDQF 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_fabd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
(define_insn "and<mode>3"
[(set (match_operand:VDQ 0 "register_operand" "=w")
(and:VDQ (match_operand:VDQ 1 "register_operand" "w")
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 8c8532c97cc..343586e28c8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3086,7 +3086,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
&& y == const0_rtx
&& (code == EQ || code == NE || code == LT || code == GE)
- && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS))
+ && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS || GET_CODE (x) == AND))
return CC_NZmode;
/* A compare with a shifted operand. Because of canonicalization,
@@ -3348,7 +3348,7 @@ aarch64_print_operand (FILE *f, rtx x, char code)
output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
return;
}
- asm_fprintf (f, "%s%c%d", REGISTER_PREFIX, code, REGNO (x) - V0_REGNUM);
+ asm_fprintf (f, "%c%d", code, REGNO (x) - V0_REGNUM);
break;
case 'S':
@@ -3361,8 +3361,17 @@ aarch64_print_operand (FILE *f, rtx x, char code)
output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
return;
}
- asm_fprintf (f, "%sv%d", REGISTER_PREFIX,
- REGNO (x) - V0_REGNUM + (code - 'S'));
+ asm_fprintf (f, "v%d", REGNO (x) - V0_REGNUM + (code - 'S'));
+ break;
+
+ case 'X':
+ /* Print integer constant in hex. */
+ if (GET_CODE (x) != CONST_INT)
+ {
+ output_operand_lossage ("invalid operand for '%%%c'", code);
+ return;
+ }
+ asm_fprintf (f, "0x%x", UINTVAL (x));
break;
case 'w':
@@ -3372,20 +3381,19 @@ aarch64_print_operand (FILE *f, rtx x, char code)
if (x == const0_rtx
|| (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x)))
{
- asm_fprintf (f, "%s%czr", REGISTER_PREFIX, code);
+ asm_fprintf (f, "%czr", code);
break;
}
if (REG_P (x) && GP_REGNUM_P (REGNO (x)))
{
- asm_fprintf (f, "%s%c%d", REGISTER_PREFIX, code,
- REGNO (x) - R0_REGNUM);
+ asm_fprintf (f, "%c%d", code, REGNO (x) - R0_REGNUM);
break;
}
if (REG_P (x) && REGNO (x) == SP_REGNUM)
{
- asm_fprintf (f, "%s%ssp", REGISTER_PREFIX, code == 'w' ? "w" : "");
+ asm_fprintf (f, "%ssp", code == 'w' ? "w" : "");
break;
}
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 73d86a7a184..c28f4a013dc 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -844,8 +844,8 @@
(match_operand:GPI 2 "const_int_operand" "n"))]
"INTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)
&& INTVAL (operands[1]) % 16 == 0
- && INTVAL (operands[2]) <= 0xffff"
- "movk\\t%<w>0, %2, lsl %1"
+ && UINTVAL (operands[2]) <= 0xffff"
+ "movk\\t%<w>0, %X2, lsl %1"
[(set_attr "v8type" "movk")
(set_attr "mode" "<MODE>")]
)
@@ -1790,6 +1790,34 @@
(set_attr "mode" "SI")]
)
+(define_insn "*sub<mode>3_carryin"
+ [(set
+ (match_operand:GPI 0 "register_operand" "=r")
+ (minus:GPI (minus:GPI
+ (match_operand:GPI 1 "register_operand" "r")
+ (ltu:GPI (reg:CC CC_REGNUM) (const_int 0)))
+ (match_operand:GPI 2 "register_operand" "r")))]
+ ""
+ "sbc\\t%<w>0, %<w>1, %<w>2"
+ [(set_attr "v8type" "adc")
+ (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of the above
+(define_insn "*subsi3_carryin_uxtw"
+ [(set
+ (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (minus:SI (minus:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (ltu:SI (reg:CC CC_REGNUM) (const_int 0)))
+ (match_operand:SI 2 "register_operand" "r"))))]
+ ""
+ "sbc\\t%w0, %w1, %w2"
+ [(set_attr "v8type" "adc")
+ (set_attr "mode" "SI")]
+)
+
(define_insn "*sub_uxt<mode>_multp2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(minus:GPI (match_operand:GPI 4 "register_operand" "r")
@@ -2547,8 +2575,8 @@
)
(define_insn "*and<mode>3nr_compare0"
- [(set (reg:CC CC_REGNUM)
- (compare:CC
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:GPI (match_operand:GPI 0 "register_operand" "%r,r")
(match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
(const_int 0)))]
@@ -2558,8 +2586,8 @@
(set_attr "mode" "<MODE>")])
(define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
- [(set (reg:CC CC_REGNUM)
- (compare:CC
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
(and:GPI (SHIFT:GPI
(match_operand:GPI 0 "register_operand" "r")
(match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
@@ -2703,6 +2731,62 @@
(set_attr "mode" "<MODE>")]
)
+(define_insn "*extr<mode>5_insn"
+ [(set (match_operand:GPI 0 "register_operand" "=r")
+ (ior:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
+ (match_operand 3 "const_int_operand" "n"))
+ (lshiftrt:GPI (match_operand:GPI 2 "register_operand" "r")
+ (match_operand 4 "const_int_operand" "n"))))]
+ "UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) &&
+ (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
+ "extr\\t%<w>0, %<w>1, %<w>2, %4"
+ [(set_attr "v8type" "shift")
+ (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of the above
+(define_insn "*extrsi5_insn_uxtw"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand 3 "const_int_operand" "n"))
+ (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
+ (match_operand 4 "const_int_operand" "n")))))]
+ "UINTVAL (operands[3]) < 32 &&
+ (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
+ "extr\\t%w0, %w1, %w2, %4"
+ [(set_attr "v8type" "shift")
+ (set_attr "mode" "SI")]
+)
+
+(define_insn "*ror<mode>3_insn"
+ [(set (match_operand:GPI 0 "register_operand" "=r")
+ (rotate:GPI (match_operand:GPI 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand" "n")))]
+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+{
+ operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
+ return "ror\\t%<w>0, %<w>1, %3";
+}
+ [(set_attr "v8type" "shift")
+ (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of the above
+(define_insn "*rorsi3_insn_uxtw"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (rotate:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand" "n"))))]
+ "UINTVAL (operands[2]) < 32"
+{
+ operands[3] = GEN_INT (32 - UINTVAL (operands[2]));
+ return "ror\\t%w0, %w1, %3";
+}
+ [(set_attr "v8type" "shift")
+ (set_attr "mode" "SI")]
+)
+
(define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>"
[(set (match_operand:GPI 0 "register_operand" "=r")
(ANY_EXTEND:GPI
diff --git a/gcc/config/aarch64/t-aarch64-linux b/gcc/config/aarch64/t-aarch64-linux
index 48b4c69f6b4..a7a0a883605 100644
--- a/gcc/config/aarch64/t-aarch64-linux
+++ b/gcc/config/aarch64/t-aarch64-linux
@@ -22,4 +22,4 @@ LIB1ASMSRC = aarch64/lib1funcs.asm
LIB1ASMFUNCS = _aarch64_sync_cache_range
AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
-MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 09:52:32 +0000