diff options
Diffstat (limited to 'gcc/config/s390/s390.md')
| -rw-r--r-- | gcc/config/s390/s390.md | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 4b8b58ad45c..a0b9a3143a0 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -514,7 +514,7 @@ "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" "@ cgr\t%0,%1 - cghi\t%0,%c1 + cghi\t%0,%h1 cg\t%0,%1 #" [(set_attr "op_type" "RRE,RI,RXY,SS")]) @@ -526,7 +526,7 @@ "s390_match_ccmode (insn, CCTmode)" "@ cr\t%0,%1 - chi\t%0,%c1 + chi\t%0,%h1 c\t%0,%1 cy\t%0,%1 #" @@ -552,7 +552,7 @@ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "@ cgr\t%0,%1 - cghi\t%0,%c1 + cghi\t%0,%h1 cg\t%0,%1" [(set_attr "op_type" "RRE,RI,RXY")]) @@ -573,7 +573,7 @@ "s390_match_ccmode(insn, CCSmode)" "@ cr\t%0,%1 - chi\t%0,%c1 + chi\t%0,%h1 c\t%0,%1 cy\t%0,%1" [(set_attr "op_type" "RR,RI,RX,RXY")]) @@ -2660,6 +2660,27 @@ ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). ; +(define_insn "*llgt_sidi" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647)))] + "TARGET_64BIT" + "llgt\t%0,%1" + [(set_attr "op_type" "RXE")]) + +(define_insn_and_split "*llgt_sidi_split" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:DI (subreg:DI (match_dup 1) 0) + (const_int 2147483647)))] + "") + (define_insn "*llgt_sisi" [(set (match_operand:SI 0 "register_operand" "=d,d") (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") @@ -2702,27 +2723,6 @@ (const_int 2147483647)))] "") -(define_insn "*llgt_sidi" - [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) - (const_int 2147483647)))] - "TARGET_64BIT" - "llgt\t%0,%1" - [(set_attr "op_type" "RXE")]) - -(define_insn_and_split "*llgt_sidi_split" - [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) - (const_int 2147483647))) - (clobber (reg:CC 33))] - "TARGET_64BIT" - "#" - "&& reload_completed" - [(set (match_dup 0) - (and:DI (subreg:DI (match_dup 1) 0) - (const_int 2147483647)))] - "") - ; ; zero_extendqidi2 instruction pattern(s) ; @@ -2776,7 +2776,7 @@ (define_insn "*zero_extendhisi2_64" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] - "TARGET_64BIT" + "TARGET_ZARCH" "llgh\t%0,%1" [(set_attr "op_type" "RXY")]) @@ -2784,7 +2784,7 @@ [(set (match_operand:SI 0 "register_operand" "=&d") (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) (clobber (reg:CC 33))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) |