diff options
Diffstat (limited to 'gcc/config')
70 files changed, 902 insertions, 1144 deletions
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 0675916a230..5ffb8f967ff 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -7135,7 +7135,7 @@ alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP) /* When outputting a thunk, we don't have valid register life info, but assemble_start_function wants to output .frame and .mask directives. */ - if (crtl->is_thunk) + if (cfun->is_thunk) { *imaskP = 0; *fmaskP = 0; @@ -7365,7 +7365,7 @@ alpha_does_function_need_gp (void) return 1; /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */ - if (crtl->is_thunk) + if (cfun->is_thunk) return 1; /* The nonlocal receiver pattern assumes that the gp is valid for @@ -7888,7 +7888,7 @@ alpha_start_function (FILE *file, const char *fnname, Otherwise, do it here. */ if (TARGET_ABI_OSF && ! alpha_function_needs_gp - && ! crtl->is_thunk) + && ! cfun->is_thunk) { putc ('$', file); assemble_name (file, fnname); @@ -7999,7 +7999,7 @@ alpha_output_function_end_prologue (FILE *file) fputs ("\t.prologue 0\n", file); else if (!flag_inhibit_size_directive) fprintf (file, "\t.prologue %d\n", - alpha_function_needs_gp || crtl->is_thunk); + alpha_function_needs_gp || cfun->is_thunk); } /* Write function epilogue. */ @@ -8283,7 +8283,7 @@ alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED) output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL); #if TARGET_ABI_OSF - if (crtl->is_thunk) + if (cfun->is_thunk) free_after_compilation (cfun); #endif @@ -8326,7 +8326,7 @@ alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, HOST_WIDE_INT hi, lo; rtx this_rtx, insn, funexp; - gcc_assert (crtl->is_thunk); + gcc_assert (cfun->is_thunk); /* We always require a valid GP. */ emit_insn (gen_prologue_ldgp ()); diff --git a/gcc/config/alpha/driver-alpha.c b/gcc/config/alpha/driver-alpha.c new file mode 100644 index 00000000000..d787886d172 --- /dev/null +++ b/gcc/config/alpha/driver-alpha.c @@ -0,0 +1,100 @@ +/* Subroutines for the gcc driver. + Copyright (C) 2009 Free Software Foundation, Inc. + Contributed by Arthur Loiret <aloiret@debian.org> + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" + +/* This will be called by the spec parser in gcc.c when it sees + a %:local_cpu_detect(args) construct. Currently it will be called + with either "cpu" or "tune" as argument depending on if -mcpu=native + or -mtune=native is to be substituted. + + It returns a string containing new command line parameters to be + put at the place of the above two options, depending on what CPU + this is executed. E.g. "-mcpu=ev6" on an Alpha 21264 for + -mcpu=native. If the routine can't detect a known processor, + the -mcpu or -mtune option is discarded. + + ARGC and ARGV are set depending on the actual arguments given + in the spec. */ +const char * +host_detect_local_cpu (int argc, const char **argv) +{ + const char *cpu = NULL; + char buf[128]; + FILE *f; + + static const struct cpu_names { + const char *const name; + const char *const cpu; + } cpu_names[] = { + { "EV79", "ev67" }, + { "EV7", "ev67" }, + { "EV69", "ev67" }, + { "EV68CX", "ev67" }, + { "EV68CB", "ev67" }, + { "EV68AL", "ev67" }, + { "EV67", "ev67" }, + { "EV6", "ev6" }, + { "PCA57", "pca56" }, + { "PCA56", "pca56" }, + { "EV56", "ev56" }, + { "EV5", "ev5" }, + { "LCA45", "ev45" }, + { "EV45", "ev45" }, + { "LCA4", "ev4" }, + { "EV4", "ev4" }, +/* { "EV3", "ev3" }, */ + { 0, 0 } + }; + + int i; + + if (argc < 1) + return NULL; + + if (strcmp (argv[0], "cpu") && strcmp (argv[0], "tune")) + return NULL; + + f = fopen ("/proc/cpuinfo", "r"); + if (f == NULL) + return NULL; + + while (fgets (buf, sizeof (buf), f) != NULL) + if (strncmp (buf, "cpu model", sizeof ("cpu model") - 1) == 0) + { + for (i = 0; cpu_names [i].name; i++) + if (strstr (buf, cpu_names [i].name) != NULL) + { + cpu = cpu_names [i].cpu; + break; + } + break; + } + + fclose (f); + + if (cpu == NULL) + return NULL; + + return concat ("-m", argv[0], "=", cpu, NULL); +} diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h index 94876f646de..0a32479d5d7 100644 --- a/gcc/config/alpha/linux.h +++ b/gcc/config/alpha/linux.h @@ -85,3 +85,19 @@ along with GCC; see the file COPYING3. If not see /* Define if long doubles should be mangled as 'g'. */ #define TARGET_ALTERNATE_LONG_DOUBLE_MANGLING + +/* -mcpu=native handling only makes sense with compiler running on + an Alpha chip. */ +#if defined(__alpha__) || defined(__alpha) +extern const char *host_detect_local_cpu (int argc, const char **argv); +# define EXTRA_SPEC_FUNCTIONS \ + { "local_cpu_detect", host_detect_local_cpu }, + +# define MCPU_MTUNE_NATIVE_SPECS \ + " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ + " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" +#else +# define MCPU_MTUNE_NATIVE_SPECS "" +#endif + +#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS diff --git a/gcc/config/alpha/x-alpha b/gcc/config/alpha/x-alpha new file mode 100644 index 00000000000..27b5f466903 --- /dev/null +++ b/gcc/config/alpha/x-alpha @@ -0,0 +1,3 @@ +driver-alpha.o: $(srcdir)/config/alpha/driver-alpha.c \ + $(CONFIG_H) $(SYSTEM_H) + $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 7788793b300..f5ec9e7166e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2448,7 +2448,7 @@ extern int making_const_table; { \ if (is_called_in_ARM_mode (DECL) \ || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ - && crtl->is_thunk)) \ + && cfun->is_thunk)) \ fprintf (STREAM, "\t.code 32\n") ; \ else if (TARGET_THUMB1) \ fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ diff --git a/gcc/config/arm/rtems-elf.h b/gcc/config/arm/rtems-elf.h index ee8c118112a..dade74b1555 100644 --- a/gcc/config/arm/rtems-elf.h +++ b/gcc/config/arm/rtems-elf.h @@ -43,4 +43,3 @@ * with how this used to be defined. */ #undef LINK_GCC_C_SEQUENCE_SPEC -#define LINK_GCC_C_SEQUENCE_SPEC "%G %L" diff --git a/gcc/config/arm/t-arm-coff b/gcc/config/arm/t-arm-coff deleted file mode 100644 index 04880833e85..00000000000 --- a/gcc/config/arm/t-arm-coff +++ /dev/null @@ -1,34 +0,0 @@ -LIB1ASMSRC = arm/lib1funcs.asm -LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func _call_via_rX _interwork_call_via_rX _clzsi2 _clzdi2 - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - echo '#ifndef __ARMEB__' >> fp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c - echo '#endif' >> fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - echo '#ifndef __ARMEB__' > dp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c - echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c - echo '#endif' >> dp-bit.c - cat $(srcdir)/config/fp-bit.c >> dp-bit.c - -MULTILIB_OPTIONS = mlittle-endian/mbig-endian mhard-float/msoft-float marm/mthumb mno-thumb-interwork/mthumb-interwork -MULTILIB_DIRNAMES = le be fpu soft arm thumb normal interwork -MULTILIB_MATCHES = -EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib - -# Currently there is a bug somewhere in GCC's alias analysis -# or scheduling code that is breaking _fpmul_parts in fp-bit.c. -# Disabling function inlining is a workaround for this problem. -TARGET_LIBGCC2_CFLAGS = -fno-inline diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index bcf81d9afc5..2df4a16d1cf 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -1,6 +1,6 @@ /* Prototypes for exported functions defined in avr.c - Copyright (C) 2000, 2001, 2002, 2003, 2004, 2006, 2007, 2008 + Copyright (C) 2000, 2001, 2002, 2003, 2004, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. Contributed by Denis Chertykov (denisc@overta.ru) @@ -32,6 +32,7 @@ extern enum reg_class avr_regno_reg_class (int r); extern enum reg_class avr_reg_class_from_letter (int c); extern int frame_pointer_required_p (void); extern void asm_globalize_label (FILE *file, const char *name); +extern void avr_asm_declare_function_name (FILE *, const char *, tree); extern void order_regs_for_local_alloc (void); extern int initial_elimination_offset (int from, int to); extern int avr_simple_epilogue (void); diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index f8ef6d58fa2..82a9742392c 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -219,6 +219,8 @@ static const struct mcu_type_s avr_mcu_types[] = { { "atmega8hva", ARCH_AVR4, "__AVR_ATmega8HVA__" }, { "atmega4hvd", ARCH_AVR4, "__AVR_ATmega4HVD__" }, { "atmega8hvd", ARCH_AVR4, "__AVR_ATmega8HVD__" }, + { "atmega8c1", ARCH_AVR4, "__AVR_ATmega8C1__" }, + { "atmega8m1", ARCH_AVR4, "__AVR_ATmega8M1__" }, { "at90pwm1", ARCH_AVR4, "__AVR_AT90PWM1__" }, { "at90pwm2", ARCH_AVR4, "__AVR_AT90PWM2__" }, { "at90pwm2b", ARCH_AVR4, "__AVR_AT90PWM2B__" }, @@ -266,6 +268,7 @@ static const struct mcu_type_s avr_mcu_types[] = { { "at90can64", ARCH_AVR5, "__AVR_AT90CAN64__" }, { "at90pwm216", ARCH_AVR5, "__AVR_AT90PWM216__" }, { "at90pwm316", ARCH_AVR5, "__AVR_AT90PWM316__" }, + { "atmega16c1", ARCH_AVR5, "__AVR_ATmega16C1__" }, { "atmega32c1", ARCH_AVR5, "__AVR_ATmega32C1__" }, { "atmega64c1", ARCH_AVR5, "__AVR_ATmega64C1__" }, { "atmega16m1", ARCH_AVR5, "__AVR_ATmega16M1__" }, @@ -4595,6 +4598,39 @@ avr_assemble_integer (rtx x, unsigned int size, int aligned_p) return default_assemble_integer (x, size, aligned_p); } +/* Worker function for ASM_DECLARE_FUNCTION_NAME. */ + +void +avr_asm_declare_function_name (FILE *file, const char *name, tree decl) +{ + + /* If the function has the 'signal' or 'interrupt' attribute, test to + make sure that the name of the function is "__vector_NN" so as to + catch when the user misspells the interrupt vector name. */ + + if (cfun->machine->is_interrupt) + { + if (strncmp (name, "__vector", strlen ("__vector")) != 0) + { + warning_at (DECL_SOURCE_LOCATION (decl), 0, + "%qs appears to be a misspelled interrupt handler", + name); + } + } + else if (cfun->machine->is_signal) + { + if (strncmp (name, "__vector", strlen ("__vector")) != 0) + { + warning_at (DECL_SOURCE_LOCATION (decl), 0, + "%qs appears to be a misspelled signal handler", + name); + } + } + + ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); + ASM_OUTPUT_LABEL (file, name); +} + /* The routine used to output NUL terminated strings. We use a special version of this for most svr4 targets because doing so makes the generated assembly code more compact (and thus faster to assemble) @@ -4779,32 +4815,6 @@ avr_handle_fndecl_attribute (tree *node, tree name, IDENTIFIER_POINTER (name)); *no_add_attrs = true; } - else - { - const char *func_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (*node)); - const char *attr = IDENTIFIER_POINTER (name); - - /* If the function has the 'signal' or 'interrupt' attribute, test to - make sure that the name of the function is "__vector_NN" so as to - catch when the user misspells the interrupt vector name. */ - - if (strncmp (attr, "interrupt", strlen ("interrupt")) == 0) - { - if (strncmp (func_name, "__vector", strlen ("__vector")) != 0) - { - warning (0, "%qs appears to be a misspelled interrupt handler", - func_name); - } - } - else if (strncmp (attr, "signal", strlen ("signal")) == 0) - { - if (strncmp (func_name, "__vector", strlen ("__vector")) != 0) - { - warning (0, "%qs appears to be a misspelled signal handler", - func_name); - } - } - } return NULL_TREE; } diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 8a4d98ab365..54c607a0e04 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -590,10 +590,7 @@ do { \ specific tm.h file (depending upon the particulars of your assembler). */ #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -do { \ - ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ - ASM_OUTPUT_LABEL (FILE, NAME); \ -} while (0) +avr_asm_declare_function_name ((FILE), (NAME), (DECL)) #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ do { \ @@ -893,8 +890,11 @@ mmcu=*:-mmcu=%*}" mmcu=attiny327|\ mmcu=at90can*|\ mmcu=at90pwm*|\ + mmcu=atmega8c1|\ + mmcu=atmega16c1|\ mmcu=atmega32c1|\ mmcu=atmega64c1|\ + mmcu=atmega8m1|\ mmcu=atmega16m1|\ mmcu=atmega32m1|\ mmcu=atmega64m1|\ @@ -975,6 +975,8 @@ mmcu=*:-mmcu=%*}" %{mmcu=atmega88p:crtm88p.o%s} \ %{mmcu=atmega8515:crtm8515.o%s} \ %{mmcu=atmega8535:crtm8535.o%s} \ +%{mmcu=atmega8c1:crtm8c1.o%s} \ +%{mmcu=atmega8m1:crtm8m1.o%s} \ %{mmcu=at90pwm1:crt90pwm1.o%s} \ %{mmcu=at90pwm2:crt90pwm2.o%s} \ %{mmcu=at90pwm2b:crt90pwm2b.o%s} \ @@ -1023,6 +1025,7 @@ mmcu=*:-mmcu=%*}" %{mmcu=at90can64:crtcan64.o%s} \ %{mmcu=at90pwm216:crt90pwm216.o%s} \ %{mmcu=at90pwm316:crt90pwm316.o%s} \ +%{mmcu=atmega16c1:crtm16c1.o%s} \ %{mmcu=atmega32c1:crtm32c1.o%s} \ %{mmcu=atmega64c1:crtm64c1.o%s} \ %{mmcu=atmega16m1:crtm16m1.o%s} \ diff --git a/gcc/config/avr/t-avr b/gcc/config/avr/t-avr index 9d8d386c787..7513b3d4afb 100644 --- a/gcc/config/avr/t-avr +++ b/gcc/config/avr/t-avr @@ -79,6 +79,8 @@ MULTILIB_MATCHES = \ mmcu?avr4=mmcu?atmega8hva \ mmcu?avr4=mmcu?atmega4hvd \ mmcu?avr4=mmcu?atmega8hvd \ + mmcu?avr4=mmcu?atmega8c1 \ + mmcu?avr4=mmcu?atmega8m1 \ mmcu?avr4=mmcu?at90pwm1 \ mmcu?avr4=mmcu?at90pwm2 \ mmcu?avr4=mmcu?at90pwm2b \ @@ -124,6 +126,7 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?at90can64 \ mmcu?avr5=mmcu?at90pwm216 \ mmcu?avr5=mmcu?at90pwm316 \ + mmcu?avr5=mmcu?atmega16c1 \ mmcu?avr5=mmcu?atmega32c1 \ mmcu?avr5=mmcu?atmega64c1 \ mmcu?avr5=mmcu?atmega16m1 \ diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index ec5dd57dde7..d1c964d02ea 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -3854,9 +3854,17 @@ bfin_optimize_loop (loop_info loop) /* Make sure the predecessor is before the loop start label, as required by the LSETUP instruction. */ length = 0; - for (insn = BB_END (loop->incoming_src); - insn && insn != loop->start_label; - insn = NEXT_INSN (insn)) + insn = BB_END (loop->incoming_src); + /* If we have to insert the LSETUP before a jump, count that jump in the + length. */ + if (VEC_length (edge, loop->incoming) > 1 + || !(VEC_last (edge, loop->incoming)->flags & EDGE_FALLTHRU)) + { + gcc_assert (JUMP_P (insn)); + insn = PREV_INSN (insn); + } + + for (; insn && insn != loop->start_label; insn = NEXT_INSN (insn)) length += length_for_loop (insn); if (!insn) @@ -4362,6 +4370,12 @@ bfin_discover_loop (loop_info loop, basic_block tail_bb, rtx tail_insn) break; } } + if (!retry) + { + if (dump_file) + fprintf (dump_file, ";; No forwarder blocks found\n"); + loop->bad = 1; + } } } } diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index eae8b484904..49822598f45 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -851,8 +851,9 @@ enum reg_class /* Node: Elimination */ /* Really only needed if the stack frame has variable length (alloca - or variable sized local arguments (GNU C extension). */ -#define FRAME_POINTER_REQUIRED 0 + or variable sized local arguments (GNU C extension). See PR39499 and + PR38609 for the reason this isn't just 0. */ +#define FRAME_POINTER_REQUIRED (!current_function_sp_is_unchanging) #define ELIMINABLE_REGS \ {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ diff --git a/gcc/config/cris/libgcc.ver b/gcc/config/cris/libgcc.ver new file mode 100644 index 00000000000..e35de83100f --- /dev/null +++ b/gcc/config/cris/libgcc.ver @@ -0,0 +1,7 @@ +GCC_4.3 { + __Mul + __Div + __Udiv + __Mod + __Umod +} diff --git a/gcc/config/cris/linux.h b/gcc/config/cris/linux.h index 247e827d677..38f0a7ef8c9 100644 --- a/gcc/config/cris/linux.h +++ b/gcc/config/cris/linux.h @@ -110,7 +110,8 @@ along with GCC; see the file COPYING3. If not see #undef CRIS_LINK_SUBTARGET_SPEC #define CRIS_LINK_SUBTARGET_SPEC \ "-mcrislinux\ - -rpath-link include/asm/../..%s\ + %{B*:-rpath-link %*}\ + %{!nostdlib:-rpath-link ../sys-include/asm/../../lib%s}\ %{shared} %{static}\ %{symbolic:-Bdynamic} %{shlib:-Bdynamic} %{static:-Bstatic}\ %{!shared:%{!static:\ diff --git a/gcc/config/cris/t-linux b/gcc/config/cris/t-linux index e10d083f565..96e861a4283 100644 --- a/gcc/config/cris/t-linux +++ b/gcc/config/cris/t-linux @@ -1,5 +1,6 @@ TARGET_LIBGCC2_CFLAGS += -fPIC CRTSTUFF_T_CFLAGS_S = $(TARGET_LIBGCC2_CFLAGS) +SHLIB_MAPFILES += $(srcdir)/config/cris/libgcc.ver # We *know* we have a limits.h in the glibc library, with extra # definitions needed for e.g. libgfortran. diff --git a/gcc/config/fr30/fr30.opt b/gcc/config/fr30/fr30.opt index ac8567da1f3..da6148a6d2b 100644 --- a/gcc/config/fr30/fr30.opt +++ b/gcc/config/fr30/fr30.opt @@ -1,6 +1,6 @@ ; Options for the FR30 port of the compiler. -; Copyright (C) 2005, 2007 Free Software Foundation, Inc. +; Copyright (C) 2005, 2007, 2009 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -23,4 +23,5 @@ Target Report Mask(SMALL_MODEL) Assume small address space mno-lsim -Target RejectNegative Undocumented +Target RejectNegative +Assume that run-time support has been provided, so omit -lsim from the linker command line diff --git a/gcc/config/h8300/coff.h b/gcc/config/h8300/coff.h deleted file mode 100644 index d4b6c9b7da9..00000000000 --- a/gcc/config/h8300/coff.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Definitions of target machine for GNU compiler. - Renesas H8/300 version generating coff - Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. - Contributed by Steve Chamberlain (sac@cygnus.com), - Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -#ifndef GCC_H8300_COFF_H -#define GCC_H8300_COFF_H - -#define SDB_DEBUGGING_INFO 1 -#define SDB_DELIM "\n" - -/* Generate a blank trailing N_SO to mark the end of the .o file, since - we can't depend upon the linker to mark .o file boundaries with - embedded stabs. */ - -#define DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END - -/* This is how to output an assembler line - that says to advance the location counter by SIZE bytes. */ - -#define ASM_OUTPUT_IDENT(FILE, NAME) \ - fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME) - -#define IDENT_ASM_OP "\t.ident\t" -#define INIT_SECTION_ASM_OP "\t.section .init" -#define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata" - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION h8300_asm_named_section - -/* A bit-field declared as `int' forces `int' alignment for the struct. */ -#define PCC_BITFIELD_TYPE_MATTERS 0 - -#endif /* h8300/coff.h */ diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index db43ffda08b..431e926818a 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -34,7 +34,7 @@ along with GCC; see the file COPYING3. If not see #endif #undef TARGET_64BIT_MS_ABI -#define TARGET_64BIT_MS_ABI (!cfun ? DEFAULT_ABI == MS_ABI : TARGET_64BIT && cfun->machine->call_abi == MS_ABI) +#define TARGET_64BIT_MS_ABI (!cfun ? ix86_abi == MS_ABI : TARGET_64BIT && cfun->machine->call_abi == MS_ABI) #undef DEFAULT_ABI #define DEFAULT_ABI (TARGET_64BIT ? MS_ABI : SYSV_ABI) @@ -202,7 +202,7 @@ do { \ #define CHECK_STACK_LIMIT 4000 #undef STACK_BOUNDARY -#define STACK_BOUNDARY (DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD) +#define STACK_BOUNDARY (ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) /* By default, target has a 80387, uses IEEE compatible arithmetic, returns float values in the 387 and needs stack probes. diff --git a/gcc/config/i386/i386-aout.h b/gcc/config/i386/i386-aout.h deleted file mode 100644 index e28f28c0280..00000000000 --- a/gcc/config/i386/i386-aout.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Definitions for "naked" Intel 386 using a.out (or coff encap'd - a.out) object format and stabs debugging info. - - Copyright (C) 1994, 2002, 2007 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - - -#define TARGET_VERSION fprintf (stderr, " (80386, BSD a.out syntax)"); - -/* end of i386-aout.h */ diff --git a/gcc/config/i386/i386-coff.h b/gcc/config/i386/i386-coff.h deleted file mode 100644 index af0204bb59e..00000000000 --- a/gcc/config/i386/i386-coff.h +++ /dev/null @@ -1,69 +0,0 @@ -/* Definitions for "naked" Intel 386 using coff object format files - and coff debugging info. - - Copyright (C) 1994, 2000, 2002, 2004, 2007 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - - -#define TARGET_VERSION fprintf (stderr, " (80386, COFF BSD syntax)"); - -#define TARGET_OS_CPP_BUILTINS() /* Sweet FA. */ - -/* We want to be able to get DBX debugging information via -gstabs. */ - -#define DBX_DEBUGGING_INFO 1 - -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION default_coff_asm_named_section - -/* Prefix for internally generated assembler labels. If we aren't using - underscores, we are using prefix `.'s to identify labels that should - be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ - -#undef LPREFIX -#define LPREFIX ".L" - -/* The prefix to add to user-visible assembler symbols. */ - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" - -/* If user-symbols don't have underscores, - then it must take more than `L' to identify - a label that should be ignored. */ - -/* This is how to store into the string BUF - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. */ - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ - sprintf ((BUF), ".%s%ld", (PREFIX), (long)(NUMBER)) - -/* GNU as expects alignment to be the number of bytes instead of the log for - COFF targets. */ - -#undef ASM_OUTPUT_ALIGN -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) - -/* end of i386-coff.h */ diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 23936a8d1e1..d6b30781692 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -85,6 +85,7 @@ extern void ix86_fixup_binary_operands_no_copy (enum rtx_code, extern void ix86_expand_binary_operator (enum rtx_code, enum machine_mode, rtx[]); extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]); +extern bool ix86_agi_dependent (rtx set_insn, rtx use_insn); extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode, rtx[]); extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx); @@ -139,9 +140,8 @@ extern int ix86_function_arg_boundary (enum machine_mode, tree); extern bool ix86_sol10_return_in_memory (const_tree,const_tree); extern rtx ix86_force_to_memory (enum machine_mode, rtx); extern void ix86_free_from_memory (enum machine_mode); -extern int ix86_cfun_abi (void); -extern int ix86_function_abi (const_tree); -extern int ix86_function_type_abi (const_tree); +extern enum calling_abi ix86_cfun_abi (void); +extern enum calling_abi ix86_function_type_abi (const_tree); extern void ix86_call_abi_override (const_tree); extern tree ix86_fn_abi_va_list (tree); extern tree ix86_canonical_va_list_type (tree); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 120ab156fb1..3dec02f3acd 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1533,24 +1533,8 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] = -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */ }; -static int const x86_64_int_parameter_registers[6] = -{ - 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/, - FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */ -}; - -static int const x86_64_ms_abi_int_parameter_registers[4] = -{ - 2 /*RCX*/, 1 /*RDX*/, - FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */ -}; - -static int const x86_64_int_return_registers[4] = -{ - 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/ -}; - /* The "default" register map used in 64bit mode. */ + int const dbx64_register_map[FIRST_PSEUDO_REGISTER] = { 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */ @@ -1634,6 +1618,23 @@ rtx ix86_compare_op0 = NULL_RTX; rtx ix86_compare_op1 = NULL_RTX; rtx ix86_compare_emitted = NULL_RTX; +/* Define parameter passing and return registers. */ + +static int const x86_64_int_parameter_registers[6] = +{ + DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG +}; + +static int const x86_64_ms_abi_int_parameter_registers[4] = +{ + CX_REG, DX_REG, R8_REG, R9_REG +}; + +static int const x86_64_int_return_registers[4] = +{ + AX_REG, DX_REG, DI_REG, SI_REG +}; + /* Define the structure for the machine field in struct function. */ struct stack_local_entry GTY(()) @@ -1742,6 +1743,9 @@ static unsigned int ix86_default_incoming_stack_boundary; /* Alignment for incoming stack boundary in bits. */ unsigned int ix86_incoming_stack_boundary; +/* The abi used by target. */ +enum calling_abi ix86_abi = DEFAULT_ABI; + /* Values 1-5: see jump.c */ int ix86_branch_cost; @@ -1818,6 +1822,8 @@ static bool ix86_valid_target_attribute_inner_p (tree, char *[]); static bool ix86_can_inline_p (tree, tree); static void ix86_set_current_function (tree); +static enum calling_abi ix86_function_abi (const_tree); + /* The svr4 ABI for the i386 says that records and unions are returned in memory. */ @@ -2715,6 +2721,18 @@ override_options (bool main_args_p) error ("bad value (%s) for %sarch=%s %s", ix86_arch_string, prefix, suffix, sw); + /* Validate -mabi= value. */ + if (ix86_abi_string) + { + if (strcmp (ix86_abi_string, "sysv") == 0) + ix86_abi = SYSV_ABI; + else if (strcmp (ix86_abi_string, "ms") == 0) + ix86_abi = MS_ABI; + else + error ("unknown ABI (%s) for %sabi=%s %s", + ix86_abi_string, prefix, suffix, sw); + } + if (ix86_cmodel_string != 0) { if (!strcmp (ix86_cmodel_string, "small")) @@ -4272,17 +4290,15 @@ static int ix86_function_regparm (const_tree type, const_tree decl) { tree attr; - int regparm = ix86_regparm; + int regparm; static bool error_issued; if (TARGET_64BIT) - { - if (ix86_function_type_abi (type) == DEFAULT_ABI) - return regparm; - return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX; - } + return (ix86_function_type_abi (type) == SYSV_ABI + ? X86_64_REGPARM_MAX : X64_REGPARM_MAX); + regparm = ix86_regparm; attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type)); if (attr) { @@ -4310,7 +4326,9 @@ ix86_function_regparm (const_tree type, const_tree decl) return 2; /* Use register calling convention for local functions when possible. */ - if (decl && TREE_CODE (decl) == FUNCTION_DECL + if (decl + && TREE_CODE (decl) == FUNCTION_DECL + && optimize && !profile_flag) { /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */ @@ -4395,7 +4413,7 @@ ix86_function_sseregparm (const_tree type, const_tree decl, bool warn) /* For local functions, pass up to SSE_REGPARM_MAX SFmode (and DFmode for SSE2) arguments in SSE registers. */ - if (decl && TARGET_SSE_MATH && !profile_flag) + if (decl && TARGET_SSE_MATH && optimize && !profile_flag) { /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */ struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl)); @@ -4514,14 +4532,14 @@ ix86_function_arg_regno_p (int regno) default ABI. */ /* RAX is used as hidden argument to va_arg functions. */ - if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG) + if (ix86_abi == SYSV_ABI && regno == AX_REG) return true; - if (DEFAULT_ABI == MS_ABI) + if (ix86_abi == MS_ABI) parm_regs = x86_64_ms_abi_int_parameter_registers; else parm_regs = x86_64_int_parameter_registers; - for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX + for (i = 0; i < (ix86_abi == MS_ABI ? X64_REGPARM_MAX : X86_64_REGPARM_MAX); i++) if (regno == parm_regs[i]) return true; @@ -4549,7 +4567,7 @@ ix86_must_pass_in_stack (enum machine_mode mode, const_tree type) int ix86_reg_parm_stack_space (const_tree fndecl) { - int call_abi = SYSV_ABI; + enum calling_abi call_abi = SYSV_ABI; if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL) call_abi = ix86_function_abi (fndecl); else @@ -4561,37 +4579,39 @@ ix86_reg_parm_stack_space (const_tree fndecl) /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the call abi used. */ -int +enum calling_abi ix86_function_type_abi (const_tree fntype) { if (TARGET_64BIT && fntype != NULL) { - int abi; - if (DEFAULT_ABI == SYSV_ABI) - abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI; - else - abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI; - + enum calling_abi abi = ix86_abi; + if (abi == SYSV_ABI) + { + if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype))) + abi = MS_ABI; + } + else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype))) + abi = SYSV_ABI; return abi; } - return DEFAULT_ABI; + return ix86_abi; } -int +static enum calling_abi ix86_function_abi (const_tree fndecl) { if (! fndecl) - return DEFAULT_ABI; + return ix86_abi; return ix86_function_type_abi (TREE_TYPE (fndecl)); } /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the call abi used. */ -int +enum calling_abi ix86_cfun_abi (void) { if (! cfun || ! TARGET_64BIT) - return DEFAULT_ABI; + return ix86_abi; return cfun->machine->call_abi; } @@ -4605,7 +4625,7 @@ void ix86_call_abi_override (const_tree fndecl) { if (fndecl == NULL_TREE) - cfun->machine->call_abi = DEFAULT_ABI; + cfun->machine->call_abi = ix86_abi; else cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl)); } @@ -4617,7 +4637,7 @@ static void ix86_maybe_switch_abi (void) { if (TARGET_64BIT && - call_used_regs[4 /*RSI*/] == (cfun->machine->call_abi == MS_ABI)) + call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI)) reinit_regs (); } @@ -4645,8 +4665,8 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ cum->nregs = ix86_regparm; if (TARGET_64BIT) { - if (cum->call_abi != DEFAULT_ABI) - cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX + if (cum->call_abi != ix86_abi) + cum->nregs = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX; } if (TARGET_SSE) @@ -4654,8 +4674,8 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ cum->sse_nregs = SSE_REGPARM_MAX; if (TARGET_64BIT) { - if (cum->call_abi != DEFAULT_ABI) - cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX + if (cum->call_abi != ix86_abi) + cum->sse_nregs = ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X64_SSE_REGPARM_MAX; } } @@ -4922,8 +4942,30 @@ classify_argument (enum machine_mode mode, const_tree type, } else { - num = classify_argument (TYPE_MODE (TREE_TYPE (field)), - TREE_TYPE (field), subclasses, + type = TREE_TYPE (field); + + /* Flexible array member is ignored. */ + if (TYPE_MODE (type) == BLKmode + && TREE_CODE (type) == ARRAY_TYPE + && TYPE_SIZE (type) == NULL_TREE + && TYPE_DOMAIN (type) != NULL_TREE + && (TYPE_MAX_VALUE (TYPE_DOMAIN (type)) + == NULL_TREE)) + { + static bool warned; + + if (!warned && warn_psabi) + { + warned = true; + inform (input_location, + "The ABI of passing struct with" + " a flexible array member has" + " changed in GCC 4.4"); + } + continue; + } + num = classify_argument (TYPE_MODE (type), type, + subclasses, (int_bit_position (field) + bit_offset) % 256); if (!num) @@ -5581,7 +5623,7 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, if (type) mode = type_natural_mode (type, NULL); - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI) + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) function_arg_advance_ms_64 (cum, bytes, words); else if (TARGET_64BIT) function_arg_advance_64 (cum, mode, type, words, named); @@ -5727,9 +5769,9 @@ function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode, if (mode == VOIDmode) return GEN_INT (cum->maybe_vaarg ? (cum->sse_nregs < 0 - ? (cum->call_abi == DEFAULT_ABI + ? (cum->call_abi == ix86_abi ? SSE_REGPARM_MAX - : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX + : (ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X64_SSE_REGPARM_MAX)) : cum->sse_regno) : -1); @@ -5823,7 +5865,7 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode, if (type && TREE_CODE (type) == VECTOR_TYPE) mode = type_natural_mode (type, cum); - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI) + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) return function_arg_ms_64 (cum, mode, omode, named, bytes); else if (TARGET_64BIT) return function_arg_64 (cum, mode, omode, type, named); @@ -5843,7 +5885,7 @@ ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, const_tree type, bool named ATTRIBUTE_UNUSED) { /* See Windows x64 Software Convention. */ - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI) + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) { int msize = (int) GET_MODE_SIZE (mode); if (type) @@ -5983,7 +6025,7 @@ ix86_function_value_regno_p (int regno) /* TODO: The function should depend on current function ABI but builtins.c would need updating then. Therefore we use the default ABI. */ - if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) + if (TARGET_64BIT && ix86_abi == MS_ABI) return false; return TARGET_FLOAT_RETURNS_IN_80387; @@ -6379,13 +6421,13 @@ ix86_build_builtin_va_list_abi (enum calling_abi abi) static tree ix86_build_builtin_va_list (void) { - tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI); + tree ret = ix86_build_builtin_va_list_abi (ix86_abi); /* Initialize abi specific va_list builtin types. */ if (TARGET_64BIT) { tree t; - if (DEFAULT_ABI == MS_ABI) + if (ix86_abi == MS_ABI) { t = ix86_build_builtin_va_list_abi (SYSV_ABI); if (TREE_CODE (t) != RECORD_TYPE) @@ -6399,7 +6441,7 @@ ix86_build_builtin_va_list (void) t = build_variant_type_copy (t); sysv_va_list_type_node = t; } - if (DEFAULT_ABI != MS_ABI) + if (ix86_abi != MS_ABI) { t = ix86_build_builtin_va_list_abi (MS_ABI); if (TREE_CODE (t) != RECORD_TYPE) @@ -6432,8 +6474,8 @@ setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum) int i; int regparm = ix86_regparm; - if (cum->call_abi != DEFAULT_ABI) - regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX; + if (cum->call_abi != ix86_abi) + regparm = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX; /* GPR size of varargs save area. */ if (cfun->va_list_gpr_size) @@ -6586,7 +6628,7 @@ is_va_list_char_pointer (tree type) return true; canonic = ix86_canonical_va_list_type (type); return (canonic == ms_va_list_type_node - || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node)); + || (ix86_abi == MS_ABI && canonic == va_list_type_node)); } /* Implement va_start. */ @@ -12632,10 +12674,9 @@ ix86_expand_push (enum machine_mode mode, rtx x) tmp = gen_rtx_MEM (mode, stack_pointer_rtx); /* When we push an operand onto stack, it has to be aligned at least - at the function argument boundary. */ - set_mem_align (tmp, - ix86_function_arg_boundary (mode, NULL_TREE)); - + at the function argument boundary. However since we don't have + the argument type, we can't determine the actual argument + boundary. */ emit_move_insn (tmp, x); } @@ -18617,12 +18658,7 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx pop, int sibcall) { rtx use = NULL, call; - enum calling_abi function_call_abi; - if (callarg2 && INTVAL (callarg2) == -2) - function_call_abi = MS_ABI; - else - function_call_abi = SYSV_ABI; if (pop == const0_rtx) pop = NULL; gcc_assert (!TARGET_64BIT || !pop); @@ -18678,14 +18714,19 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1, pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop); pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop); call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop)); - gcc_assert (ix86_cfun_abi () != MS_ABI || function_call_abi != SYSV_ABI); } - /* We need to represent that SI and DI registers are clobbered - by SYSV calls. */ - if (ix86_cfun_abi () == MS_ABI && function_call_abi == SYSV_ABI) - { - static int clobbered_registers[] = {27, 28, 45, 46, 47, 48, 49, 50, 51, - 52, SI_REG, DI_REG}; + if (TARGET_64BIT + && ix86_cfun_abi () == MS_ABI + && (!callarg2 || INTVAL (callarg2) != -2)) + { + /* We need to represent that SI and DI registers are clobbered + by SYSV calls. */ + static int clobbered_registers[] = { + XMM6_REG, XMM7_REG, XMM8_REG, + XMM9_REG, XMM10_REG, XMM11_REG, + XMM12_REG, XMM13_REG, XMM14_REG, + XMM15_REG, SI_REG, DI_REG + }; unsigned int i; rtx vec[ARRAY_SIZE (clobbered_registers) + 2]; rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), @@ -18724,7 +18765,7 @@ ix86_init_machine_status (void) f = GGC_CNEW (struct machine_function); f->use_fast_prologue_epilogue_nregs = -1; f->tls_descriptor_call_expanded_p = 0; - f->call_abi = DEFAULT_ABI; + f->call_abi = ix86_abi; return f; } @@ -19051,41 +19092,21 @@ ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type) return 1; } -/* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory - address with operands set by DEP_INSN. */ +/* Return true iff USE_INSN has a memory address with operands set by + SET_INSN. */ -static int -ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type) +bool +ix86_agi_dependent (rtx set_insn, rtx use_insn) { - rtx addr; - - if (insn_type == TYPE_LEA - && TARGET_PENTIUM) - { - addr = PATTERN (insn); - - if (GET_CODE (addr) == PARALLEL) - addr = XVECEXP (addr, 0, 0); - - gcc_assert (GET_CODE (addr) == SET); - - addr = SET_SRC (addr); - } - else - { - int i; - extract_insn_cached (insn); - for (i = recog_data.n_operands - 1; i >= 0; --i) - if (MEM_P (recog_data.operand[i])) - { - addr = XEXP (recog_data.operand[i], 0); - goto found; - } - return 0; - found:; - } - - return modified_in_p (addr, dep_insn); + int i; + extract_insn_cached (use_insn); + for (i = recog_data.n_operands - 1; i >= 0; --i) + if (MEM_P (recog_data.operand[i])) + { + rtx addr = XEXP (recog_data.operand[i], 0); + return modified_in_p (addr, set_insn) != 0; + } + return false; } static int @@ -19113,7 +19134,20 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) { case PROCESSOR_PENTIUM: /* Address Generation Interlock adds a cycle of latency. */ - if (ix86_agi_dependent (insn, dep_insn, insn_type)) + if (insn_type == TYPE_LEA) + { + rtx addr = PATTERN (insn); + + if (GET_CODE (addr) == PARALLEL) + addr = XVECEXP (addr, 0, 0); + + gcc_assert (GET_CODE (addr) == SET); + + addr = SET_SRC (addr); + if (modified_in_p (addr, dep_insn)) + cost += 1; + } + else if (ix86_agi_dependent (dep_insn, insn)) cost += 1; /* ??? Compares pair with jump/setcc. */ @@ -19123,7 +19157,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) /* Floating point stores require value to be ready one cycle earlier. */ if (insn_type == TYPE_FMOV && get_attr_memory (insn) == MEMORY_STORE - && !ix86_agi_dependent (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (dep_insn, insn)) cost += 1; break; @@ -19146,7 +19180,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) in parallel with previous instruction in case previous instruction is not needed to compute the address. */ if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) - && !ix86_agi_dependent (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (dep_insn, insn)) { /* Claim moves to take one cycle, as core can issue one load at time and the next load can start cycle later. */ @@ -19175,7 +19209,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) in parallel with previous instruction in case previous instruction is not needed to compute the address. */ if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) - && !ix86_agi_dependent (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (dep_insn, insn)) { /* Claim moves to take one cycle, as core can issue one load at time and the next load can start cycle later. */ @@ -19200,7 +19234,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) in parallel with previous instruction in case previous instruction is not needed to compute the address. */ if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) - && !ix86_agi_dependent (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (dep_insn, insn)) { enum attr_unit unit = get_attr_unit (insn); int loadcost = 3; @@ -19342,15 +19376,39 @@ ix86_data_alignment (tree type, int align) return align; } -/* Compute the alignment for a local variable or a stack slot. TYPE is - the data type, MODE is the widest mode available and ALIGN is the - alignment that the object would ordinarily have. The value of this - macro is used instead of that alignment to align the object. */ +/* Compute the alignment for a local variable or a stack slot. EXP is + the data type or decl itself, MODE is the widest mode available and + ALIGN is the alignment that the object would ordinarily have. The + value of this macro is used instead of that alignment to align the + object. */ unsigned int -ix86_local_alignment (tree type, enum machine_mode mode, +ix86_local_alignment (tree exp, enum machine_mode mode, unsigned int align) { + tree type, decl; + + if (exp && DECL_P (exp)) + { + type = TREE_TYPE (exp); + decl = exp; + } + else + { + type = exp; + decl = NULL; + } + + /* Don't do dynamic stack realignment for long long objects with + -mpreferred-stack-boundary=2. */ + if (!TARGET_64BIT + && align == 64 + && ix86_preferred_stack_boundary < 64 + && (mode == DImode || (type && TYPE_MODE (type) == DImode)) + && (!type || !TYPE_USER_ALIGN (type)) + && (!decl || !DECL_USER_ALIGN (decl))) + align = 32; + /* If TYPE is NULL, we are allocating a stack slot for caller-save register in MODE. We will return the largest alignment of XF and DF. */ @@ -20182,6 +20240,7 @@ enum ix86_builtins /* TFmode support builtins. */ IX86_BUILTIN_INFQ, + IX86_BUILTIN_HUGE_VALQ, IX86_BUILTIN_FABSQ, IX86_BUILTIN_COPYSIGNQ, @@ -23350,6 +23409,11 @@ ix86_init_builtins (void) NULL, NULL_TREE); ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl; + decl = add_builtin_function ("__builtin_huge_valq", ftype, + IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD, + NULL, NULL_TREE); + ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl; + /* We will expand them to normal call if SSE2 isn't available since they are used by libgcc. */ ftype = build_function_type_list (float128_type_node, @@ -24805,6 +24869,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return ix86_expand_vec_set_builtin (exp); case IX86_BUILTIN_INFQ: + case IX86_BUILTIN_HUGE_VALQ: { REAL_VALUE_TYPE inf; rtx tmp; @@ -25757,7 +25822,7 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) { /* Take care for QImode values - they can be in non-QI regs, but then they do cause partial register stalls. */ - if (regno < 4 || TARGET_64BIT) + if (regno <= BX_REG || TARGET_64BIT) return 1; if (!TARGET_PARTIAL_REG_STALL) return 1; @@ -26869,7 +26934,7 @@ x86_extended_QIreg_mentioned_p (rtx insn) extract_insn_cached (insn); for (i = 0; i < recog_data.n_operands; i++) if (REG_P (recog_data.operand[i]) - && REGNO (recog_data.operand[i]) >= 4) + && REGNO (recog_data.operand[i]) > BX_REG) return true; return false; } @@ -29419,14 +29484,11 @@ x86_builtin_vectorization_cost (bool runtime_test) tree ix86_fn_abi_va_list (tree fndecl) { - int abi; - if (!TARGET_64BIT) return va_list_type_node; gcc_assert (fndecl != NULL_TREE); - abi = ix86_function_abi ((const_tree) fndecl); - if (abi == MS_ABI) + if (ix86_function_abi ((const_tree) fndecl) == MS_ABI) return ms_va_list_type_node; else return sysv_va_list_type_node; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 48ee1ff8569..89e26f63dde 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -465,7 +465,10 @@ enum calling_abi MS_ABI = 1 }; -/* The default abi form used by target. */ +/* The abi used by target. */ +extern enum calling_abi ix86_abi; + +/* The default abi used by target. */ #define DEFAULT_ABI SYSV_ABI /* Subtargets may reset this to 1 in order to enable 96-bit long double @@ -667,7 +670,7 @@ enum target_cpu_default /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY \ - (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD) + (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) /* Stack boundary of the main function guaranteed by OS. */ #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) @@ -805,6 +808,19 @@ enum target_cpu_default #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ ix86_local_alignment ((TYPE), (MODE), (ALIGN)) +/* If defined, a C expression to compute the alignment for a local + variable DECL. + + If this macro is not defined, then + LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. + + One use of this macro is to increase alignment of medium-size + data to make it all fit in fewer cache lines. */ + +#define LOCAL_DECL_ALIGNMENT(DECL) \ + ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) + + /* If defined, a C expression that gives the alignment boundary, in bits, of an argument with the specified mode and type. If it is not defined, `PARM_BOUNDARY' is used for all arguments. */ @@ -873,7 +889,7 @@ enum target_cpu_default 1, 1, 1, 1, 1, \ /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ -/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ +/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 2, 2, 2, 2, 2, 2, 2, 2, \ @@ -901,7 +917,7 @@ enum target_cpu_default 1, 1, 1, 1, 1, \ /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ -/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ +/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1, 1, 1, 1, 2, 2, 2, 2, \ @@ -947,47 +963,32 @@ do { \ } \ j = PIC_OFFSET_TABLE_REGNUM; \ if (j != INVALID_REGNUM) \ - { \ - fixed_regs[j] = 1; \ - call_used_regs[j] = 1; \ - } \ + fixed_regs[j] = call_used_regs[j] = 1; \ if (TARGET_64BIT \ - && ((cfun && cfun->machine->call_abi == MS_ABI) \ - || (!cfun && DEFAULT_ABI == MS_ABI))) \ + && ((cfun && cfun->machine->call_abi == MS_ABI) \ + || (!cfun && ix86_abi == MS_ABI))) \ { \ - int i; \ - call_used_regs[4 /*RSI*/] = 0; \ - call_used_regs[5 /*RDI*/] = 0; \ - for (i = 0; i < 8; i++) \ - call_used_regs[45+i] = 0; \ - call_used_regs[27] = call_used_regs[28] = 0; \ + call_used_regs[SI_REG] = 0; \ + call_used_regs[DI_REG] = 0; \ + call_used_regs[XMM6_REG] = 0; \ + call_used_regs[XMM7_REG] = 0; \ + for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ + call_used_regs[i] = 0; \ } \ if (! TARGET_MMX) \ - { \ - int i; \ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ - if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ - fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ - } \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ + if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ + fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ if (! TARGET_SSE) \ - { \ - int i; \ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ - if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ - fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ - } \ - if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ - { \ - int i; \ - HARD_REG_SET x; \ - COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ - if (TEST_HARD_REG_BIT (x, i)) \ - fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ - } \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ + if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ + fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ + if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387)) \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ + if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i)) \ + fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ if (! TARGET_64BIT) \ { \ - int i; \ for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ reg_names[i] = ""; \ for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ @@ -1102,7 +1103,7 @@ do { \ : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ - : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ + : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \ : (MODE)) /* Specify the registers used for certain standard purposes. @@ -1339,7 +1340,7 @@ enum reg_class #define SMALL_REGISTER_CLASSES 1 -#define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4) +#define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) #define GENERAL_REGNO_P(N) \ ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) @@ -1537,7 +1538,8 @@ enum reg_class prologue and apilogue. This is not possible without ACCUMULATE_OUTGOING_ARGS. */ -#define ACCUMULATE_OUTGOING_ARGS (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI) +#define ACCUMULATE_OUTGOING_ARGS \ + (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI) /* If defined, a C expression whose value is nonzero when we want to use PUSH instructions to pass outgoing arguments. */ @@ -1624,7 +1626,7 @@ typedef struct ix86_args { int maybe_vaarg; /* true for calls to possibly vardic fncts. */ int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should be passed in SSE registers. Otherwise 0. */ - int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise + enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise MS_ABI for ms abi. */ } CUMULATIVE_ARGS; @@ -2443,7 +2445,7 @@ struct machine_function GTY(()) int tls_descriptor_call_expanded_p; /* This value is used for amd64 targets and specifies the current abi to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ - int call_abi; + enum calling_abi call_abi; }; #define ix86_stack_locals (cfun->machine->stack_locals) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9c38ee848cd..9592f91ff7e 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -264,6 +264,14 @@ (DI_REG 5) (BP_REG 6) (SP_REG 7) + (ST0_REG 8) + (ST1_REG 9) + (ST2_REG 10) + (ST3_REG 11) + (ST4_REG 12) + (ST5_REG 13) + (ST6_REG 14) + (ST7_REG 15) (FLAGS_REG 17) (FPSR_REG 18) (FPCR_REG 19) @@ -275,6 +283,16 @@ (XMM5_REG 26) (XMM6_REG 27) (XMM7_REG 28) + (MM0_REG 29) + (MM1_REG 30) + (MM2_REG 31) + (MM3_REG 32) + (MM4_REG 33) + (MM5_REG 34) + (MM6_REG 35) + (MM7_REG 36) + (R8_REG 37) + (R9_REG 38) (R10_REG 39) (R11_REG 40) (R13_REG 42) @@ -4440,35 +4458,33 @@ (set_attr "mode" "SF")]) (define_insn "*truncdfsf_mixed" - [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y2") + [(set (match_operand:SF 0 "nonimmediate_operand" "=m,Y2 ,?f,?x,?*r") (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Y2m"))) - (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))] + (match_operand:DF 1 "nonimmediate_operand" "f ,Y2m,f ,f ,f"))) + (clobber (match_operand:SF 2 "memory_operand" "=X,X ,m ,m ,m"))] "TARGET_MIX_SSE_I387" { switch (which_alternative) { case 0: return output_387_reg_move (insn, operands); - case 1: - return "#"; - case 2: return "%vcvtsd2ss\t{%1, %d0|%d0, %1}"; + default: - gcc_unreachable (); + return "#"; } } - [(set_attr "type" "fmov,multi,ssecvt") - (set_attr "unit" "*,i387,*") - (set_attr "prefix" "orig,orig,maybe_vex") + [(set_attr "type" "fmov,ssecvt,multi,multi,multi") + (set_attr "unit" "*,*,i387,i387,i387") + (set_attr "prefix" "orig,maybe_vex,orig,orig,orig") (set_attr "mode" "SF")]) (define_insn "*truncdfsf_i387" - [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r") + [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r") (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "f,f"))) - (clobber (match_operand:SF 2 "memory_operand" "=X,m"))] + (match_operand:DF 1 "nonimmediate_operand" "f ,f ,f ,f"))) + (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))] "TARGET_80387" { switch (which_alternative) @@ -4476,14 +4492,12 @@ case 0: return output_387_reg_move (insn, operands); - case 1: - return "#"; default: - gcc_unreachable (); + return "#"; } } - [(set_attr "type" "fmov,multi") - (set_attr "unit" "*,i387") + [(set_attr "type" "fmov,multi,multi,multi") + (set_attr "unit" "*,i387,i387,i387") (set_attr "mode" "SF")]) (define_insn "*truncdfsf2_i387_1" @@ -4534,31 +4548,31 @@ }) (define_insn "*truncxfsf2_mixed" - [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r") + [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r") (float_truncate:SF - (match_operand:XF 1 "register_operand" "f,f"))) - (clobber (match_operand:SF 2 "memory_operand" "=X,m"))] + (match_operand:XF 1 "register_operand" "f ,f ,f ,f"))) + (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))] "TARGET_80387" { gcc_assert (!which_alternative); return output_387_reg_move (insn, operands); } - [(set_attr "type" "fmov,multi") - (set_attr "unit" "*,i387") + [(set_attr "type" "fmov,multi,multi,multi") + (set_attr "unit" "*,i387,i387,i387") (set_attr "mode" "SF")]) (define_insn "*truncxfdf2_mixed" - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fY2*r") + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?Y2,?*r") (float_truncate:DF - (match_operand:XF 1 "register_operand" "f,f"))) - (clobber (match_operand:DF 2 "memory_operand" "=X,m"))] + (match_operand:XF 1 "register_operand" "f ,f ,f ,f"))) + (clobber (match_operand:DF 2 "memory_operand" "=X,m ,m ,m"))] "TARGET_80387" { gcc_assert (!which_alternative); return output_387_reg_move (insn, operands); } - [(set_attr "type" "fmov,multi") - (set_attr "unit" "*,i387") + [(set_attr "type" "fmov,multi,multi,multi") + (set_attr "unit" "*,i387,i387,i387") (set_attr "mode" "DF")]) (define_insn "truncxf<mode>2_i387_noop" @@ -15076,16 +15090,16 @@ [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) (match_operand 1 "" "")) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) - (clobber (reg:TI 27)) - (clobber (reg:TI 28)) - (clobber (reg:TI 45)) - (clobber (reg:TI 46)) - (clobber (reg:TI 47)) - (clobber (reg:TI 48)) - (clobber (reg:TI 49)) - (clobber (reg:TI 50)) - (clobber (reg:TI 51)) - (clobber (reg:TI 52)) + (clobber (reg:TI XMM6_REG)) + (clobber (reg:TI XMM7_REG)) + (clobber (reg:TI XMM8_REG)) + (clobber (reg:TI XMM9_REG)) + (clobber (reg:TI XMM10_REG)) + (clobber (reg:TI XMM11_REG)) + (clobber (reg:TI XMM12_REG)) + (clobber (reg:TI XMM13_REG)) + (clobber (reg:TI XMM14_REG)) + (clobber (reg:TI XMM15_REG)) (clobber (reg:DI SI_REG)) (clobber (reg:DI DI_REG))] "!SIBLING_CALL_P (insn) && TARGET_64BIT" @@ -15172,13 +15186,19 @@ /* In order to give reg-stack an easier job in validating two coprocessor registers as containing a possible return value, simply pretend the untyped call returns a complex long double - value. */ + value. + + We can't use SSE_REGPARM_MAX here since callee is unprototyped + and should have the default ABI. */ ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL), operands[0], const0_rtx, - GEN_INT ((DEFAULT_ABI == SYSV_ABI ? X86_64_SSE_REGPARM_MAX - : X64_SSE_REGPARM_MAX) + GEN_INT ((TARGET_64BIT + ? (ix86_abi == SYSV_ABI + ? X86_64_SSE_REGPARM_MAX + : X64_SSE_REGPARM_MAX) + : X86_32_SSE_REGPARM_MAX) - 1), NULL, 0); @@ -20834,7 +20854,7 @@ [(match_dup 0) (match_operand:SI 2 "memory_operand" "")])) (clobber (reg:CC FLAGS_REG))])] - "operands[0] != operands[1] + "REGNO (operands[0]) != REGNO (operands[1]) && GENERAL_REGNO_P (REGNO (operands[0])) && GENERAL_REGNO_P (REGNO (operands[1]))" [(set (match_dup 0) (match_dup 4)) @@ -20850,7 +20870,7 @@ (match_operator 3 "commutative_operator" [(match_dup 0) (match_operand 2 "memory_operand" "")]))] - "operands[0] != operands[1] + "REGNO (operands[0]) != REGNO (operands[1]) && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1])) || (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))" [(set (match_dup 0) (match_dup 2)) @@ -21544,16 +21564,16 @@ (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" "")) (match_operand:DI 2 "const_int_operand" ""))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) - (clobber (reg:TI 27)) - (clobber (reg:TI 28)) - (clobber (reg:TI 45)) - (clobber (reg:TI 46)) - (clobber (reg:TI 47)) - (clobber (reg:TI 48)) - (clobber (reg:TI 49)) - (clobber (reg:TI 50)) - (clobber (reg:TI 51)) - (clobber (reg:TI 52)) + (clobber (reg:TI XMM6_REG)) + (clobber (reg:TI XMM7_REG)) + (clobber (reg:TI XMM8_REG)) + (clobber (reg:TI XMM9_REG)) + (clobber (reg:TI XMM10_REG)) + (clobber (reg:TI XMM11_REG)) + (clobber (reg:TI XMM12_REG)) + (clobber (reg:TI XMM13_REG)) + (clobber (reg:TI XMM14_REG)) + (clobber (reg:TI XMM15_REG)) (clobber (reg:DI SI_REG)) (clobber (reg:DI DI_REG))] "!SIBLING_CALL_P (insn) && TARGET_64BIT" diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 853059081d2..6fd218f8ede 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -228,6 +228,10 @@ mtune= Target RejectNegative Joined Var(ix86_tune_string) Schedule code for given CPU +mabi= +Target RejectNegative Joined Var(ix86_abi_string) +Generate code that conforms to the given ABI + mveclibabi= Target RejectNegative Joined Var(ix86_veclibabi_string) Vector library ABI to use diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h index f3fbe8c5865..746d7d105da 100644 --- a/gcc/config/i386/mingw32.h +++ b/gcc/config/i386/mingw32.h @@ -38,7 +38,7 @@ along with GCC; see the file COPYING3. If not see builtin_define_std ("WINNT"); \ builtin_define_with_int_value ("_INTEGRAL_MAX_BITS", \ TYPE_PRECISION (intmax_type_node));\ - if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) \ + if (TARGET_64BIT && ix86_abi == MS_ABI) \ { \ builtin_define ("__MINGW64__"); \ builtin_define_std ("WIN64"); \ diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 870fc8855e7..5184b1d7f5c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1583,22 +1583,22 @@ (define_insn "mmx_emms" [(unspec_volatile [(const_int 0)] UNSPECV_EMMS) - (clobber (reg:XF 8)) - (clobber (reg:XF 9)) - (clobber (reg:XF 10)) - (clobber (reg:XF 11)) - (clobber (reg:XF 12)) - (clobber (reg:XF 13)) - (clobber (reg:XF 14)) - (clobber (reg:XF 15)) - (clobber (reg:DI 29)) - (clobber (reg:DI 30)) - (clobber (reg:DI 31)) - (clobber (reg:DI 32)) - (clobber (reg:DI 33)) - (clobber (reg:DI 34)) - (clobber (reg:DI 35)) - (clobber (reg:DI 36))] + (clobber (reg:XF ST0_REG)) + (clobber (reg:XF ST1_REG)) + (clobber (reg:XF ST2_REG)) + (clobber (reg:XF ST3_REG)) + (clobber (reg:XF ST4_REG)) + (clobber (reg:XF ST5_REG)) + (clobber (reg:XF ST6_REG)) + (clobber (reg:XF ST7_REG)) + (clobber (reg:DI MM0_REG)) + (clobber (reg:DI MM1_REG)) + (clobber (reg:DI MM2_REG)) + (clobber (reg:DI MM3_REG)) + (clobber (reg:DI MM4_REG)) + (clobber (reg:DI MM5_REG)) + (clobber (reg:DI MM6_REG)) + (clobber (reg:DI MM7_REG))] "TARGET_MMX" "emms" [(set_attr "type" "mmx") @@ -1606,22 +1606,22 @@ (define_insn "mmx_femms" [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS) - (clobber (reg:XF 8)) - (clobber (reg:XF 9)) - (clobber (reg:XF 10)) - (clobber (reg:XF 11)) - (clobber (reg:XF 12)) - (clobber (reg:XF 13)) - (clobber (reg:XF 14)) - (clobber (reg:XF 15)) - (clobber (reg:DI 29)) - (clobber (reg:DI 30)) - (clobber (reg:DI 31)) - (clobber (reg:DI 32)) - (clobber (reg:DI 33)) - (clobber (reg:DI 34)) - (clobber (reg:DI 35)) - (clobber (reg:DI 36))] + (clobber (reg:XF ST0_REG)) + (clobber (reg:XF ST1_REG)) + (clobber (reg:XF ST2_REG)) + (clobber (reg:XF ST3_REG)) + (clobber (reg:XF ST4_REG)) + (clobber (reg:XF ST5_REG)) + (clobber (reg:XF ST6_REG)) + (clobber (reg:XF ST7_REG)) + (clobber (reg:DI MM0_REG)) + (clobber (reg:DI MM1_REG)) + (clobber (reg:DI MM2_REG)) + (clobber (reg:DI MM3_REG)) + (clobber (reg:DI MM4_REG)) + (clobber (reg:DI MM5_REG)) + (clobber (reg:DI MM6_REG)) + (clobber (reg:DI MM7_REG))] "TARGET_3DNOW" "femms" [(set_attr "type" "mmx") diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index b2bef6470be..f1c71033333 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -887,6 +887,34 @@ return parts.disp != NULL_RTX; }) +;; Returns 1 if OP is memory operand which will need zero or +;; one register at most, not counting stack pointer or frame pointer. +(define_predicate "cmpxchg8b_pic_memory_operand" + (match_operand 0 "memory_operand") +{ + struct ix86_address parts; + int ok; + + ok = ix86_decompose_address (XEXP (op, 0), &parts); + gcc_assert (ok); + if (parts.base == NULL_RTX + || parts.base == arg_pointer_rtx + || parts.base == frame_pointer_rtx + || parts.base == hard_frame_pointer_rtx + || parts.base == stack_pointer_rtx) + return 1; + + if (parts.index == NULL_RTX + || parts.index == arg_pointer_rtx + || parts.index == frame_pointer_rtx + || parts.index == hard_frame_pointer_rtx + || parts.index == stack_pointer_rtx) + return 1; + + return 0; +}) + + ;; Returns 1 if OP is memory operand that cannot be represented ;; by the modRM array. (define_predicate "long_memory_operand" diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a54133378b5..e6d1fd14b2d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1101,7 +1101,7 @@ (match_operand:V8SF 1 "register_operand" "x") (match_operand:V8SF 2 "nonimmediate_operand" "xm")) (minus:V8SF (match_dup 1) (match_dup 2)) - (const_int 85)))] + (const_int 170)))] "TARGET_AVX" "vaddsubps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") @@ -1115,7 +1115,7 @@ (match_operand:V4DF 1 "register_operand" "x") (match_operand:V4DF 2 "nonimmediate_operand" "xm")) (minus:V4DF (match_dup 1) (match_dup 2)) - (const_int 5)))] + (const_int 10)))] "TARGET_AVX" "vaddsubpd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") @@ -1129,7 +1129,7 @@ (match_operand:V4SF 1 "register_operand" "x") (match_operand:V4SF 2 "nonimmediate_operand" "xm")) (minus:V4SF (match_dup 1) (match_dup 2)) - (const_int 5)))] + (const_int 10)))] "TARGET_AVX" "vaddsubps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") @@ -1143,7 +1143,7 @@ (match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 2 "nonimmediate_operand" "xm")) (minus:V4SF (match_dup 1) (match_dup 2)) - (const_int 5)))] + (const_int 10)))] "TARGET_SSE3" "addsubps\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") @@ -1157,7 +1157,7 @@ (match_operand:V2DF 1 "register_operand" "x") (match_operand:V2DF 2 "nonimmediate_operand" "xm")) (minus:V2DF (match_dup 1) (match_dup 2)) - (const_int 1)))] + (const_int 2)))] "TARGET_AVX" "vaddsubpd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") @@ -1171,7 +1171,7 @@ (match_operand:V2DF 1 "register_operand" "0") (match_operand:V2DF 2 "nonimmediate_operand" "xm")) (minus:V2DF (match_dup 1) (match_dup 2)) - (const_int 1)))] + (const_int 2)))] "TARGET_SSE3" "addsubpd\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") @@ -3059,10 +3059,10 @@ (vec_concat:V16SF (match_operand:V8SF 1 "register_operand" "x") (match_operand:V8SF 2 "nonimmediate_operand" "xm")) - (parallel [(const_int 2) (const_int 6) - (const_int 3) (const_int 7) - (const_int 10) (const_int 14) - (const_int 11) (const_int 15)])))] + (parallel [(const_int 2) (const_int 10) + (const_int 3) (const_int 11) + (const_int 6) (const_int 14) + (const_int 7) (const_int 15)])))] "TARGET_AVX" "vunpckhps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") @@ -3102,10 +3102,10 @@ (vec_concat:V16SF (match_operand:V8SF 1 "register_operand" "x") (match_operand:V8SF 2 "nonimmediate_operand" "xm")) - (parallel [(const_int 0) (const_int 4) - (const_int 1) (const_int 5) - (const_int 8) (const_int 12) - (const_int 9) (const_int 13)])))] + (parallel [(const_int 0) (const_int 8) + (const_int 1) (const_int 9) + (const_int 4) (const_int 12) + (const_int 5) (const_int 13)])))] "TARGET_AVX" "vunpcklps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") @@ -3902,7 +3902,7 @@ (vec_concat:V8DF (match_operand:V4DF 1 "register_operand" "x") (match_operand:V4DF 2 "nonimmediate_operand" "xm")) - (parallel [(const_int 2) (const_int 6) + (parallel [(const_int 1) (const_int 5) (const_int 3) (const_int 7)])))] "TARGET_AVX" "vunpckhpd\t{%2, %1, %0|%0, %1, %2}" @@ -4023,7 +4023,7 @@ (match_operand:V4DF 1 "register_operand" "x") (match_operand:V4DF 2 "nonimmediate_operand" "xm")) (parallel [(const_int 0) (const_int 4) - (const_int 1) (const_int 5)])))] + (const_int 2) (const_int 6)])))] "TARGET_AVX" "vunpcklpd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index e2675744b01..05aad00ba94 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for i386 synchronization instructions. -;; Copyright (C) 2005, 2006, 2007, 2008 +;; Copyright (C) 2005, 2006, 2007, 2008, 2009 ;; Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -82,8 +82,15 @@ low = force_reg (hmode, low); high = force_reg (hmode, high); if (<MODE>mode == DImode) - emit_insn (gen_sync_double_compare_and_swapdi - (operands[0], operands[1], operands[2], low, high)); + { + if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode)) + operands[1] = replace_equiv_address (operands[1], + force_reg (Pmode, + XEXP (operands[1], + 0))); + emit_insn (gen_sync_double_compare_and_swapdi + (operands[0], operands[1], operands[2], low, high)); + } else if (<MODE>mode == TImode) emit_insn (gen_sync_double_compare_and_swapti (operands[0], operands[1], operands[2], low, high)); @@ -131,7 +138,7 @@ ;; are just esi and edi. (define_insn "*sync_double_compare_and_swapdi_pic" [(set (match_operand:DI 0 "register_operand" "=A") - (match_operand:DI 1 "memory_operand" "+m")) + (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m")) (set (match_dup 1) (unspec_volatile:DI [(match_dup 1) @@ -173,8 +180,15 @@ low = force_reg (hmode, low); high = force_reg (hmode, high); if (<MODE>mode == DImode) - emit_insn (gen_sync_double_compare_and_swap_ccdi - (operands[0], operands[1], operands[2], low, high)); + { + if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode)) + operands[1] = replace_equiv_address (operands[1], + force_reg (Pmode, + XEXP (operands[1], + 0))); + emit_insn (gen_sync_double_compare_and_swap_ccdi + (operands[0], operands[1], operands[2], low, high)); + } else if (<MODE>mode == TImode) emit_insn (gen_sync_double_compare_and_swap_ccti (operands[0], operands[1], operands[2], low, high)); @@ -224,7 +238,7 @@ ;; operand 3. (define_insn "*sync_double_compare_and_swap_ccdi_pic" [(set (match_operand:DI 0 "register_operand" "=A") - (match_operand:DI 1 "memory_operand" "+m")) + (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m")) (set (match_dup 1) (unspec_volatile:DI [(match_dup 1) diff --git a/gcc/config/i386/x-mingw32 b/gcc/config/i386/x-mingw32 index 7ae61522a56..0af4f5c3f41 100644 --- a/gcc/config/i386/x-mingw32 +++ b/gcc/config/i386/x-mingw32 @@ -8,6 +8,6 @@ local_includedir=$(libsubdir)/$(unlibsubdir)/..`echo $(exec_prefix) | sed -e 's| WERROR_FLAGS += -Wno-format host-mingw32.o : $(srcdir)/config/i386/host-mingw32.c $(CONFIG_H) $(SYSTEM_H) \ - coretypes.h hosthooks.h hosthooks-def.h toplev.h diagnostic.h $(HOOKS_H) + coretypes.h hosthooks.h hosthooks-def.h toplev.h $(DIAGNOSTIC_H) $(HOOKS_H) $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/i386/host-mingw32.c diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 420a8e46327..da96fce6d4f 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -7274,6 +7274,8 @@ ia64_set_sched_flags (spec_info_t spec_info) spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH; } } + else + spec_info->mask = 0; } /* If INSN is an appropriate load return its mode. diff --git a/gcc/config/ia64/sync.md b/gcc/config/ia64/sync.md index e356081202e..b40e208b6a0 100644 --- a/gcc/config/ia64/sync.md +++ b/gcc/config/ia64/sync.md @@ -151,10 +151,10 @@ (unspec:I124MODE [(match_dup 1) (match_operand:DI 2 "ar_ccv_reg_operand" "") - (match_operand:I124MODE 3 "gr_register_operand" "r")] + (match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")] UNSPEC_CMPXCHG_ACQ))] "" - "cmpxchg<modesuffix>.rel %0 = %1, %3, %2" + "cmpxchg<modesuffix>.rel %0 = %1, %r3, %2" [(set_attr "itanium_class" "sem")]) (define_insn "cmpxchg_rel_di" @@ -163,19 +163,19 @@ (set (match_dup 1) (unspec:DI [(match_dup 1) (match_operand:DI 2 "ar_ccv_reg_operand" "") - (match_operand:DI 3 "gr_register_operand" "r")] + (match_operand:DI 3 "gr_reg_or_0_operand" "rO")] UNSPEC_CMPXCHG_ACQ))] "" - "cmpxchg8.rel %0 = %1, %3, %2" + "cmpxchg8.rel %0 = %1, %r3, %2" [(set_attr "itanium_class" "sem")]) (define_insn "sync_lock_test_and_set<mode>" [(set (match_operand:IMODE 0 "gr_register_operand" "=r") (match_operand:IMODE 1 "not_postinc_memory_operand" "+S")) (set (match_dup 1) - (match_operand:IMODE 2 "gr_register_operand" "r"))] + (match_operand:IMODE 2 "gr_reg_or_0_operand" "rO"))] "" - "xchg<modesuffix> %0 = %1, %2" + "xchg<modesuffix> %0 = %1, %r2" [(set_attr "itanium_class" "sem")]) (define_expand "sync_lock_release<mode>" diff --git a/gcc/config/libgloss.h b/gcc/config/libgloss.h deleted file mode 100644 index 2e4553b3b42..00000000000 --- a/gcc/config/libgloss.h +++ /dev/null @@ -1,37 +0,0 @@ -/* libgloss.h -- operating system specific defines to be used when - targeting GCC for Libgloss supported targets. - Copyright (C) 1996, 2004, 2007 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -/* This file should not be used for ELF targets, as this definition of - STARTFILE_SPEC is all wrong. */ - -/* The libgloss standard for crt0.s has the name based on the command line - option. */ -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "%{!shared:%{pg:pgcrt0%O%s}%{!pg:%{p:pcrt0%O%s}%{!p:crt0%O%s}}}" - -/* This file used to force LINK_SPEC to be the null string, but that is not - correct. LINK_SPEC is used to pass machine specific arguments to the - linker and hence cannot be redefined here. LINK_SPEC is never used to - specify startup files or libraries, so it should never conflict with - libgloss. */ - -/* Don't set the target flags, this is done by the linker script */ -#undef LIB_SPEC -#define LIB_SPEC "" diff --git a/gcc/config/m32r/t-linux b/gcc/config/m32r/t-linux index 311c4e7ef9b..1ccdcc93473 100644 --- a/gcc/config/m32r/t-linux +++ b/gcc/config/m32r/t-linux @@ -27,10 +27,6 @@ dp-bit.c: $(srcdir)/config/fp-bit.c CRTSTUFF_T_CFLAGS_S = -fPIC - -# Don't run fixproto -STMP_FIXPROTO = - # Don't install "assert.h" in gcc. We use the one in glibc. INSTALL_ASSERT_H = diff --git a/gcc/config/m68k/coff.h b/gcc/config/m68k/coff.h deleted file mode 100644 index cb548abd020..00000000000 --- a/gcc/config/m68k/coff.h +++ /dev/null @@ -1,88 +0,0 @@ -/* Definitions of target machine for GNU compiler. - m68k series COFF object files and debugging, version. - Copyright (C) 1994, 1996, 1997, 2000, 2002, 2003, 2004, 2007 - Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -/* This file is included after m68k.h by CPU COFF specific files. It - is not a complete target itself. */ - -/* Used in m68k.c to include required support code. */ - -#define M68K_TARGET_COFF 1 - -/* Generate sdb debugging information. */ - -#define SDB_DEBUGGING_INFO 1 - -/* COFF symbols don't start with an underscore. */ - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" - -/* Use a prefix for local labels, just to be on the save side. */ - -#undef LOCAL_LABEL_PREFIX -#define LOCAL_LABEL_PREFIX "." - -/* Use a register prefix to avoid clashes with external symbols (classic - example: `extern char PC;' in termcap). */ - -#undef REGISTER_PREFIX -#define REGISTER_PREFIX "%" - -/* config/m68k.md has an explicit reference to the program counter, - prefix this by the register prefix. */ - -#define ASM_RETURN_CASE_JUMP \ - do { \ - if (TARGET_COLDFIRE) \ - { \ - if (ADDRESS_REG_P (operands[0])) \ - return "jmp %%pc@(2,%0:l)"; \ - else \ - return "ext%.l %0\n\tjmp %%pc@(2,%0:l)"; \ - } \ - else \ - return "jmp %%pc@(2,%0:w)"; \ - } while (0) - -#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true - -/* If defined, a C expression whose value is a string containing the - assembler operation to identify the following data as uninitialized global - data. */ - -#define BSS_SECTION_ASM_OP "\t.section\t.bss" - -/* A C statement (sans semicolon) to output to the stdio stream - FILE the assembler definition of uninitialized global DECL named - NAME whose size is SIZE bytes and alignment is ALIGN bytes. - Try to use asm_output_aligned_bss to implement this macro. */ - -#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ - asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) - -/* Switch into a generic section. */ -#undef TARGET_ASM_NAMED_SECTION -#define TARGET_ASM_NAMED_SECTION m68k_coff_asm_named_section - -/* Don't assume anything about startfiles. */ - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "" diff --git a/gcc/config/m68k/m68k-aout.h b/gcc/config/m68k/m68k-aout.h deleted file mode 100644 index df2cdf7a44a..00000000000 --- a/gcc/config/m68k/m68k-aout.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Definitions of target machine for GNU compiler. "naked" 68020, - a.out object files and debugging, version. - Copyright (C) 1994, 1996, 2003, 2007 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -#define DBX_DEBUGGING_INFO 1 -#undef SDB_DEBUGGING_INFO - -/* If defined, a C expression whose value is a string containing the - assembler operation to identify the following data as uninitialized global - data. */ -#define BSS_SECTION_ASM_OP "\t.bss" - -/* A C statement (sans semicolon) to output to the stdio stream - FILE the assembler definition of uninitialized global DECL named - NAME whose size is SIZE bytes. The variable ROUNDED - is the size rounded up to whatever alignment the caller wants. - Try to use asm_output_bss to implement this macro. */ -/* a.out files typically can't handle arbitrary variable alignments so - define ASM_OUTPUT_BSS instead of ASM_OUTPUT_ALIGNED_BSS. */ -#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ROUNDED) \ - asm_output_bss ((FILE), (DECL), (NAME), (SIZE), (ROUNDED)) diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 2f931c6be42..bccb8348a55 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -1,6 +1,6 @@ /* Subroutines for insn-output.c for Motorola 68000 family. Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2003, 2004, 2005, 2006, 2007, 2008 + 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. This file is part of GCC. @@ -134,9 +134,6 @@ static int m68k_sched_first_cycle_multipass_dfa_lookahead (void); static bool m68k_handle_option (size_t, const char *, int); static rtx find_addr_reg (rtx); static const char *singlemove_string (rtx *); -#ifdef M68K_TARGET_COFF -static void m68k_coff_asm_named_section (const char *, unsigned int, tree); -#endif /* M68K_TARGET_COFF */ static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); static rtx m68k_struct_value_rtx (tree, int); @@ -4336,26 +4333,6 @@ output_sibcall (rtx x) return "jmp %a0"; } -#ifdef M68K_TARGET_COFF - -/* Output assembly to switch to section NAME with attribute FLAGS. */ - -static void -m68k_coff_asm_named_section (const char *name, unsigned int flags, - tree decl ATTRIBUTE_UNUSED) -{ - char flagchar; - - if (flags & SECTION_WRITE) - flagchar = 'd'; - else - flagchar = 'x'; - - fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar); -} - -#endif /* M68K_TARGET_COFF */ - static void m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, diff --git a/gcc/config/m68k/t-rtems b/gcc/config/m68k/t-rtems index 2b0750f0f05..0997afebc94 100644 --- a/gcc/config/m68k/t-rtems +++ b/gcc/config/m68k/t-rtems @@ -4,5 +4,6 @@ M68K_MLIB_CPU += && (match(MLIB, "^68") \ || MLIB == "5206" \ || MLIB == "5208" \ || MLIB == "5307" \ + || MLIB == "5329" \ || MLIB == "5407" \ || MLIB == "5475") diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index 6e26d5e7b35..278c1b248ee 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -50,8 +50,6 @@ } \ while (0) -/* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC - %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}. */ #undef CPP_SPEC #define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}" @@ -67,7 +65,6 @@ #define TARGET_DEFAULT \ (MASK_HARDLIT \ - | MASK_8ALIGN \ | MASK_DIV \ | MASK_RELAX_IMM \ | MASK_M340 \ diff --git a/gcc/config/mcore/mcore.opt b/gcc/config/mcore/mcore.opt index 1eae8901e6e..c445237301a 100644 --- a/gcc/config/mcore/mcore.opt +++ b/gcc/config/mcore/mcore.opt @@ -1,6 +1,6 @@ ; Options for the Motorola MCore port of the compiler. -; Copyright (C) 2005, 2007 Free Software Foundation, Inc. +; Copyright (C) 2005, 2007, 2009 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -26,18 +26,10 @@ m340 Target RejectNegative Report Mask(M340) Generate code for the M*Core M340 -m4align -Target RejectNegative Report InverseMask(8ALIGN) -Set maximum alignment to 4 - m4byte-functions Target Report Mask(OVERALIGN_FUNC) Force functions to be aligned to a 4 byte boundary -m8align -Target RejectNegative Report Mask(8ALIGN) -Set maximum alignment to 8 - mbig-endian Target RejectNegative Report InverseMask(LITTLE_END) Generate big-endian code @@ -60,7 +52,8 @@ Generate little-endian code ; Not used by the compiler proper. mno-lsim -Target RejectNegative Undocumented +Target RejectNegative +Assume that run-time support has been provided, so omit -lsim from the linker command line mrelax-immediates Target Report Mask(RELAX_IMM) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 64da58a7f12..f153d137411 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -7782,7 +7782,7 @@ mips_mdebug_abi_name (void) case ABI_N32: return "abiN32"; case ABI_64: - return "abiN64"; + return "abi64"; case ABI_EABI: return TARGET_64BIT ? "eabi64" : "eabi32"; default: diff --git a/gcc/config/mips/t-iris b/gcc/config/mips/t-iris index 4a7143f9ddd..a200cf8c19c 100644 --- a/gcc/config/mips/t-iris +++ b/gcc/config/mips/t-iris @@ -1,6 +1,3 @@ -# Find all of the declarations from the header files -FIXPROTO_DEFINES = -D__EXTENSIONS__ -D_SGI_SOURCE -D_LANGUAGE_C_PLUS_PLUS - $(T)irix-crti.o: $(srcdir)/config/mips/irix-crti.asm $(GCC_PASSES) $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -c -o $@ -x assembler-with-cpp $< diff --git a/gcc/config/pa/t-pa-hpux b/gcc/config/pa/t-pa-hpux index 1c62f4ee237..63eab636200 100644 --- a/gcc/config/pa/t-pa-hpux +++ b/gcc/config/pa/t-pa-hpux @@ -1,6 +1,3 @@ -# So putenv and other functions get seen by fixproto. -FIXPROTO_DEFINES = -D_HPUX_SOURCE -D_HIUX_SOURCE - lib2funcs.asm: $(srcdir)/config/pa/lib2funcs.asm rm -f lib2funcs.asm cp $(srcdir)/config/pa/lib2funcs.asm . diff --git a/gcc/config/pdp11/2bsd.h b/gcc/config/pdp11/2bsd.h deleted file mode 100644 index c96065a6490..00000000000 --- a/gcc/config/pdp11/2bsd.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Definitions of target machine for GNU compiler, for a PDP with 2BSD - Copyright (C) 1995, 1996, 1999, 2000, 2007 Free Software Foundation, Inc. - Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -#define TWO_BSD - -/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, - the stack pointer does not matter. The value is tested only in - functions that have frame pointers. - No definition is equivalent to always zero. */ - -#undef EXIT_IGNORE_STACK -#define EXIT_IGNORE_STACK 1 - -#undef INITIAL_FRAME_POINTER_OFFSET -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \ -{ \ - int offset; \ - offset = get_frame_size(); \ - offset = (offset <= 2)? 0: (offset -2); \ - (DEPTH_VAR) = offset+10; \ -} - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms - may be accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. - */ - -#undef FRAME_POINTER_REQUIRED -#define FRAME_POINTER_REQUIRED 1 - -/* Offset within stack frame to start allocating local variables at. - If FRAME_GROWS_DOWNWARD, this is the offset to the END of the - first local allocated. Otherwise, it is the offset to the BEGINNING - of the first local allocated. */ -#undef STARTING_FRAME_OFFSET -#define STARTING_FRAME_OFFSET -8 - - -#undef ASM_DECLARE_FUNCTION_NAME -#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ -do { \ -ASM_OUTPUT_LABEL (STREAM, NAME); \ -fprintf (STREAM, "~~%s:\n", NAME); \ -} while (0) - -#undef TARGET_UNIX_ASM_DEFAULT -#define TARGET_UNIX_ASM_DEFAULT MASK_UNIX_ASM diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index f6171356a12..6e8941d75e9 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -1,6 +1,6 @@ /* Subroutines for gcc2 for pdp11. Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2004, 2005, - 2006, 2007, 2008 Free Software Foundation, Inc. + 2006, 2007, 2008, 2009 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. @@ -241,23 +241,6 @@ expand_shift_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) knowing which registers should not be saved even if used. */ -#ifdef TWO_BSD - -static void -pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size) -{ - fprintf (stream, "\tjsr r5, csv\n"); - if (size) - { - fprintf (stream, "\t/*abuse empty parameter slot for locals!*/\n"); - if (size > 2) - asm_fprintf (stream, "\tsub $%#wo, sp\n", size - 2); - - } -} - -#else /* !TWO_BSD */ - static void pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size) { @@ -331,8 +314,6 @@ pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size) fprintf (stream, "\t;/* end of prologue */\n\n"); } -#endif /* !TWO_BSD */ - /* The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because @@ -352,18 +333,6 @@ pdp11_output_function_prologue (FILE *stream, HOST_WIDE_INT size) maybe as option if you want to generate code for kernel mode? */ -#ifdef TWO_BSD - -static void -pdp11_output_function_epilogue (FILE *stream, - HOST_WIDE_INT size ATTRIBUTE_UNUSED) -{ - fprintf (stream, "\t/* SP ignored by cret? */\n"); - fprintf (stream, "\tjmp cret\n"); -} - -#else /* !TWO_BSD */ - static void pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size) { @@ -469,8 +438,6 @@ pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size) fprintf (stream, "\t;/* end of epilogue*/\n\n\n"); } -#endif /* !TWO_BSD */ - /* Return the best assembler insn template for moving operands[1] into operands[0] as a fullword. */ static const char * diff --git a/gcc/config/picochip/picochip.c b/gcc/config/picochip/picochip.c index b77b30186fc..e9b61563153 100644 --- a/gcc/config/picochip/picochip.c +++ b/gcc/config/picochip/picochip.c @@ -3898,23 +3898,6 @@ picochip_generate_halt (void) return const0_rtx; } -static rtx -picochip_generate_profile (tree arglist) -{ - tree arg0 = TREE_VALUE (arglist); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - - start_sequence(); - emit_insn (gen_profile (op0)); - - rtx insns = get_insns(); - end_sequence(); - emit_insn (insns); - - return const0_rtx; -} - - /* Initialise the builtin functions. Start by initialising descriptions of different types of functions (e.g., void fn(int), int fn(void)), and then use these to define the builtins. */ @@ -3996,14 +3979,6 @@ picochip_init_builtins (void) BUILT_IN_MD, NULL, NULL_TREE); /* Initialise the bit reverse function. */ - add_builtin_function ("__builtin_profile", void_ftype_int, - PICOCHIP_BUILTIN_PROFILE, BUILT_IN_MD, NULL, - NULL_TREE); - add_builtin_function ("picoProfile", void_ftype_int, - PICOCHIP_BUILTIN_PROFILE, BUILT_IN_MD, NULL, - NULL_TREE); - - /* Initialise the bit reverse function. */ add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned, PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL, NULL_TREE); @@ -4135,9 +4110,6 @@ picochip_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case PICOCHIP_BUILTIN_HALT: return picochip_generate_halt (); - case PICOCHIP_BUILTIN_PROFILE: - return picochip_generate_profile (arglist); - default: gcc_unreachable(); diff --git a/gcc/config/picochip/picochip.h b/gcc/config/picochip/picochip.h index 6c92fb48a69..dc57364f2b7 100644 --- a/gcc/config/picochip/picochip.h +++ b/gcc/config/picochip/picochip.h @@ -736,7 +736,6 @@ enum picochip_builtins PICOCHIP_BUILTIN_PUT_ARRAY, PICOCHIP_BUILTIN_TESTPORT_ARRAY, PICOCHIP_BUILTIN_ASRI, - PICOCHIP_BUILTIN_PROFILE, PICOCHIP_BUILTIN_HALT }; diff --git a/gcc/config/picochip/picochip.md b/gcc/config/picochip/picochip.md index e1f3b388f68..657629c96fa 100644 --- a/gcc/config/picochip/picochip.md +++ b/gcc/config/picochip/picochip.md @@ -111,9 +111,6 @@ ; Internal TSTPORT instruction, used to generate a single TSTPORT ; instruction for use in the testport branch split. (UNSPEC_INTERNAL_TESTPORT 19) - - ; instruction for use in the profile based optimizations. - (UNSPEC_INTERNAL_PROFILE 20) ] ) @@ -2228,14 +2225,6 @@ [(set_attr "length" "1") (set_attr "type" "unknown")]) -(define_insn "profile" - [(unspec_volatile [(match_operand:HI 0 "const_int_operand" "i")] - UNSPEC_INTERNAL_PROFILE)] - "" - "PROFILE_DUMMY %0 \t// (profile instruction %0)" - [(set_attr "length" "1") - (set_attr "type" "unknown")]) - (define_insn "internal_testport" [(set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_operand:HI 0 "const_int_operand" "i")] diff --git a/gcc/config/rs6000/aix41.h b/gcc/config/rs6000/aix41.h deleted file mode 100644 index a109084994a..00000000000 --- a/gcc/config/rs6000/aix41.h +++ /dev/null @@ -1,101 +0,0 @@ -/* Definitions of target machine for GNU compiler, - for IBM RS/6000 POWER running AIX version 4.1. - Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, - 2005, 2007 - Free Software Foundation, Inc. - Contributed by David Edelsohn (edelsohn@gnu.org). - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. */ - -#undef ASM_SPEC -#define ASM_SPEC "-u %(asm_cpu)" - -#undef ASM_DEFAULT_SPEC -#define ASM_DEFAULT_SPEC "-mcom" - -#undef TARGET_OS_CPP_BUILTINS -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - TARGET_OS_AIX_CPP_BUILTINS (); \ - } \ - while (0) - -#undef CPP_SPEC -#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\ - %{ansi: -D_ANSI_C_SOURCE}\ - %{mpe: -I/usr/lpp/ppe.poe/include}\ - %{pthread: -D_THREAD_SAFE}" - -#undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_NEW_MNEMONICS - -#undef PROCESSOR_DEFAULT -#define PROCESSOR_DEFAULT PROCESSOR_PPC601 - -/* AIX does not support Altivec. */ -#undef TARGET_ALTIVEC -#define TARGET_ALTIVEC 0 -#undef TARGET_ALTIVEC_ABI -#define TARGET_ALTIVEC_ABI 0 - -/* Define this macro as a C expression for the initializer of an - array of string to tell the driver program which options are - defaults for this target and thus do not need to be handled - specially when using `MULTILIB_OPTIONS'. - - Do not define this macro if `MULTILIB_OPTIONS' is not defined in - the target makefile fragment or if none of the options listed in - `MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */ - -#undef MULTILIB_DEFAULTS -#define MULTILIB_DEFAULTS { "mcpu=common" } - -#undef LIB_SPEC -#define LIB_SPEC "%{pg:-L/lib/profiled -L/usr/lib/profiled}\ - %{p:-L/lib/profiled -L/usr/lib/profiled} %{!shared:%{g*:-lg}}\ - %{mpe:-L/usr/lpp/ppe.poe/lib -lmpi -lvtd}\ - %{pthread: -L/usr/lib/threads -lpthreads -lc_r /usr/lib/libc.a}\ - %{!pthread: -lc}" - -#undef LINK_SPEC -#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\ - %{static:-bnso %(link_syscalls) } %{!shared: %{g*: %(link_libg) }}\ - %{shared:-bM:SRE %{!e:-bnoentry}}" - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "%{!shared:\ - %{mpe:%{pg:/usr/lpp/ppe.poe/lib/gcrt0.o}\ - %{!pg:%{p:/usr/lpp/ppe.poe/lib/mcrt0.o}\ - %{!p:/usr/lpp/ppe.poe/lib/crt0.o}}}\ - %{!mpe:\ - %{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\ - %{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}" - -/* AIX 4 uses PowerPC nop (ori 0,0,0) instruction as call glue for PowerPC - and "cror 31,31,31" for POWER architecture. */ - -#undef RS6000_CALL_GLUE -#define RS6000_CALL_GLUE "{cror 31,31,31|nop}" - -/* The IBM AIX 4.x assembler doesn't support forward references in - .set directives. We handle this by deferring the output of .set - directives to the end of the compilation unit. */ -#define TARGET_DEFERRED_OUTPUT_DEFS(DECL,TARGET) true - -#undef TARGET_64BIT -#define TARGET_64BIT 0 diff --git a/gcc/config/rs6000/aix41.opt b/gcc/config/rs6000/aix41.opt deleted file mode 100644 index 62e37679f7f..00000000000 --- a/gcc/config/rs6000/aix41.opt +++ /dev/null @@ -1,24 +0,0 @@ -; Options for AIX4.1. -; -; Copyright (C) 2005, 2007 Free Software Foundation, Inc. -; Contributed by Aldy Hernandez <aldy@quesejoda.com>. -; -; This file is part of GCC. -; -; GCC is free software; you can redistribute it and/or modify it under -; the terms of the GNU General Public License as published by the Free -; Software Foundation; either version 3, or (at your option) any later -; version. -; -; GCC is distributed in the hope that it will be useful, but WITHOUT -; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -; License for more details. -; -; You should have received a copy of the GNU General Public License -; along with GCC; see the file COPYING3. If not see -; <http://www.gnu.org/licenses/>. - -mpe -Target Report RejectNegative Var(internal_nothing_1) -Support message passing with the Parallel Environment diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 46cb876ed2d..ad2eb4b7fea 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -152,7 +152,7 @@ extern int dot_symbols; #define ASM_SPEC32 "-a32 %{n} %{T} %{Ym,*} %{Yd,*} \ %{mrelocatable} %{mrelocatable-lib} %{fpic:-K PIC} %{fPIC:-K PIC} \ -%{memb} %{!memb: %{msdata: -memb} %{msdata=eabi: -memb}} \ +%{memb} %{!memb: %{msdata=eabi: -memb}} \ %{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \ %{mcall-freebsd: -mbig} \ %{mcall-i960-old: -mlittle} \ diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index f968b2f1467..3aa17143b67 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -188,7 +188,19 @@ rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) tok = cpp_peek_token (pfile, idx++); while (tok->type == CPP_PADDING); ident = altivec_categorize_keyword (tok); - if (ident) + if (ident == C_CPP_HASHNODE (__pixel_keyword)) + { + expand_this = C_CPP_HASHNODE (__vector_keyword); + expand_bool_pixel = __pixel_keyword; + rid_code = RID_MAX; + } + else if (ident == C_CPP_HASHNODE (__bool_keyword)) + { + expand_this = C_CPP_HASHNODE (__vector_keyword); + expand_bool_pixel = __bool_keyword; + rid_code = RID_MAX; + } + else if (ident) rid_code = (enum rid)(ident->rid_code); } diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 3073561c9f0..17622c26f00 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15254,7 +15254,7 @@ rs6000_ra_ever_killed (void) rtx reg; rtx insn; - if (crtl->is_thunk) + if (cfun->is_thunk) return 0; /* regs_ever_live has LR marked as used if any sibcalls are present, @@ -17556,7 +17556,7 @@ rs6000_output_function_epilogue (FILE *file, System V.4 Powerpc's (and the embedded ABI derived from it) use a different traceback table. */ if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive - && rs6000_traceback != traceback_none && !crtl->is_thunk) + && rs6000_traceback != traceback_none && !cfun->is_thunk) { const char *fname = NULL; const char *language_string = lang_hooks.name; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5290e2b68c1..e7daff15bab 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -9278,7 +9278,7 @@ "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" "#" - [(set_attr "type" "*,load,store")]) + [(set_attr "type" "*,store,load")]) (define_split [(set (match_operand:TI 0 "gpc_reg_operand" "") diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 69ccb58a1ff..1deb0eb8cfd 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -588,7 +588,7 @@ extern int fixuplabelno; %{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \ SVR4_ASM_SPEC \ "%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \ -%{memb|msdata|msdata=eabi: -memb} \ +%{memb|msdata=eabi: -memb} \ %{mlittle|mlittle-endian:-mlittle; \ mbig|mbig-endian :-mbig; \ mcall-aixdesc | \ diff --git a/gcc/config/rs6000/sysv4.opt b/gcc/config/rs6000/sysv4.opt index 5de03b34a84..01b087dedcf 100644 --- a/gcc/config/rs6000/sysv4.opt +++ b/gcc/config/rs6000/sysv4.opt @@ -94,7 +94,8 @@ mregnames Target Mask(REGNAMES) Use alternate register names -;; FIXME: Does nothing. +;; This option does nothing and only exists because the compiler +;; driver passes all -m* options through. msdata Target no description yet diff --git a/gcc/config/rs6000/t-newas b/gcc/config/rs6000/t-newas deleted file mode 100644 index eed66bf5f09..00000000000 --- a/gcc/config/rs6000/t-newas +++ /dev/null @@ -1,37 +0,0 @@ -# Build the libraries for both hard and soft floating point and all of the -# different processor models - -MULTILIB_OPTIONS = msoft-float \ - mcpu=common/mcpu=power/mcpu=powerpc - -MULTILIB_DIRNAMES = soft-float \ - common power powerpc - -MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT) \ - mcpu?power=mpower \ - mcpu?power=mrios1 \ - mcpu?power=mcpu?rios1 \ - mcpu?power=mcpu?rsc \ - mcpu?power=mcpu?rsc1 \ - mcpu?power=mpower2 \ - mcpu?power=mrios2 \ - mcpu?power=mcpu=rios2 \ - mcpu?powerpc=mcpu?601 \ - mcpu?powerpc=mcpu?602 \ - mcpu?powerpc=mcpu?603 \ - mcpu?powerpc=mcpu?603e \ - mcpu?powerpc=mcpu?604 \ - mcpu?powerpc=mcpu?620 \ - mcpu?powerpc=mcpu?403 \ - mcpu?powerpc=mpowerpc \ - mcpu?powerpc=mpowerpc-gpopt \ - mcpu?powerpc=mpowerpc-gfxopt - -# GCC 128-bit long double support routines. -LIB2FUNCS_EXTRA = $(srcdir)/config/rs6000/darwin-ldouble.c - -# Aix 3.2.x needs milli.exp for -mcpu=common -EXTRA_PARTS = milli.exp -$(T)milli.exp: $(srcdir)/config/rs6000/milli.exp - rm -f $(T)milli.exp - cp $(srcdir)/config/rs6000/milli.exp $(T)milli.exp diff --git a/gcc/config/rs6000/t-rtems b/gcc/config/rs6000/t-rtems index b3db9498a23..c0fd8bf3b07 100644 --- a/gcc/config/rs6000/t-rtems +++ b/gcc/config/rs6000/t-rtems @@ -10,8 +10,6 @@ m403 m505 m601 m603e m604 m860 m7400 \ mpc8260 \ nof -MULTILIB_EXTRA_OPTS = mrelocatable-lib mno-eabi mstrict-align - # MULTILIB_MATCHES = ${MULTILIB_MATCHES_FLOAT} MULTILIB_MATCHES = MULTILIB_MATCHES += ${MULTILIB_MATCHES_ENDIAN} diff --git a/gcc/config/sh/coff.h b/gcc/config/sh/coff.h deleted file mode 100644 index a3242c54a76..00000000000 --- a/gcc/config/sh/coff.h +++ /dev/null @@ -1,70 +0,0 @@ -/* Definitions of target machine for gcc for Renesas / SuperH SH using ELF. - Copyright (C) 1997, 1998, 2001, 2002, 2007 Free Software Foundation, Inc. - Contributed by Jörn Rennecke <joern.rennecke@superh.com>. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -/* Generate SDB debugging information. */ - -#define SDB_DEBUGGING_INFO 1 - -#define SDB_DELIM ";" - -#ifndef MAX_OFILE_ALIGNMENT -#define MAX_OFILE_ALIGNMENT 128 -#endif - -#define IDENT_ASM_OP "\t.ident\t" - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION default_coff_asm_named_section - -/* The prefix to add to user-visible assembler symbols. */ - -#define USER_LABEL_PREFIX "_" - -/* The prefix to add to an internally generated label. */ - -#define LOCAL_LABEL_PREFIX "" - -/* Make an internal label into a string. */ -#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ - sprintf ((STRING), "*%s%s%ld", LOCAL_LABEL_PREFIX, (PREFIX), (long)(NUM)) - -/* This is how to output an assembler line - that says to advance the location counter by SIZE bytes. */ - -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf ((FILE), "\t.space %d\n", (int)(SIZE)) - -/* This says how to output an assembler line - to define a global common symbol. */ - -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\t.comm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%d\n", (int)(SIZE))) - -/* This says how to output an assembler line - to define a local common symbol. */ - -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -( fputs ("\t.lcomm ", (FILE)), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ",%d\n", (int)(SIZE))) - -#define DWARF2_UNWIND_INFO 0 diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 3c57730b83e..c8f4c85ee75 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -5966,7 +5966,9 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) && crtl->args.info.call_cookie && reg == PIC_OFFSET_TABLE_REGNUM) || (df_regs_ever_live_p (reg) - && (!call_really_used_regs[reg] + && ((!call_really_used_regs[reg] + && !(reg != PIC_OFFSET_TABLE_REGNUM + && fixed_regs[reg] && call_used_regs[reg])) || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY))) || (crtl->calls_eh_return && (reg == EH_RETURN_DATA_REGNO (0) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index e20bfbdb45b..7e6a358f89b 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -282,7 +282,7 @@ static GTY(()) alias_set_type struct_value_alias_set; /* Save the operands last given to a compare for use when we generate a scc or bcc insn. */ -rtx sparc_compare_op0, sparc_compare_op1, sparc_compare_emitted; +rtx sparc_compare_op0, sparc_compare_op1; /* Vector to say how input registers are mapped to output registers. HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to @@ -2006,17 +2006,15 @@ select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) rtx gen_compare_reg (enum rtx_code code) { - rtx x = sparc_compare_op0; - rtx y = sparc_compare_op1; - enum machine_mode mode = SELECT_CC_MODE (code, x, y); - rtx cc_reg; + enum machine_mode mode; + rtx x, y, cc_reg; - if (sparc_compare_emitted != NULL_RTX) - { - cc_reg = sparc_compare_emitted; - sparc_compare_emitted = NULL_RTX; - return cc_reg; - } + if (GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_CC) + return sparc_compare_op0; + + x = sparc_compare_op0; + y = sparc_compare_op1; + mode = SELECT_CC_MODE (code, x, y); /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the fcc regs (cse can't tell they're really call clobbered regs and will @@ -2198,7 +2196,7 @@ gen_v9_scc (enum rtx_code compare_code, register rtx *operands) void emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) { - gcc_assert (sparc_compare_emitted == NULL_RTX); + gcc_assert (GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) != MODE_CC); emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, gen_rtx_IF_THEN_ELSE (VOIDmode, @@ -9026,7 +9024,8 @@ sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval) emit_insn (gen_rtx_SET (VOIDmode, val, resv)); - sparc_compare_emitted = cc; + sparc_compare_op0 = cc; + sparc_compare_op1 = const0_rtx; emit_jump_insn (gen_bne (loop_label)); emit_label (end_label); diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 6271a943d19..6a46093dfd3 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1558,12 +1558,10 @@ function_arg_padding ((MODE), (TYPE)) ? 128 : PARM_BOUNDARY) /* Define the information needed to generate branch and scc insns. This is - stored from the compare operation. Note that we can't use "rtx" here - since it hasn't been defined! */ + stored from the compare operation. */ extern GTY(()) rtx sparc_compare_op0; extern GTY(()) rtx sparc_compare_op1; -extern GTY(()) rtx sparc_compare_emitted; /* Generate the special assembly code needed to tell the assembler whatever diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index d78d6e93b43..8e8991129aa 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -7082,10 +7082,10 @@ [(unspec_volatile [(const_int 0)] UNSPECV_SETJMP)] "" { - if (! cfun->calls_alloca) + if (!cfun->calls_alloca) return ""; - if (! TARGET_V9) - return "\tta\t3\n"; + if (!TARGET_V9) + return "ta\t3"; fputs ("\tflushw\n", asm_out_file); if (flag_pic) fprintf (asm_out_file, "\tst%c\t%%l7, [%%sp+%d]\n", @@ -8076,9 +8076,8 @@ else { emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); - sparc_compare_op0 = operands[0]; - sparc_compare_op1 = operands[1]; - sparc_compare_emitted = gen_rtx_REG (CCmode, SPARC_ICC_REG); + sparc_compare_op0 = gen_rtx_REG (CCmode, SPARC_ICC_REG); + sparc_compare_op1 = const0_rtx; } emit_jump_insn (gen_beq (operands[2])); DONE; @@ -8173,7 +8172,7 @@ ;; (ior (not (op1)) (not (op2))) is the canonical form of NAND. -(define_insn "*nand<V64mode>_vis" +(define_insn "*nand<V64:mode>_vis" [(set (match_operand:V64 0 "register_operand" "=e") (ior:V64 (not:V64 (match_operand:V64 1 "register_operand" "e")) (not:V64 (match_operand:V64 2 "register_operand" "e"))))] @@ -8182,7 +8181,7 @@ [(set_attr "type" "fga") (set_attr "fptype" "double")]) -(define_insn "*nand<V32mode>_vis" +(define_insn "*nand<V32:mode>_vis" [(set (match_operand:V32 0 "register_operand" "=f") (ior:V32 (not:V32 (match_operand:V32 1 "register_operand" "f")) (not:V32 (match_operand:V32 2 "register_operand" "f"))))] diff --git a/gcc/config/spu/divv2df3.c b/gcc/config/spu/divv2df3.c new file mode 100644 index 00000000000..cd7126bb733 --- /dev/null +++ b/gcc/config/spu/divv2df3.c @@ -0,0 +1,198 @@ +/* Copyright (C) 2009 Free Software Foundation, Inc. + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. The exception does not + however invalidate any other reasons why the executable file might be covered + by the GNU General Public License. */ + + +#include <spu_intrinsics.h> + +vector double __divv2df3 (vector double a_in, vector double b_in); + +/* __divv2df3 divides the vector dividend a by the vector divisor b and + returns the resulting vector quotient. Maximum error about 0.5 ulp + over entire double range including denorms, compared to true result + in round-to-nearest rounding mode. Handles Inf or NaN operands and + results correctly. */ + +vector double +__divv2df3 (vector double a_in, vector double b_in) +{ + /* Variables */ + vec_int4 exp, exp_bias; + vec_uint4 no_underflow, overflow; + vec_float4 mant_bf, inv_bf; + vec_ullong2 exp_a, exp_b; + vec_ullong2 a_nan, a_zero, a_inf, a_denorm, a_denorm0; + vec_ullong2 b_nan, b_zero, b_inf, b_denorm, b_denorm0; + vec_ullong2 nan; + vec_uint4 a_exp, b_exp; + vec_ullong2 a_mant_0, b_mant_0; + vec_ullong2 a_exp_1s, b_exp_1s; + vec_ullong2 sign_exp_mask; + + vec_double2 a, b; + vec_double2 mant_a, mant_b, inv_b, q0, q1, q2, mult; + + /* Constants */ + vec_uint4 exp_mask_u32 = spu_splats((unsigned int)0x7FF00000); + vec_uchar16 splat_hi = (vec_uchar16){0,1,2,3, 0,1,2,3, 8, 9,10,11, 8,9,10,11}; + vec_uchar16 swap_32 = (vec_uchar16){4,5,6,7, 0,1,2,3, 12,13,14,15, 8,9,10,11}; + vec_ullong2 exp_mask = spu_splats(0x7FF0000000000000ULL); + vec_ullong2 sign_mask = spu_splats(0x8000000000000000ULL); + vec_float4 onef = spu_splats(1.0f); + vec_double2 one = spu_splats(1.0); + vec_double2 exp_53 = (vec_double2)spu_splats(0x0350000000000000ULL); + + sign_exp_mask = spu_or(sign_mask, exp_mask); + + /* Extract the floating point components from each of the operands including + * exponent and mantissa. + */ + a_exp = (vec_uint4)spu_and((vec_uint4)a_in, exp_mask_u32); + a_exp = spu_shuffle(a_exp, a_exp, splat_hi); + b_exp = (vec_uint4)spu_and((vec_uint4)b_in, exp_mask_u32); + b_exp = spu_shuffle(b_exp, b_exp, splat_hi); + + a_mant_0 = (vec_ullong2)spu_cmpeq((vec_uint4)spu_andc((vec_ullong2)a_in, sign_exp_mask), 0); + a_mant_0 = spu_and(a_mant_0, spu_shuffle(a_mant_0, a_mant_0, swap_32)); + + b_mant_0 = (vec_ullong2)spu_cmpeq((vec_uint4)spu_andc((vec_ullong2)b_in, sign_exp_mask), 0); + b_mant_0 = spu_and(b_mant_0, spu_shuffle(b_mant_0, b_mant_0, swap_32)); + + a_exp_1s = (vec_ullong2)spu_cmpeq(a_exp, exp_mask_u32); + b_exp_1s = (vec_ullong2)spu_cmpeq(b_exp, exp_mask_u32); + + /* Identify all possible special values that must be accomodated including: + * +-denorm, +-0, +-infinity, and NaNs. + */ + a_denorm0= (vec_ullong2)spu_cmpeq(a_exp, 0); + a_nan = spu_andc(a_exp_1s, a_mant_0); + a_zero = spu_and (a_denorm0, a_mant_0); + a_inf = spu_and (a_exp_1s, a_mant_0); + a_denorm = spu_andc(a_denorm0, a_zero); + + b_denorm0= (vec_ullong2)spu_cmpeq(b_exp, 0); + b_nan = spu_andc(b_exp_1s, b_mant_0); + b_zero = spu_and (b_denorm0, b_mant_0); + b_inf = spu_and (b_exp_1s, b_mant_0); + b_denorm = spu_andc(b_denorm0, b_zero); + + /* Scale denorm inputs to into normalized numbers by conditionally scaling the + * input parameters. + */ + a = spu_sub(spu_or(a_in, exp_53), spu_sel(exp_53, a_in, sign_mask)); + a = spu_sel(a_in, a, a_denorm); + + b = spu_sub(spu_or(b_in, exp_53), spu_sel(exp_53, b_in, sign_mask)); + b = spu_sel(b_in, b, b_denorm); + + /* Extract the divisor and dividend exponent and force parameters into the signed + * range [1.0,2.0) or [-1.0,2.0). + */ + exp_a = spu_and((vec_ullong2)a, exp_mask); + exp_b = spu_and((vec_ullong2)b, exp_mask); + + mant_a = spu_sel(a, one, (vec_ullong2)exp_mask); + mant_b = spu_sel(b, one, (vec_ullong2)exp_mask); + + /* Approximate the single reciprocal of b by using + * the single precision reciprocal estimate followed by one + * single precision iteration of Newton-Raphson. + */ + mant_bf = spu_roundtf(mant_b); + inv_bf = spu_re(mant_bf); + inv_bf = spu_madd(spu_nmsub(mant_bf, inv_bf, onef), inv_bf, inv_bf); + + /* Perform 2 more Newton-Raphson iterations in double precision. The + * result (q1) is in the range (0.5, 2.0). + */ + inv_b = spu_extend(inv_bf); + inv_b = spu_madd(spu_nmsub(mant_b, inv_b, one), inv_b, inv_b); + q0 = spu_mul(mant_a, inv_b); + q1 = spu_madd(spu_nmsub(mant_b, q0, mant_a), inv_b, q0); + + /* Determine the exponent correction factor that must be applied + * to q1 by taking into account the exponent of the normalized inputs + * and the scale factors that were applied to normalize them. + */ + exp = spu_rlmaska(spu_sub((vec_int4)exp_a, (vec_int4)exp_b), -20); + exp = spu_add(exp, (vec_int4)spu_add(spu_and((vec_int4)a_denorm, -0x34), spu_and((vec_int4)b_denorm, 0x34))); + + /* Bias the quotient exponent depending on the sign of the exponent correction + * factor so that a single multiplier will ensure the entire double precision + * domain (including denorms) can be achieved. + * + * exp bias q1 adjust exp + * ===== ======== ========== + * positive 2^+65 -65 + * negative 2^-64 +64 + */ + exp_bias = spu_xor(spu_rlmaska(exp, -31), 64); + exp = spu_sub(exp, exp_bias); + + q1 = spu_sel(q1, (vec_double2)spu_add((vec_int4)q1, spu_sl(exp_bias, 20)), exp_mask); + + /* Compute a multiplier (mult) to applied to the quotient (q1) to produce the + * expected result. On overflow, clamp the multiplier to the maximum non-infinite + * number in case the rounding mode is not round-to-nearest. + */ + exp = spu_add(exp, 0x3FF); + no_underflow = spu_cmpgt(exp, 0); + overflow = spu_cmpgt(exp, 0x7FE); + exp = spu_and(spu_sl(exp, 20), (vec_int4)no_underflow); + exp = spu_and(exp, (vec_int4)exp_mask); + + mult = spu_sel((vec_double2)exp, (vec_double2)(spu_add((vec_uint4)exp_mask, -1)), (vec_ullong2)overflow); + + /* Handle special value conditions. These include: + * + * 1) IF either operand is a NaN OR both operands are 0 or INFINITY THEN a NaN + * results. + * 2) ELSE IF the dividend is an INFINITY OR the divisor is 0 THEN a INFINITY results. + * 3) ELSE IF the dividend is 0 OR the divisor is INFINITY THEN a 0 results. + */ + mult = spu_andc(mult, (vec_double2)spu_or(a_zero, b_inf)); + mult = spu_sel(mult, (vec_double2)exp_mask, spu_or(a_inf, b_zero)); + + nan = spu_or(a_nan, b_nan); + nan = spu_or(nan, spu_and(a_zero, b_zero)); + nan = spu_or(nan, spu_and(a_inf, b_inf)); + + mult = spu_or(mult, (vec_double2)nan); + + /* Scale the final quotient */ + + q2 = spu_mul(q1, mult); + + return (q2); +} + + +/* We use the same function for vector and scalar division. Provide the + scalar entry point as an alias. */ +double __divdf3 (double a, double b) + __attribute__ ((__alias__ ("__divv2df3"))); + +/* Some toolchain builds used the __fast_divdf3 name for this helper function. + Provide this as another alternate entry point for compatibility. */ +double __fast_divdf3 (double a, double b) + __attribute__ ((__alias__ ("__divv2df3"))); + diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index a29125269e5..6e0001b0a05 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -143,6 +143,7 @@ static bool spu_vector_alignment_reachable (const_tree, bool); static tree spu_builtin_vec_perm (tree, tree *); static int spu_sms_res_mii (struct ddg *g); static void asm_file_start (void); +static unsigned int spu_section_type_flags (tree, const char *, int); extern const char *reg_names[]; rtx spu_compare_op0, spu_compare_op1; @@ -329,6 +330,9 @@ const struct attribute_spec spu_attribute_table[]; #undef TARGET_ASM_FILE_START #define TARGET_ASM_FILE_START asm_file_start +#undef TARGET_SECTION_TYPE_FLAGS +#define TARGET_SECTION_TYPE_FLAGS spu_section_type_flags + struct gcc_target targetm = TARGET_INITIALIZER; void @@ -4110,17 +4114,16 @@ spu_expand_mov (rtx * ops, enum machine_mode mode) if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1])) { rtx from = SUBREG_REG (ops[1]); - enum machine_mode imode = GET_MODE (from); + enum machine_mode imode = int_mode_for_mode (GET_MODE (from)); gcc_assert (GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_CLASS (imode) == MODE_INT && subreg_lowpart_p (ops[1])); if (GET_MODE_SIZE (imode) < 4) - { - from = gen_rtx_SUBREG (SImode, from, 0); - imode = SImode; - } + imode = SImode; + if (imode != GET_MODE (from)) + from = gen_rtx_SUBREG (imode, from, 0); if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (imode)) { @@ -6285,3 +6288,13 @@ asm_file_start (void) default_file_start (); } +/* Implement targetm.section_type_flags. */ +static unsigned int +spu_section_type_flags (tree decl, const char *name, int reloc) +{ + /* .toe needs to have type @nobits. */ + if (strcmp (name, ".toe") == 0) + return SECTION_BSS; + return default_section_type_flags (decl, name, reloc); +} + diff --git a/gcc/config/spu/t-spu-elf b/gcc/config/spu/t-spu-elf index 2e1928707df..f8c5ba5b01d 100644 --- a/gcc/config/spu/t-spu-elf +++ b/gcc/config/spu/t-spu-elf @@ -29,6 +29,10 @@ TARGET_LIBGCC2_CFLAGS = -fPIC -mwarn-reloc -D__IN_LIBGCC2 # own versions below. LIB2FUNCS_EXCLUDE = _floatdisf _floatundisf +# We provide our own version of __divdf3 that performs better and has +# better support for non-default rounding modes. +DPBIT_FUNCS := $(filter-out _div_df, $(DPBIT_FUNCS)) + LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/spu/float_unssidf.c \ $(srcdir)/config/spu/float_unsdidf.c \ $(srcdir)/config/spu/float_unsdisf.c \ @@ -39,7 +43,8 @@ LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/spu/float_unssidf.c \ $(srcdir)/config/spu/mfc_multi_tag_reserve.c \ $(srcdir)/config/spu/mfc_multi_tag_release.c \ $(srcdir)/config/spu/multi3.c \ - $(srcdir)/config/spu/divmodti4.c + $(srcdir)/config/spu/divmodti4.c \ + $(srcdir)/config/spu/divv2df3.c LIB2ADDEH = $(srcdir)/unwind-dw2.c $(srcdir)/unwind-dw2-fde.c \ $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c diff --git a/gcc/config/t-svr4 b/gcc/config/t-svr4 index 3ea1174580d..6e75eea1f6e 100644 --- a/gcc/config/t-svr4 +++ b/gcc/config/t-svr4 @@ -6,6 +6,3 @@ CRTSTUFF_T_CFLAGS_S = $(CRTSTUFF_T_CFLAGS) -fPIC TARGET_LIBGCC2_CFLAGS = -fPIC - -# See all the declarations. -FIXPROTO_DEFINES = -D_XOPEN_SOURCE diff --git a/gcc/config/t-vxworks b/gcc/config/t-vxworks index c9d69e0edce..ebedb1f5056 100644 --- a/gcc/config/t-vxworks +++ b/gcc/config/t-vxworks @@ -1,6 +1,3 @@ -# Don't run fixproto. -STMP_FIXPROTO = - # Build libgcc using the multilib mechanism LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib |