diff options
Diffstat (limited to 'gcc/config')
72 files changed, 667 insertions, 404 deletions
diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 9136910cd32..822d608a5b3 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -762,16 +762,16 @@ aarch64_init_simd_builtins (void) if (qualifiers & qualifier_unsigned) { - type_signature[arg_num] = 'u'; + type_signature[op_num] = 'u'; print_type_signature_p = true; } else if (qualifiers & qualifier_poly) { - type_signature[arg_num] = 'p'; + type_signature[op_num] = 'p'; print_type_signature_p = true; } else - type_signature[arg_num] = 's'; + type_signature[op_num] = 's'; /* Skip an internal operand for vget_{low, high}. */ if (qualifiers & qualifier_internal) diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index 048c2a3e3f7..68b5ba0ad0e 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -29,3 +29,8 @@ AARCH64_TUNE_ to give an enum name. */ AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS) + +/* Don't create non-8 byte aligned load/store pair. That is if the +two load/stores are not at least 8 byte aligned don't create load/store +pairs. */ +AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3e663eb5f13..6078b163548 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -712,7 +712,7 @@ static const struct tune_params thunderx_tunings = 0, /* max_case_values. */ 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) /* tune_flags. */ }; static const struct tune_params xgene1_tunings = @@ -4191,6 +4191,24 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x, return aarch64_classify_address (&addr, x, mode, outer_code, strict_p); } +/* Split an out-of-range address displacement into a base and offset. + Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise + to increase opportunities for sharing the base address of different sizes. + For TI/TFmode and unaligned accesses use a 256-byte range. */ +static bool +aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode) +{ + HOST_WIDE_INT mask = GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3fff; + + if (mode == TImode || mode == TFmode || + (INTVAL (*disp) & (GET_MODE_SIZE (mode) - 1)) != 0) + mask = 0xff; + + *off = GEN_INT (INTVAL (*disp) & ~mask); + *disp = GEN_INT (INTVAL (*disp) & mask); + return true; +} + /* Return TRUE if rtx X is immediate constant 0.0 */ bool aarch64_float_const_zero_rtx_p (rtx x) @@ -4264,6 +4282,14 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) && (GET_MODE (x) == HImode || GET_MODE (x) == QImode)) return CC_NZmode; + /* Similarly, comparisons of zero_extends from shorter modes can + be performed using an ANDS with an immediate mask. */ + if (y == const0_rtx && GET_CODE (x) == ZERO_EXTEND + && (GET_MODE (x) == SImode || GET_MODE (x) == DImode) + && (GET_MODE (XEXP (x, 0)) == HImode || GET_MODE (XEXP (x, 0)) == QImode) + && (code == EQ || code == NE)) + return CC_NZmode; + if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) && y == const0_rtx && (code == EQ || code == NE || code == LT || code == GE) @@ -5056,9 +5082,19 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */, machine_mode mode) /* For offsets aren't a multiple of the access size, the limit is -256...255. */ else if (offset & (GET_MODE_SIZE (mode) - 1)) - base_offset = (offset + 0x100) & ~0x1ff; + { + base_offset = (offset + 0x100) & ~0x1ff; + + /* BLKmode typically uses LDP of X-registers. */ + if (mode == BLKmode) + base_offset = (offset + 512) & ~0x3ff; + } + /* Small negative offsets are supported. */ + else if (IN_RANGE (offset, -256, 0)) + base_offset = 0; + /* Use 12-bit offset by access size. */ else - base_offset = offset & ~0xfff; + base_offset = offset & (~0xfff * GET_MODE_SIZE (mode)); if (base_offset != 0) { @@ -13593,6 +13629,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2)) return false; + /* If we have SImode and slow unaligned ldp, + check the alignment to be at least 8 byte. */ + if (mode == SImode + && (aarch64_tune_params.extra_tuning_flags + & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) + && !optimize_size + && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT) + return false; + /* Check if the addresses are in the form of [base+offset]. */ extract_base_offset_in_addr (mem_1, &base_1, &offset_1); if (base_1 == NULL_RTX || offset_1 == NULL_RTX) @@ -13752,6 +13797,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load, return false; } + /* If we have SImode and slow unaligned ldp, + check the alignment to be at least 8 byte. */ + if (mode == SImode + && (aarch64_tune_params.extra_tuning_flags + & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) + && !optimize_size + && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT) + return false; + if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1))) rclass_1 = FP_REGS; else @@ -14127,12 +14181,13 @@ aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode, #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p +#undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT +#define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \ + aarch64_legitimize_address_displacement + #undef TARGET_LIBGCC_CMP_RETURN_MODE #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode -#undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_true - #undef TARGET_MANGLE_TYPE #define TARGET_MANGLE_TYPE aarch64_mangle_type diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c95258b7103..6afaf906915 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3811,6 +3811,18 @@ [(set_attr "type" "alus_imm")] ) +(define_insn "*ands<mode>_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (zero_extend:GPI (match_dup 1)))] + "" + "ands\\t%<GPI:w>0, %<GPI:w>1, <short_mask>" + [(set_attr "type" "alus_imm")] +) + (define_insn "*and<mode>3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 702cd277ede..6d4af04dd7d 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -5754,8 +5754,29 @@ static bool alpha_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, machine_mode mode, const_tree type ATTRIBUTE_UNUSED, - bool named ATTRIBUTE_UNUSED) + bool named) { + /* Pass float and _Complex float variable arguments by reference. + This avoids 64-bit store from a FP register to a pretend args save area + and subsequent 32-bit load from the saved location to a FP register. + + Note that 32-bit loads and stores to/from a FP register on alpha reorder + bits to form a canonical 64-bit value in the FP register. This fact + invalidates compiler assumption that 32-bit FP value lives in the lower + 32-bits of the passed 64-bit FP value, so loading the 32-bit value from + the stored 64-bit location using 32-bit FP load is invalid on alpha. + + This introduces sort of ABI incompatibility, but until _Float32 was + introduced, C-family languages promoted 32-bit float variable arg to + a 64-bit double, and it was not allowed to pass float as a varible + argument. Passing _Complex float as a variable argument never + worked on alpha. Thus, we have no backward compatibility issues + to worry about, and passing unpromoted _Float32 and _Complex float + as a variable argument will actually work in the future. */ + + if (mode == SFmode || mode == SCmode) + return !named; + return mode == TFmode || mode == TCmode; } @@ -10039,6 +10060,9 @@ alpha_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) #define TARGET_MANGLE_TYPE alpha_mangle_type #endif +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P alpha_legitimate_address_p diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 946f308ca84..1183d45d497 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -355,9 +355,6 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_LEGITIMIZE_ADDRESS #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address -#undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_true - #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE arm_attribute_table diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index f6d73423728..148a61df721 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -13843,6 +13843,9 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg, #undef TARGET_CONVERT_TO_TYPE #define TARGET_CONVERT_TO_TYPE avr_convert_to_type +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_ADDR_SPACE_SUBSET_P #define TARGET_ADDR_SPACE_SUBSET_P avr_addr_space_subset_p diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index 086d5482706..e1e39459201 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -5805,6 +5805,9 @@ bfin_conditional_register_usage (void) #undef TARGET_RETURN_IN_MEMORY #define TARGET_RETURN_IN_MEMORY bfin_return_in_memory +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P bfin_legitimate_address_p diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c index d75948260fc..cd7c1bb4559 100644 --- a/gcc/config/c6x/c6x.c +++ b/gcc/config/c6x/c6x.c @@ -6748,6 +6748,9 @@ c6x_debug_unwind_info (void) #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P c6x_legitimate_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_IN_SMALL_DATA_P #define TARGET_IN_SMALL_DATA_P c6x_in_small_data_p #undef TARGET_ASM_SELECT_RTX_SECTION diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c index 141b8bc895f..2f75ca2301b 100644 --- a/gcc/config/cr16/cr16.c +++ b/gcc/config/cr16/cr16.c @@ -172,6 +172,9 @@ static void cr16_print_operand_address (FILE *, machine_mode, rtx); #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P cr16_legitimate_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + /* Returning function value. */ #undef TARGET_FUNCTION_VALUE #define TARGET_FUNCTION_VALUE cr16_function_value diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 971d07fb12a..203819381e1 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -212,6 +212,9 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; #undef TARGET_INIT_LIBFUNCS #define TARGET_INIT_LIBFUNCS cris_init_libfuncs +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p @@ -1282,8 +1285,7 @@ cris_return_address_on_stack_for_return (void) : cris_return_address_on_stack (); } -/* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only - handles FP -> SP elimination offset. */ +/* This handles FP -> SP elimination offset. */ static int cris_initial_frame_pointer_offset (void) diff --git a/gcc/config/darwin-protos.h b/gcc/config/darwin-protos.h index 62c72596461..7eb096b4577 100644 --- a/gcc/config/darwin-protos.h +++ b/gcc/config/darwin-protos.h @@ -91,9 +91,9 @@ extern void darwin_globalize_label (FILE *, const char *); extern void darwin_assemble_visibility (tree, int); extern void darwin_asm_output_dwarf_delta (FILE *, int, const char *, - const char *); + const char *, HOST_WIDE_INT); extern void darwin_asm_output_dwarf_offset (FILE *, int, const char *, - section *); + HOST_WIDE_INT, section *); extern void darwin_asm_declare_object_name (FILE *, const char *, tree); extern void darwin_asm_declare_constant_name (FILE *, const char *, diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index 0055d805441..f8da9591be8 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -2790,7 +2790,8 @@ static int darwin_dwarf_label_counter; void darwin_asm_output_dwarf_delta (FILE *file, int size, - const char *lab1, const char *lab2) + const char *lab1, const char *lab2, + HOST_WIDE_INT offset) { int islocaldiff = (lab1[0] == '*' && lab1[1] == 'L' && lab2[0] == '*' && lab2[1] == 'L'); @@ -2804,6 +2805,8 @@ darwin_asm_output_dwarf_delta (FILE *file, int size, assemble_name_raw (file, lab1); fprintf (file, "-"); assemble_name_raw (file, lab2); + if (offset != 0) + fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset); if (islocaldiff) fprintf (file, "\n\t%s L$set$%d", directive, darwin_dwarf_label_counter++); } @@ -2815,7 +2818,7 @@ darwin_asm_output_dwarf_delta (FILE *file, int size, void darwin_asm_output_dwarf_offset (FILE *file, int size, const char * lab, - section *base) + HOST_WIDE_INT offset, section *base) { char sname[64]; int namelen; @@ -2826,7 +2829,7 @@ darwin_asm_output_dwarf_offset (FILE *file, int size, const char * lab, namelen = strchr (base->named.name + 8, ',') - (base->named.name + 8); sprintf (sname, "*Lsection%.*s", namelen, base->named.name + 8); - darwin_asm_output_dwarf_delta (file, size, lab, sname); + darwin_asm_output_dwarf_delta (file, size, lab, sname, offset); } /* Called from the within the TARGET_ASM_FILE_START for each target. */ diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h index 944548a7416..3782eb34047 100644 --- a/gcc/config/darwin.h +++ b/gcc/config/darwin.h @@ -835,10 +835,10 @@ enum machopic_addr_class { ((CODE) == 1 || (GLOBAL) == 0) ? DW_EH_PE_pcrel : DW_EH_PE_absptr) #define ASM_OUTPUT_DWARF_DELTA(FILE,SIZE,LABEL1,LABEL2) \ - darwin_asm_output_dwarf_delta (FILE, SIZE, LABEL1, LABEL2) + darwin_asm_output_dwarf_delta (FILE, SIZE, LABEL1, LABEL2, 0) -#define ASM_OUTPUT_DWARF_OFFSET(FILE,SIZE,LABEL,BASE) \ - darwin_asm_output_dwarf_offset (FILE, SIZE, LABEL, BASE) +#define ASM_OUTPUT_DWARF_OFFSET(FILE,SIZE,LABEL,OFFSET,BASE) \ + darwin_asm_output_dwarf_offset (FILE, SIZE, LABEL, OFFSET, BASE) #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(ASM_OUT_FILE, ENCODING, SIZE, ADDR, DONE) \ if (ENCODING == ASM_PREFERRED_EH_DATA_FORMAT (2, 1)) { \ diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c index 25cbdfc6982..b871ccb3feb 100644 --- a/gcc/config/epiphany/epiphany.c +++ b/gcc/config/epiphany/epiphany.c @@ -102,6 +102,8 @@ static rtx_insn *frame_insn (rtx); #define TARGET_SCHED_ISSUE_RATE epiphany_issue_rate #define TARGET_SCHED_ADJUST_COST epiphany_adjust_cost +#define TARGET_LRA_P hook_bool_void_false + #define TARGET_LEGITIMATE_ADDRESS_P epiphany_legitimate_address_p #define TARGET_SECONDARY_RELOAD epiphany_secondary_reload diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c index f4fef2b3f04..741a0136640 100644 --- a/gcc/config/fr30/fr30.c +++ b/gcc/config/fr30/fr30.c @@ -179,6 +179,9 @@ static int fr30_num_arg_regs (machine_mode, const_tree); #undef TARGET_CAN_ELIMINATE #define TARGET_CAN_ELIMINATE fr30_can_eliminate +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_ASM_TRAMPOLINE_TEMPLATE #define TARGET_ASM_TRAMPOLINE_TEMPLATE fr30_asm_trampoline_template #undef TARGET_TRAMPOLINE_INIT diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h index 51a05db9c2d..82366e35415 100644 --- a/gcc/config/fr30/fr30.h +++ b/gcc/config/fr30/fr30.h @@ -460,9 +460,8 @@ enum reg_class {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ } -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the - initial difference between the specified pair of registers. This macro must - be defined if `ELIMINABLE_REGS' is defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ (OFFSET) = fr30_compute_frame_size (FROM, TO) diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index 957ff0390a0..60c3863bbad 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -491,6 +491,9 @@ static bool frv_class_likely_spilled_p (reg_class_t); #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD frv_secondary_reload +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p @@ -2076,9 +2079,8 @@ frv_can_eliminate (const int from, const int to) : true); } -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the - initial difference between the specified pair of registers. This macro must - be defined if `ELIMINABLE_REGS' is defined. */ +/* This function returns the initial difference between the specified + pair of registers. */ /* See frv_stack_info for more details on the frv stack frame. */ diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index 8d41b6aa84a..e7f87b1ff88 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -1197,9 +1197,8 @@ typedef struct frv_stack { {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ } -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the - initial difference between the specified pair of registers. This macro must - be defined if `ELIMINABLE_REGS' is defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ (OFFSET) = frv_initial_elimination_offset (FROM, TO) diff --git a/gcc/config/ft32/ft32.h b/gcc/config/ft32/ft32.h index dd40b1de0b6..6bfd4851fe6 100644 --- a/gcc/config/ft32/ft32.h +++ b/gcc/config/ft32/ft32.h @@ -250,8 +250,6 @@ enum reg_class pointer to a smaller address. */ #define STACK_GROWS_DOWNWARD 1 -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0 - /* Offset from the frame pointer to the first local variable slot to be allocated. */ #define STARTING_FRAME_OFFSET 0 @@ -426,10 +424,8 @@ do { \ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It - specifies the initial difference between the specified pair of - registers. This macro must be defined if `ELIMINABLE_REGS' is - defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ do { \ (OFFSET) = ft32_initial_elimination_offset ((FROM), (TO)); \ diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 1818684c72b..db8eeab3361 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -6097,6 +6097,9 @@ h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) #undef TARGET_HARD_REGNO_SCRATCH_OK #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index d6c2254b800..60e11b481e9 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -102,13 +102,16 @@ along with GCC; see the file COPYING3. If not see /* Use section relative relocations for debugging offsets. Unlike other targets that fake this by putting the section VMA at 0, PE won't allow it. */ -#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION) \ +#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, OFFSET, SECTION) \ do { \ switch (SIZE) \ { \ case 4: \ fputs ("\t.secrel32\t", FILE); \ assemble_name (FILE, LABEL); \ + if ((OFFSET) != 0) \ + fprintf (FILE, "+" HOST_WIDE_INT_PRINT_DEC, \ + (HOST_WIDE_INT) (OFFSET)) \ break; \ case 8: \ /* This is a hack. There is no 64-bit section relative \ @@ -118,6 +121,9 @@ along with GCC; see the file COPYING3. If not see Fake the 64-bit offset by zero-extending it. */ \ fputs ("\t.secrel32\t", FILE); \ assemble_name (FILE, LABEL); \ + if ((OFFSET) != 0) \ + fprintf (FILE, "+" HOST_WIDE_INT_PRINT_DEC, \ + (HOST_WIDE_INT) (OFFSET)) \ fputs ("\n\t.long\t0", FILE); \ break; \ default: \ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a229a738399..60b81bbb8ab 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2162,45 +2162,45 @@ const struct processor_costs *ix86_tune_cost = &pentium_cost; const struct processor_costs *ix86_cost = &pentium_cost; /* Processor feature/optimization bitmasks. */ -#define m_386 (1<<PROCESSOR_I386) -#define m_486 (1<<PROCESSOR_I486) -#define m_PENT (1<<PROCESSOR_PENTIUM) -#define m_LAKEMONT (1<<PROCESSOR_LAKEMONT) -#define m_PPRO (1<<PROCESSOR_PENTIUMPRO) -#define m_PENT4 (1<<PROCESSOR_PENTIUM4) -#define m_NOCONA (1<<PROCESSOR_NOCONA) +#define m_386 (1U<<PROCESSOR_I386) +#define m_486 (1U<<PROCESSOR_I486) +#define m_PENT (1U<<PROCESSOR_PENTIUM) +#define m_LAKEMONT (1U<<PROCESSOR_LAKEMONT) +#define m_PPRO (1U<<PROCESSOR_PENTIUMPRO) +#define m_PENT4 (1U<<PROCESSOR_PENTIUM4) +#define m_NOCONA (1U<<PROCESSOR_NOCONA) #define m_P4_NOCONA (m_PENT4 | m_NOCONA) -#define m_CORE2 (1<<PROCESSOR_CORE2) -#define m_NEHALEM (1<<PROCESSOR_NEHALEM) -#define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE) -#define m_HASWELL (1<<PROCESSOR_HASWELL) +#define m_CORE2 (1U<<PROCESSOR_CORE2) +#define m_NEHALEM (1U<<PROCESSOR_NEHALEM) +#define m_SANDYBRIDGE (1U<<PROCESSOR_SANDYBRIDGE) +#define m_HASWELL (1U<<PROCESSOR_HASWELL) #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL) -#define m_BONNELL (1<<PROCESSOR_BONNELL) -#define m_SILVERMONT (1<<PROCESSOR_SILVERMONT) -#define m_KNL (1<<PROCESSOR_KNL) -#define m_SKYLAKE_AVX512 (1<<PROCESSOR_SKYLAKE_AVX512) -#define m_INTEL (1<<PROCESSOR_INTEL) - -#define m_GEODE (1<<PROCESSOR_GEODE) -#define m_K6 (1<<PROCESSOR_K6) +#define m_BONNELL (1U<<PROCESSOR_BONNELL) +#define m_SILVERMONT (1U<<PROCESSOR_SILVERMONT) +#define m_KNL (1U<<PROCESSOR_KNL) +#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512) +#define m_INTEL (1U<<PROCESSOR_INTEL) + +#define m_GEODE (1U<<PROCESSOR_GEODE) +#define m_K6 (1U<<PROCESSOR_K6) #define m_K6_GEODE (m_K6 | m_GEODE) -#define m_K8 (1<<PROCESSOR_K8) -#define m_ATHLON (1<<PROCESSOR_ATHLON) +#define m_K8 (1U<<PROCESSOR_K8) +#define m_ATHLON (1U<<PROCESSOR_ATHLON) #define m_ATHLON_K8 (m_K8 | m_ATHLON) -#define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10) -#define m_BDVER1 (1<<PROCESSOR_BDVER1) -#define m_BDVER2 (1<<PROCESSOR_BDVER2) -#define m_BDVER3 (1<<PROCESSOR_BDVER3) -#define m_BDVER4 (1<<PROCESSOR_BDVER4) -#define m_ZNVER1 (1<<PROCESSOR_ZNVER1) -#define m_BTVER1 (1<<PROCESSOR_BTVER1) -#define m_BTVER2 (1<<PROCESSOR_BTVER2) +#define m_AMDFAM10 (1U<<PROCESSOR_AMDFAM10) +#define m_BDVER1 (1U<<PROCESSOR_BDVER1) +#define m_BDVER2 (1U<<PROCESSOR_BDVER2) +#define m_BDVER3 (1U<<PROCESSOR_BDVER3) +#define m_BDVER4 (1U<<PROCESSOR_BDVER4) +#define m_ZNVER1 (1U<<PROCESSOR_ZNVER1) +#define m_BTVER1 (1U<<PROCESSOR_BTVER1) +#define m_BTVER2 (1U<<PROCESSOR_BTVER2) #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4) #define m_BTVER (m_BTVER1 | m_BTVER2) #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \ | m_ZNVER1) -#define m_GENERIC (1<<PROCESSOR_GENERIC) +#define m_GENERIC (1U<<PROCESSOR_GENERIC) const char* ix86_tune_feature_names[X86_TUNE_LAST] = { #undef DEF_TUNE @@ -4516,6 +4516,7 @@ ix86_parse_stringop_strategy_string (char *strategy_str, bool is_memset) const struct stringop_algs *default_algs; stringop_size_range input_ranges[MAX_STRINGOP_ALGS]; char *curr_range_str, *next_range_str; + const char *opt = is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="; int i = 0, n = 0; if (is_memset) @@ -4537,15 +4538,13 @@ ix86_parse_stringop_strategy_string (char *strategy_str, bool is_memset) if (3 != sscanf (curr_range_str, "%20[^:]:%d:%10s", alg_name, &maxs, align)) { - error ("wrong arg %s to option %s", curr_range_str, - is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="); + error ("wrong argument %qs to option %qs", curr_range_str, opt); return; } if (n > 0 && (maxs < (input_ranges[n - 1].max + 1) && maxs != -1)) { - error ("size ranges of option %s should be increasing", - is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="); + error ("size ranges of option %qs should be increasing", opt); return; } @@ -4555,9 +4554,25 @@ ix86_parse_stringop_strategy_string (char *strategy_str, bool is_memset) if (i == last_alg) { - error ("wrong stringop strategy name %s specified for option %s", - alg_name, - is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="); + error ("wrong strategy name %qs specified for option %qs", + alg_name, opt); + + auto_vec <const char *> candidates; + for (i = 0; i < last_alg; i++) + if ((stringop_alg) i != rep_prefix_8_byte || TARGET_64BIT) + candidates.safe_push (stringop_alg_names[i]); + + char *s; + const char *hint + = candidates_list_and_hint (alg_name, s, candidates); + if (hint) + inform (input_location, + "valid arguments to %qs are: %s; did you mean %qs?", + opt, s, hint); + else + inform (input_location, "valid arguments to %qs are: %s", + opt, s); + XDELETEVEC (s); return; } @@ -4565,10 +4580,8 @@ ix86_parse_stringop_strategy_string (char *strategy_str, bool is_memset) && !TARGET_64BIT) { /* rep; movq isn't available in 32-bit code. */ - error ("stringop strategy name %s specified for option %s " - "not supported for 32-bit code", - alg_name, - is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="); + error ("strategy name %qs specified for option %qs " + "not supported for 32-bit code", alg_name, opt); return; } @@ -4580,8 +4593,7 @@ ix86_parse_stringop_strategy_string (char *strategy_str, bool is_memset) input_ranges[n].noalign = true; else { - error ("unknown alignment %s specified for option %s", - align, is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="); + error ("unknown alignment %qs specified for option %qs", align, opt); return; } n++; @@ -4592,15 +4604,13 @@ ix86_parse_stringop_strategy_string (char *strategy_str, bool is_memset) if (input_ranges[n - 1].max != -1) { error ("the max value for the last size range should be -1" - " for option %s", - is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="); + " for option %qs", opt); return; } if (n > MAX_STRINGOP_ALGS) { - error ("too many size ranges specified in option %s", - is_memset ? "-mmemset_strategy=" : "-mmemcpy_strategy="); + error ("too many size ranges specified in option %qs", opt); return; } @@ -4731,9 +4741,6 @@ ix86_option_override_internal (bool main_args_p, int i; unsigned int ix86_arch_mask; const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL); - const char *prefix; - const char *suffix; - const char *sw; #define PTA_3DNOW (HOST_WIDE_INT_1 << 0) #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1) @@ -5031,21 +5038,6 @@ ix86_option_override_internal (bool main_args_p, int const pta_size = ARRAY_SIZE (processor_alias_table); - /* Set up prefix/suffix so the error messages refer to either the command - line argument, or the attribute(target). */ - if (main_args_p) - { - prefix = "-m"; - suffix = ""; - sw = "switch"; - } - else - { - prefix = "option(\""; - suffix = "\")"; - sw = "attribute"; - } - /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */ if (TARGET_64BIT_DEFAULT && !TARGET_64BIT_P (opts->x_ix86_isa_flags)) @@ -5118,9 +5110,13 @@ ix86_option_override_internal (bool main_args_p, opts->x_ix86_tune_string = "generic"; } else if (!strcmp (opts->x_ix86_tune_string, "x86-64")) - warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated; use " - "%stune=k8%s or %stune=generic%s instead as appropriate", - prefix, suffix, prefix, suffix, prefix, suffix); + warning (OPT_Wdeprecated, + main_args_p + ? "%<-mtune=x86-64%> is deprecated; use %<-mtune=k8%> " + "or %<-mtune=generic%> instead as appropriate" + : "%<target(\"tune=x86-64\")%> is deprecated; use " + "%<target(\"tune=k8\")%> or %<target(\"tune=generic\")%> " + "instead as appropriate"); } else { @@ -5474,14 +5470,48 @@ ix86_option_override_internal (bool main_args_p, error ("Intel MPX does not support x32"); if (!strcmp (opts->x_ix86_arch_string, "generic")) - error ("generic CPU can be used only for %stune=%s %s", - prefix, suffix, sw); + error (main_args_p + ? "%<generic%> CPU can be used only for %<-mtune=%> switch" + : "%<generic%> CPU can be used only for " + "%<target(\"tune=\")%> attribute"); else if (!strcmp (opts->x_ix86_arch_string, "intel")) - error ("intel CPU can be used only for %stune=%s %s", - prefix, suffix, sw); + error (main_args_p + ? "%<intel%> CPU can be used only for %<-mtune=%> switch" + : "%<intel%> CPU can be used only for " + "%<target(\"tune=\")%> attribute"); else if (i == pta_size) - error ("bad value (%s) for %sarch=%s %s", - opts->x_ix86_arch_string, prefix, suffix, sw); + { + error (main_args_p + ? "bad value (%qs) for %<-march=%> switch" + : "bad value (%qs) for %<target(\"arch=\")%> attribute", + opts->x_ix86_arch_string); + + auto_vec <const char *> candidates; + for (i = 0; i < pta_size; i++) + if (strcmp (processor_alias_table[i].name, "generic") + && strcmp (processor_alias_table[i].name, "intel") + && (!TARGET_64BIT_P (opts->x_ix86_isa_flags) + || (processor_alias_table[i].flags & PTA_64BIT))) + candidates.safe_push (processor_alias_table[i].name); + + char *s; + const char *hint + = candidates_list_and_hint (opts->x_ix86_arch_string, s, candidates); + if (hint) + inform (input_location, + main_args_p + ? "valid arguments to %<-march=%> switch are: " + "%s; did you mean %qs?" + : "valid arguments to %<target(\"arch=\")%> attribute are: " + "%s; did you mean %qs?", s, hint); + else + inform (input_location, + main_args_p + ? "valid arguments to %<-march=%> switch are: %s" + : "valid arguments to %<target(\"arch=\")%> attribute are: %s", + s); + XDELETEVEC (s); + } ix86_arch_mask = 1u << ix86_arch; for (i = 0; i < X86_ARCH_LAST; ++i) @@ -5523,8 +5553,36 @@ ix86_option_override_internal (bool main_args_p, } if (ix86_tune_specified && i == pta_size) - error ("bad value (%s) for %stune=%s %s", - opts->x_ix86_tune_string, prefix, suffix, sw); + { + error (main_args_p + ? "bad value (%qs) for %<-mtune=%> switch" + : "bad value (%qs) for %<target(\"tune=\")%> attribute", + opts->x_ix86_tune_string); + + auto_vec <const char *> candidates; + for (i = 0; i < pta_size; i++) + if (!TARGET_64BIT_P (opts->x_ix86_isa_flags) + || (processor_alias_table[i].flags & PTA_64BIT)) + candidates.safe_push (processor_alias_table[i].name); + + char *s; + const char *hint + = candidates_list_and_hint (opts->x_ix86_tune_string, s, candidates); + if (hint) + inform (input_location, + main_args_p + ? "valid arguments to %<-mtune=%> switch are: " + "%s; did you mean %qs?" + : "valid arguments to %<target(\"tune=\")%> attribute are: " + "%s; did you mean %qs?", s, hint); + else + inform (input_location, + main_args_p + ? "valid arguments to %<-mtune=%> switch are: %s" + : "valid arguments to %<target(\"tune=\")%> attribute are: %s", + s); + XDELETEVEC (s); + } set_ix86_tune_features (ix86_tune, opts->x_ix86_dump_tunes); @@ -5623,7 +5681,9 @@ ix86_option_override_internal (bool main_args_p, & ~opts->x_ix86_isa_flags_explicit); if (TARGET_RTD_P (opts->x_target_flags)) - warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix); + warning (0, + main_args_p ? "%<-mrtd%> is ignored in 64bit mode" + : "%<target(\"rtd\")%> is ignored in 64bit mode"); } else { @@ -5744,7 +5804,9 @@ ix86_option_override_internal (bool main_args_p, /* Accept -msseregparm only if at least SSE support is enabled. */ if (TARGET_SSEREGPARM_P (opts->x_target_flags) && ! TARGET_SSE_P (opts->x_ix86_isa_flags)) - error ("%ssseregparm%s used without SSE enabled", prefix, suffix); + error (main_args_p + ? "%<-msseregparm%> used without SSE enabled" + : "%<target(\"sseregparm\")%> used without SSE enabled"); if (opts_set->x_ix86_fpmath) { @@ -5809,8 +5871,12 @@ ix86_option_override_internal (bool main_args_p, && !(opts->x_target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)) { if (opts_set->x_target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) - warning (0, "stack probing requires %saccumulate-outgoing-args%s " - "for correctness", prefix, suffix); + warning (0, + main_args_p + ? "stack probing requires %<-maccumulate-outgoing-args%> " + "for correctness" + : "stack probing requires " + "%<target(\"accumulate-outgoing-args\")%> for correctness"); opts->x_target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS; } @@ -5820,8 +5886,11 @@ ix86_option_override_internal (bool main_args_p, && !(opts->x_target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)) { if (opts_set->x_target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) - warning (0, "fixed ebp register requires %saccumulate-outgoing-args%s", - prefix, suffix); + warning (0, + main_args_p + ? "fixed ebp register requires %<-maccumulate-outgoing-args%>" + : "fixed ebp register requires " + "%<target(\"accumulate-outgoing-args\")%>"); opts->x_target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS; } @@ -5957,11 +6026,12 @@ ix86_option_override_internal (bool main_args_p, if (!(opts_set->x_target_flags & MASK_STV)) opts->x_target_flags |= MASK_STV; /* Disable STV if -mpreferred-stack-boundary={2,3} or - -mincoming-stack-boundary={2,3} - the needed + -mincoming-stack-boundary={2,3} or -mstackrealign - the needed stack realignment will be extra cost the pass doesn't take into account and the pass can't realign the stack. */ if (ix86_preferred_stack_boundary < 128 - || ix86_incoming_stack_boundary < 128) + || ix86_incoming_stack_boundary < 128 + || opts->x_ix86_force_align_arg_pointer) opts->x_target_flags &= ~MASK_STV; if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL] && !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD)) @@ -34861,7 +34931,6 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V4DI_FTYPE_V4DI_V4DI_V4DI_INT_UQI: case V4SI_FTYPE_V4SI_V4SI_V4SI_INT_UQI: case V2DI_FTYPE_V2DI_V2DI_V2DI_INT_UQI: - nargs = 5; nargs = 5; mask_pos = 1; nargs_constant = 1; @@ -36107,7 +36176,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, error ("%qE needs isa option %s", fndecl, opts); free (opts); } - return const0_rtx; + return expand_call (exp, target, ignore); } switch (fcode) @@ -48562,14 +48631,6 @@ ix86_fn_abi_va_list (tree fndecl) static tree ix86_canonical_va_list_type (tree type) { - /* Resolve references and pointers to va_list type. */ - if (TREE_CODE (type) == MEM_REF) - type = TREE_TYPE (type); - else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type))) - type = TREE_TYPE (type); - else if (POINTER_TYPE_P (type) && TREE_CODE (TREE_TYPE (type)) == ARRAY_TYPE) - type = TREE_TYPE (type); - if (TARGET_64BIT) { if (lookup_attribute ("ms_abi va_list", TYPE_ATTRIBUTES (type))) @@ -50628,9 +50689,6 @@ ix86_addr_space_zero_address_valid (addr_space_t as) #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p -#undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_true - #undef TARGET_REGISTER_PRIORITY #define TARGET_REGISTER_PRIORITY ix86_register_priority diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 0deecb1b366..e3c9eadde85 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -799,7 +799,7 @@ sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq, - avx512vl,noavx512vl,x64_avx512dq" + avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw" (const_string "base")) (define_attr "enabled" "" @@ -812,6 +812,8 @@ (symbol_ref "TARGET_64BIT && TARGET_AVX") (eq_attr "isa" "x64_avx512dq") (symbol_ref "TARGET_64BIT && TARGET_AVX512DQ") + (eq_attr "isa" "x64_avx512bw") + (symbol_ref "TARGET_64BIT && TARGET_AVX512BW") (eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT") (eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2") (eq_attr "isa" "sse2_noavx") @@ -3735,12 +3737,14 @@ [(set (attr "isa") (cond [(eq_attr "alternative" "0,1,2") (const_string "nox64") - (eq_attr "alternative" "3,7,11") + (eq_attr "alternative" "3,7") (const_string "x64") (eq_attr "alternative" "8") (const_string "x64_sse4") (eq_attr "alternative" "10") (const_string "sse2") + (eq_attr "alternative" "11") + (const_string "x64_avx512bw") ] (const_string "*"))) (set (attr "type") @@ -3804,6 +3808,9 @@ (set (match_dup 4) (const_int 0))] "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") +(define_mode_attr kmov_isa + [(QI "avx512dq") (HI "avx512f") (SI "avx512bw") (DI "avx512bw")]) + (define_insn "zero_extend<mode>di2" [(set (match_operand:DI 0 "register_operand" "=r,*r") (zero_extend:DI @@ -3812,7 +3819,8 @@ "@ movz{<imodesuffix>l|x}\t{%1, %k0|%k0, %1} kmov<mskmodesuffix>\t{%1, %k0|%k0, %1}" - [(set_attr "type" "imovx,mskmov") + [(set_attr "isa" "*,<kmov_isa>") + (set_attr "type" "imovx,mskmov") (set_attr "mode" "SI")]) (define_expand "zero_extend<mode>si2" @@ -3863,7 +3871,8 @@ "@ movz{<imodesuffix>l|x}\t{%1, %0|%0, %1} kmov<mskmodesuffix>\t{%1, %0|%0, %1}" - [(set_attr "type" "imovx,mskmov") + [(set_attr "isa" "*,<kmov_isa>") + (set_attr "type" "imovx,mskmov") (set_attr "mode" "SI,<MODE>")]) (define_expand "zero_extendqihi2" @@ -3914,6 +3923,7 @@ movz{bl|x}\t{%1, %k0|%k0, %1} kmovb\t{%1, %k0|%k0, %1}" [(set_attr "type" "imovx,mskmov") + (set_attr "isa" "*,avx512dq") (set_attr "mode" "SI,QI")]) (define_insn_and_split "*zext<mode>_doubleword_and" diff --git a/gcc/config/i386/linux-common.h b/gcc/config/i386/linux-common.h index 4b9910fa902..22731706a25 100644 --- a/gcc/config/i386/linux-common.h +++ b/gcc/config/i386/linux-common.h @@ -79,13 +79,23 @@ along with GCC; see the file COPYING3. If not see #endif #endif +#ifdef HAVE_LD_PUSHPOPSTATE_SUPPORT +#define MPX_LD_AS_NEEDED_GUARD_PUSH "--push-state --no-as-needed" +#define MPX_LD_AS_NEEDED_GUARD_POP "--pop-state" +#else +#define MPX_LD_AS_NEEDED_GUARD_PUSH "" +#define MPX_LD_AS_NEEDED_GUARD_POP "" +#endif + #ifndef LIBMPX_SPEC #if defined(HAVE_LD_STATIC_DYNAMIC) #define LIBMPX_SPEC "\ %{mmpx:%{fcheck-pointer-bounds:\ %{static:--whole-archive -lmpx --no-whole-archive" LIBMPX_LIBS "}\ %{!static:%{static-libmpx:" LD_STATIC_OPTION " --whole-archive}\ - -lmpx %{static-libmpx:--no-whole-archive " LD_DYNAMIC_OPTION \ + %{!static-libmpx:" MPX_LD_AS_NEEDED_GUARD_PUSH "} -lmpx \ + %{!static-libmpx:" MPX_LD_AS_NEEDED_GUARD_POP "} \ + %{static-libmpx:--no-whole-archive " LD_DYNAMIC_OPTION \ LIBMPX_LIBS "}}}}" #else #define LIBMPX_SPEC "\ @@ -98,8 +108,8 @@ along with GCC; see the file COPYING3. If not see #define LIBMPXWRAPPERS_SPEC "\ %{mmpx:%{fcheck-pointer-bounds:%{!fno-chkp-use-wrappers:\ %{static:-lmpxwrappers}\ - %{!static:%{static-libmpxwrappers:" LD_STATIC_OPTION " --whole-archive}\ - -lmpxwrappers %{static-libmpxwrappers:--no-whole-archive "\ + %{!static:%{static-libmpxwrappers:" LD_STATIC_OPTION "}\ + -lmpxwrappers %{static-libmpxwrappers: "\ LD_DYNAMIC_OPTION "}}}}}" #else #define LIBMPXWRAPPERS_SPEC "\ diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 31a87b913b2..8c7a14d9022 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -535,15 +535,15 @@ DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi", on simulation result. But after P4 was made, no performance benefit was observed with branch hints. It also increases the code size. As a result, icc never generates branch hints. */ -DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0) +DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0U) /* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */ -DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0) +DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0U) /* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme is usually used for RISC targets. */ -DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0) +DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0U) /* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based on hardware capabilities. Bdver3 hardware has a loop buffer which makes diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index ebd2c86b8d8..5f0bf43a103 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -603,6 +603,9 @@ static const struct attribute_spec ia64_attribute_table[] = #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_CANNOT_FORCE_CONST_MEM #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index 4e1b7af6ab7..ac0cb864209 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -961,10 +961,8 @@ enum reg_class {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ } -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It - specifies the initial difference between the specified pair of - registers. This macro must be defined if `ELIMINABLE_REGS' is - defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) @@ -1583,11 +1581,14 @@ do { \ /* Use section-relative relocations for debugging offsets. Unlike other targets that fake this by putting the section VMA at 0, IA-64 has proper relocations for them. */ -#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION) \ +#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, OFFSET, SECTION) \ do { \ fputs (integer_asm_op (SIZE, FALSE), FILE); \ fputs ("@secrel(", FILE); \ assemble_name (FILE, LABEL); \ + if ((OFFSET) != 0) \ + fprintf (FILE, "+" HOST_WIDE_INT_PRINT_DEC, \ + (HOST_WIDE_INT) (OFFSET)); \ fputc (')', FILE); \ } while (0) diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c index 73b9cdb3fe0..c7e5f199b8f 100644 --- a/gcc/config/iq2000/iq2000.c +++ b/gcc/config/iq2000/iq2000.c @@ -237,6 +237,9 @@ static bool iq2000_print_operand_punct_valid_p (unsigned char code); #undef TARGET_EXPAND_BUILTIN_VA_START #define TARGET_EXPAND_BUILTIN_VA_START iq2000_va_start +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P iq2000_legitimate_address_p diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c index 4a8079f4a74..8a102207f0d 100644 --- a/gcc/config/lm32/lm32.c +++ b/gcc/config/lm32/lm32.c @@ -99,6 +99,8 @@ static void lm32_function_arg_advance (cumulative_args_t cum, #define TARGET_MAX_ANCHOR_OFFSET 0x7fff #undef TARGET_CAN_ELIMINATE #define TARGET_CAN_ELIMINATE lm32_can_eliminate +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P lm32_legitimate_address_p diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 6f6d7e4e45e..1db1ef7ade1 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -1632,6 +1632,9 @@ m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval) #undef A0 } +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + /* Addressing Modes */ /* The r8c/m32c family supports a wide range of non-orthogonal diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index b40c53ca189..943f8c7e253 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -119,6 +119,9 @@ static const struct attribute_spec m32r_attribute_table[] = #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P m32r_attribute_identifier +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p #undef TARGET_LEGITIMIZE_ADDRESS diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 2ff4a459dc4..cd74cfcf3b5 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -581,15 +581,6 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; /* Eliminating the frame and arg pointers. */ -#if 0 -/* C statement to store the difference between the frame pointer - and the stack pointer values immediately after the function prologue. - If `ELIMINABLE_REGS' is defined, this macro will be not be used and - need not be defined. */ -#define INITIAL_FRAME_POINTER_OFFSET(VAR) \ -((VAR) = m32r_compute_frame_size (get_frame_size ())) -#endif - /* If defined, this macro specifies a table of register pairs used to eliminate unneeded registers that point into the stack frame. If it is not defined, the only elimination attempted by the compiler @@ -604,10 +595,8 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It - specifies the initial difference between the specified pair of - registers. This macro must be defined if `ELIMINABLE_REGS' is - defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ do \ diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 7cee0f59529..a104193c23c 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -289,6 +289,9 @@ static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel #endif +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c index c9d0506afd5..3afe42c0c86 100644 --- a/gcc/config/mcore/mcore.c +++ b/gcc/config/mcore/mcore.c @@ -232,6 +232,9 @@ static const struct attribute_spec mcore_attribute_table[] = #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P mcore_legitimate_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_WARN_FUNC_RETURN #define TARGET_WARN_FUNC_RETURN mcore_warn_func_return diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c index 735dff52db2..e32fa0eca75 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c @@ -3810,6 +3810,9 @@ microblaze_machine_dependent_reorg (void) #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P microblaze_legitimate_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c index 3fffdc2e9af..bf06e3b1933 100644 --- a/gcc/config/mmix/mmix.c +++ b/gcc/config/mmix/mmix.c @@ -260,6 +260,9 @@ static void mmix_conditional_register_usage (void); #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS mmix_preferred_output_reload_class +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P mmix_legitimate_address_p #undef TARGET_LEGITIMATE_CONSTANT_P diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index 6e590cd6a33..e384796873a 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -3379,6 +3379,9 @@ mn10300_reorg (void) #undef TARGET_CASE_VALUES_THRESHOLD #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p #undef TARGET_DELEGITIMIZE_ADDRESS diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c index 4e38a57f828..9d376f1959b 100644 --- a/gcc/config/moxie/moxie.c +++ b/gcc/config/moxie/moxie.c @@ -624,6 +624,9 @@ moxie_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, #undef TARGET_FUNCTION_ARG_ADVANCE #define TARGET_FUNCTION_ARG_ADVANCE moxie_function_arg_advance +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P moxie_legitimate_address_p diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h index b9cb38bf139..204e23c405b 100644 --- a/gcc/config/moxie/moxie.h +++ b/gcc/config/moxie/moxie.h @@ -243,8 +243,6 @@ enum reg_class pointer to a smaller address. */ #define STACK_GROWS_DOWNWARD 1 -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0 - /* Offset from the frame pointer to the first local variable slot to be allocated. */ #define STARTING_FRAME_OFFSET 0 @@ -386,10 +384,8 @@ enum reg_class {{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It - specifies the initial difference between the specified pair of - registers. This macro must be defined if `ELIMINABLE_REGS' is - defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ do { \ (OFFSET) = moxie_initial_elimination_offset ((FROM), (TO)); \ diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index dba4d198776..93431765562 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -1490,6 +1490,9 @@ msp430_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, return addr; } +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + /* Addressing Modes */ #undef TARGET_LEGITIMATE_ADDRESS_P @@ -2108,6 +2111,13 @@ msp430_start_function (FILE *file, const char *name, tree decl) { char buf[101]; + /* Interrupt vector sections should be unique, but use of weak + functions implies multiple definitions. */ + if (DECL_WEAK (decl)) + { + error ("argument to interrupt attribute is unsupported for weak functions"); + } + intr_vector = TREE_VALUE (intr_vector); /* The interrupt attribute has a vector value. Turn this into a diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index bdec202660f..720dd7cc2ef 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -1459,7 +1459,7 @@ (match_operand 1 "immediate_operand" "i") ] UNS_DELAY_32X)] "" - "PUSHM.A #2,r13 + "PUSHM.A #2,r14 MOV.W %A0, r13 MOV.W %B0, r14 1: SUB.W #1, r13 @@ -1467,7 +1467,7 @@ JNE 1b TST.W r13 JNE 1b - POPM.A #2,r13" + POPM.A #2,r14" ) (define_insn "delay_cycles_16" diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index c47c122a817..8dbeba56576 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -3547,9 +3547,6 @@ nds32_target_alignment (rtx label) #undef TARGET_CLASS_MAX_NREGS #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs -#undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_true - #undef TARGET_REGISTER_PRIORITY #define TARGET_REGISTER_PRIORITY nds32_register_priority diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c index 18fcbb3266e..632adadb072 100644 --- a/gcc/config/nios2/nios2.c +++ b/gcc/config/nios2/nios2.c @@ -5038,6 +5038,9 @@ nios2_adjust_reg_alloc_order (void) #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P nios2_legitimate_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_PREFERRED_RELOAD_CLASS #define TARGET_PREFERRED_RELOAD_CLASS nios2_preferred_reload_class diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index 23b5078919e..16e04a4f726 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -4856,6 +4856,9 @@ nvptx_goacc_reduction (gcall *call) #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE nvptx_attribute_table +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P nvptx_legitimate_address_p diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index e48412de6a6..d117343c531 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -541,7 +541,7 @@ [(set (pc) (if_then_else (match_operator 0 "nvptx_comparison_operator" [(match_operand:HSDIM 1 "nvptx_register_operand" "") - (match_operand:HSDIM 2 "nvptx_register_operand" "")]) + (match_operand:HSDIM 2 "nvptx_nonmemory_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] "" @@ -556,7 +556,7 @@ [(set (pc) (if_then_else (match_operator 0 "nvptx_float_comparison_operator" [(match_operand:SDFM 1 "nvptx_register_operand" "") - (match_operand:SDFM 2 "nvptx_register_operand" "")]) + (match_operand:SDFM 2 "nvptx_nonmemory_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] "" diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 251c1ada392..18b73249d27 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -397,6 +397,9 @@ static size_t n_deferred_plabels = 0; #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P pa_legitimate_address_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + struct gcc_target targetm = TARGET_INITIALIZER; /* Parse the -mfixed-range= option string. */ diff --git a/gcc/config/pa/pa64-linux.h b/gcc/config/pa/pa64-linux.h index 540bfa64c6c..4bf1f795c5e 100644 --- a/gcc/config/pa/pa64-linux.h +++ b/gcc/config/pa/pa64-linux.h @@ -28,10 +28,8 @@ along with GCC; see the file COPYING3. If not see {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ } -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It - specifies the initial difference between the specified pair of - registers. This macro must be defined if `ELIMINABLE_REGS' is - defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ do \ { \ diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index 35d57c72488..7fa08cbf66a 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -208,6 +208,9 @@ static bool pdp11_scalar_mode_supported_p (machine_mode); #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c index 3ddb19865b8..ecbf6f9b5f9 100644 --- a/gcc/config/rl78/rl78.c +++ b/gcc/config/rl78/rl78.c @@ -1071,6 +1071,9 @@ rl78_is_legitimate_constant (machine_mode mode ATTRIBUTE_UNUSED, rtx x ATTRIBUTE return true; } +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P rl78_as_legitimate_address diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index c39a0b655b4..857f257edda 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -371,7 +371,7 @@ (define_insn "get_vrsave_internal" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))] + (unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))] "TARGET_ALTIVEC" { if (TARGET_MACHO) @@ -383,9 +383,9 @@ (define_insn "*set_vrsave_internal" [(match_parallel 0 "vrsave_operation" - [(set (reg:SI 109) + [(set (reg:SI VRSAVE_REGNO) (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") - (reg:SI 109)] UNSPECV_SET_VRSAVE))])] + (reg:SI VRSAVE_REGNO)] UNSPECV_SET_VRSAVE))])] "TARGET_ALTIVEC" { if (TARGET_MACHO) @@ -397,7 +397,7 @@ (define_insn "*save_world" [(match_parallel 0 "save_world_operation" - [(clobber (reg:SI 65)) + [(clobber (reg:SI LR_REGNO)) (use (match_operand:SI 1 "call_operand" "s"))])] "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT" "bl %z1" @@ -407,7 +407,7 @@ (define_insn "*restore_world" [(match_parallel 0 "restore_world_operation" [(return) - (use (reg:SI 65)) + (use (reg:SI LR_REGNO)) (use (match_operand:SI 1 "call_operand" "s")) (clobber (match_operand:SI 2 "gpc_reg_operand" "=r"))])] "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT" @@ -421,7 +421,7 @@ ;; to describe the operation to dwarf2out_frame_debug_expr. (define_insn "*save_vregs_<mode>_r11" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (clobber (reg:P 11)) (use (reg:P 0)) @@ -435,7 +435,7 @@ (define_insn "*save_vregs_<mode>_r12" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (clobber (reg:P 12)) (use (reg:P 0)) @@ -449,7 +449,7 @@ (define_insn "*restore_vregs_<mode>_r11" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (clobber (reg:P 11)) (use (reg:P 0)) @@ -463,7 +463,7 @@ (define_insn "*restore_vregs_<mode>_r12" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (clobber (reg:P 12)) (use (reg:P 0)) @@ -508,7 +508,7 @@ (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDU)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "<VI_unit>" "vaddu<VI_char>s %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -518,7 +518,7 @@ (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "vadds<VI_char>s %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -554,7 +554,7 @@ (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBU)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "vsubu<VI_char>s %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -564,7 +564,7 @@ (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "vsubs<VI_char>s %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -830,7 +830,7 @@ (match_operand:V8HI 2 "register_operand" "v") (match_operand:V4SI 3 "register_operand" "v")] UNSPEC_VMSUMUHS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vmsumuhs %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) @@ -841,7 +841,7 @@ (match_operand:V8HI 2 "register_operand" "v") (match_operand:V4SI 3 "register_operand" "v")] UNSPEC_VMSUMSHS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vmsumshs %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) @@ -902,7 +902,7 @@ (match_operand:V8HI 2 "register_operand" "v") (match_operand:V8HI 3 "register_operand" "v")] UNSPEC_VMHADDSHS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vmhaddshs %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) @@ -913,7 +913,7 @@ (match_operand:V8HI 2 "register_operand" "v") (match_operand:V8HI 3 "register_operand" "v")] UNSPEC_VMHRADDSHS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vmhraddshs %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) @@ -1699,7 +1699,7 @@ (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUM4UBS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vsum4ubs %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -1709,7 +1709,7 @@ (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUM4S)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vsum4s<VI_char>s %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -1722,7 +1722,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUM2SWS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) (clobber (match_scratch:V4SI 3 "=v"))] "TARGET_ALTIVEC" { @@ -1743,7 +1743,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUMSWS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR)) (clobber (match_scratch:V4SI 3 "=v"))] "TARGET_ALTIVEC" { @@ -1764,7 +1764,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUMSWS_DIRECT)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vsumsws %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -2124,7 +2124,7 @@ (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_VCTUXS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vctuxs %0,%1,%2" [(set_attr "type" "vecfloat")]) @@ -2134,7 +2134,7 @@ (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_VCTSXS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] + (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] "TARGET_ALTIVEC" "vctsxs %0,%1,%2" [(set_attr "type" "vecfloat")]) @@ -2274,7 +2274,7 @@ ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*altivec_vcmpequ<VI_char>_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2286,7 +2286,7 @@ [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgts<VI_char>_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2298,7 +2298,7 @@ [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgtu<VI_char>_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2310,7 +2310,7 @@ [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpeqfp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2322,7 +2322,7 @@ [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgtfp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2334,7 +2334,7 @@ [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgefp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v"))] UNSPEC_PREDICATE)) @@ -2346,7 +2346,7 @@ [(set_attr "type" "veccmp")]) (define_insn "altivec_vcmpbfp_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VCMPBFP)) @@ -2359,7 +2359,7 @@ [(set_attr "type" "veccmp")]) (define_insn "altivec_mtvscr" - [(set (reg:SI 110) + [(set (reg:SI VSCR_REGNO) (unspec_volatile:SI [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))] "TARGET_ALTIVEC" @@ -2368,7 +2368,7 @@ (define_insn "altivec_mfvscr" [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))] + (unspec_volatile:V8HI [(reg:SI VSCR_REGNO)] UNSPECV_MFVSCR))] "TARGET_ALTIVEC" "mfvscr %0" [(set_attr "type" "vecsimple")]) @@ -2757,7 +2757,8 @@ (unspec:VI [(match_dup 2) (match_operand:VI 1 "register_operand" "v")] UNSPEC_VSUBS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]) + (set (reg:SI VSCR_REGNO) + (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]) (set (match_operand:VI 0 "register_operand" "=v") (smax:VI (match_dup 1) (match_dup 3)))] "TARGET_ALTIVEC" @@ -3634,7 +3635,7 @@ (match_operand:V1TI 2 "register_operand" "") (match_operand:QI 3 "const_0_to_1_operand" "")] UNSPEC_BCD_ADD_SUB)) - (clobber (reg:CCFP 74))] + (clobber (reg:CCFP CR6_REGNO))] "TARGET_P8_VECTOR" "bcd<bcd_add_sub>. %0,%1,%2,%3" [(set_attr "length" "4") @@ -3646,7 +3647,7 @@ ;; probably should be one that can go in the VMX (Altivec) registers, so we ;; can't use DDmode or DFmode. (define_insn "*bcd<bcd_add_sub>_test" - [(set (reg:CCFP 74) + [(set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v") (match_operand:V1TI 2 "register_operand" "v") @@ -3665,7 +3666,7 @@ (match_operand:V1TI 2 "register_operand" "v") (match_operand:QI 3 "const_0_to_1_operand" "i")] UNSPEC_BCD_ADD_SUB)) - (set (reg:CCFP 74) + (set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_dup 1) (match_dup 2) @@ -3699,7 +3700,7 @@ [(set_attr "type" "integer")]) (define_expand "bcd<bcd_add_sub>_<code>" - [(parallel [(set (reg:CCFP 74) + [(parallel [(set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "") (match_operand:V1TI 2 "register_operand" "") @@ -3708,7 +3709,7 @@ (match_dup 4))) (clobber (match_scratch:V1TI 5 ""))]) (set (match_operand:SI 0 "register_operand" "") - (BCD_TEST:SI (reg:CCFP 74) + (BCD_TEST:SI (reg:CCFP CR6_REGNO) (const_int 0)))] "TARGET_P8_VECTOR" { @@ -3727,8 +3728,8 @@ (match_operand:V1TI 2 "register_operand" "") (match_operand:QI 3 "const_0_to_1_operand" "")] UNSPEC_BCD_ADD_SUB)) - (clobber (reg:CCFP 74))]) - (parallel [(set (reg:CCFP 74) + (clobber (reg:CCFP CR6_REGNO))]) + (parallel [(set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_dup 1) (match_dup 2) @@ -3742,7 +3743,7 @@ (match_dup 2) (match_dup 3)] UNSPEC_BCD_ADD_SUB)) - (set (reg:CCFP 74) + (set (reg:CCFP CR6_REGNO) (compare:CCFP (unspec:V2DF [(match_dup 1) (match_dup 2) diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 57ce30e0cd1..5870e0a762f 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -238,7 +238,7 @@ You should have received a copy of the GNU General Public License "") (define_expand "load_macho_picbase" - [(set (reg:SI 65) + [(set (reg:SI LR_REGNO) (unspec [(match_operand 0 "" "")] UNSPEC_LD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" @@ -252,7 +252,7 @@ You should have received a copy of the GNU General Public License }) (define_insn "load_macho_picbase_si" - [(set (reg:SI 65) + [(set (reg:SI LR_REGNO) (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") (pc)] UNSPEC_LD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" @@ -268,7 +268,7 @@ You should have received a copy of the GNU General Public License (set_attr "length" "4")]) (define_insn "load_macho_picbase_di" - [(set (reg:DI 65) + [(set (reg:DI LR_REGNO) (unspec:DI [(match_operand:DI 0 "immediate_operand" "s") (pc)] UNSPEC_LD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT" @@ -325,7 +325,7 @@ You should have received a copy of the GNU General Public License [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l")) (match_operand 1 "" "g,g,g,g")) (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) - (clobber (reg:SI 65))] + (clobber (reg:SI LR_REGNO))] "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT" { return "b%T0l"; @@ -337,7 +337,7 @@ You should have received a copy of the GNU General Public License [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s")) (match_operand 1 "" "g,g")) (use (match_operand:SI 2 "immediate_operand" "O,n")) - (clobber (reg:SI 65))] + (clobber (reg:SI LR_REGNO))] "(DEFAULT_ABI == ABI_DARWIN) && (INTVAL (operands[2]) & CALL_LONG) == 0" { @@ -355,7 +355,7 @@ You should have received a copy of the GNU General Public License (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l")) (match_operand 2 "" "g,g,g,g"))) (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) - (clobber (reg:SI 65))] + (clobber (reg:SI LR_REGNO))] "DEFAULT_ABI == ABI_DARWIN" { return "b%T1l"; @@ -368,7 +368,7 @@ You should have received a copy of the GNU General Public License (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s")) (match_operand 2 "" "g,g"))) (use (match_operand:SI 3 "immediate_operand" "O,n")) - (clobber (reg:SI 65))] + (clobber (reg:SI LR_REGNO))] "(DEFAULT_ABI == ABI_DARWIN) && (INTVAL (operands[3]) & CALL_LONG) == 0" { @@ -382,7 +382,7 @@ You should have received a copy of the GNU General Public License (set_attr "length" "4,8")]) (define_expand "reload_macho_picbase" - [(set (reg:SI 65) + [(set (reg:SI LR_REGNO) (unspec [(match_operand 0 "" "")] UNSPEC_RELD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" @@ -396,7 +396,7 @@ You should have received a copy of the GNU General Public License }) (define_insn "reload_macho_picbase_si" - [(set (reg:SI 65) + [(set (reg:SI LR_REGNO) (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") (pc)] UNSPEC_RELD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" @@ -419,7 +419,7 @@ You should have received a copy of the GNU General Public License (set_attr "length" "4")]) (define_insn "reload_macho_picbase_di" - [(set (reg:DI 65) + [(set (reg:DI LR_REGNO) (unspec:DI [(match_operand:DI 0 "immediate_operand" "s") (pc)] UNSPEC_RELD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT" diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 2f15a053075..ed24d96006f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -8409,7 +8409,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, pointer, so it works with both GPRs and VSX registers. */ /* Make sure both operands are registers. */ else if (GET_CODE (x) == PLUS - && (mode != TImode || !TARGET_QUAD_MEMORY)) + && (mode != TImode || !TARGET_VSX_TIMODE)) return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), force_reg (Pmode, XEXP (x, 1))); @@ -9418,12 +9418,16 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict) return 1; } - /* For TImode, if we have load/store quad and TImode in VSX registers, only - allow register indirect addresses. This will allow the values to go in - either GPRs or VSX registers without reloading. The vector types would - tend to go into VSX registers, so we allow REG+REG, while TImode seems + /* For TImode, if we have TImode in VSX registers, only allow register + indirect addresses. This will allow the values to go in either GPRs + or VSX registers without reloading. The vector types would tend to + go into VSX registers, so we allow REG+REG, while TImode seems somewhat split, in that some uses are GPR based, and some VSX based. */ - if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE) + /* FIXME: We could loosen this by changing the following to + if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE) + but currently we cannot allow REG+REG addressing for TImode. See + PR72827 for complete details on how this ends up hoodwinking DSE. */ + if (mode == TImode && TARGET_VSX_TIMODE) return 0; /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ if (! reg_ok_strict @@ -39097,10 +39101,15 @@ rtx_is_swappable_p (rtx op, unsigned int *special) handling. */ if (GET_CODE (XEXP (op, 0)) == CONST_INT) return 1; - else if (GET_CODE (XEXP (op, 0)) == REG + else if (REG_P (XEXP (op, 0)) && GET_MODE_INNER (GET_MODE (op)) == GET_MODE (XEXP (op, 0))) /* This catches V2DF and V2DI splat, at a minimum. */ return 1; + else if (GET_CODE (XEXP (op, 0)) == TRUNCATE + && REG_P (XEXP (XEXP (op, 0), 0)) + && GET_MODE_INNER (GET_MODE (op)) == GET_MODE (XEXP (op, 0))) + /* This catches splat of a truncated value. */ + return 1; else if (GET_CODE (XEXP (op, 0)) == VEC_SELECT) /* If the duplicated item is from a select, defer to the select processing to see if we can change the lane for the splat. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d54eaa1b5a2..446d388469e 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1958,7 +1958,7 @@ typedef struct rs6000_args #define TRAMPOLINE_SIZE rs6000_trampoline_size () /* Definitions for __builtin_return_address and __builtin_frame_address. - __builtin_return_address (0) should give link register (65), enable + __builtin_return_address (0) should give link register (LR_REGNO), enable this. */ /* This should be uncommented, so that the link register is used, but currently this would result in unmatched insns and spilling fixed diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 560cf1fd740..8d09c8cd2dd 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4323,13 +4323,15 @@ ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal ;; hardware division. This is only done before register allocation and with ;; -ffast-math. This must appear before the divsf3/divdf3 insns. +;; We used to also check optimize_insn_for_speed_p () but problems with guessed +;; frequencies (pr68212/pr77536) yields that unreliable so it was removed. (define_split [(set (match_operand:RECIPF 0 "gpc_reg_operand" "") (div:RECIPF (match_operand 1 "gpc_reg_operand" "") (match_operand 2 "gpc_reg_operand" "")))] "RS6000_RECIP_AUTO_RE_P (<MODE>mode) - && can_create_pseudo_p () && optimize_insn_for_speed_p () - && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math" + && can_create_pseudo_p () && flag_finite_math_only + && !flag_trapping_math && flag_reciprocal_math" [(const_int 0)] { rs6000_emit_swdiv (operands[0], operands[1], operands[2], true); @@ -12455,7 +12457,7 @@ (define_insn "*save_gpregs_<mode>_r11" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 11)) (set (match_operand:P 2 "memory_operand" "=m") @@ -12467,7 +12469,7 @@ (define_insn "*save_gpregs_<mode>_r12" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 12)) (set (match_operand:P 2 "memory_operand" "=m") @@ -12479,7 +12481,7 @@ (define_insn "*save_gpregs_<mode>_r1" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 1)) (set (match_operand:P 2 "memory_operand" "=m") @@ -12491,7 +12493,7 @@ (define_insn "*save_fpregs_<mode>_r11" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 11)) (set (match_operand:DF 2 "memory_operand" "=m") @@ -12503,7 +12505,7 @@ (define_insn "*save_fpregs_<mode>_r12" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 12)) (set (match_operand:DF 2 "memory_operand" "=m") @@ -12515,7 +12517,7 @@ (define_insn "*save_fpregs_<mode>_r1" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 1)) (set (match_operand:DF 2 "memory_operand" "=m") @@ -12620,141 +12622,139 @@ (define_insn "*restore_gpregs_<mode>_r11" [(match_parallel 0 "any_parallel_operand" - [(clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 11)) - (set (match_operand:P 3 "gpc_reg_operand" "=r") - (match_operand:P 4 "memory_operand" "m"))])] + [(clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 11)) + (set (match_operand:P 2 "gpc_reg_operand" "=r") + (match_operand:P 3 "memory_operand" "m"))])] "" - "bl %2" + "bl %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*restore_gpregs_<mode>_r12" [(match_parallel 0 "any_parallel_operand" - [(clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 12)) - (set (match_operand:P 3 "gpc_reg_operand" "=r") - (match_operand:P 4 "memory_operand" "m"))])] + [(clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 12)) + (set (match_operand:P 2 "gpc_reg_operand" "=r") + (match_operand:P 3 "memory_operand" "m"))])] "" - "bl %2" + "bl %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*restore_gpregs_<mode>_r1" [(match_parallel 0 "any_parallel_operand" - [(clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 1)) - (set (match_operand:P 3 "gpc_reg_operand" "=r") - (match_operand:P 4 "memory_operand" "m"))])] + [(clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 1)) + (set (match_operand:P 2 "gpc_reg_operand" "=r") + (match_operand:P 3 "memory_operand" "m"))])] "" - "bl %2" + "bl %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_gpregs_<mode>_r11" [(match_parallel 0 "any_parallel_operand" - [(return) - (clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 11)) - (set (match_operand:P 3 "gpc_reg_operand" "=r") - (match_operand:P 4 "memory_operand" "m"))])] + [(return) + (clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 11)) + (set (match_operand:P 2 "gpc_reg_operand" "=r") + (match_operand:P 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_gpregs_<mode>_r12" [(match_parallel 0 "any_parallel_operand" - [(return) - (clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 12)) - (set (match_operand:P 3 "gpc_reg_operand" "=r") - (match_operand:P 4 "memory_operand" "m"))])] + [(return) + (clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 12)) + (set (match_operand:P 2 "gpc_reg_operand" "=r") + (match_operand:P 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_gpregs_<mode>_r1" [(match_parallel 0 "any_parallel_operand" - [(return) - (clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 1)) - (set (match_operand:P 3 "gpc_reg_operand" "=r") - (match_operand:P 4 "memory_operand" "m"))])] + [(return) + (clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 1)) + (set (match_operand:P 2 "gpc_reg_operand" "=r") + (match_operand:P 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_fpregs_<mode>_r11" [(match_parallel 0 "any_parallel_operand" - [(return) - (clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 11)) - (set (match_operand:DF 3 "gpc_reg_operand" "=d") - (match_operand:DF 4 "memory_operand" "m"))])] + [(return) + (clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 11)) + (set (match_operand:DF 2 "gpc_reg_operand" "=d") + (match_operand:DF 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_fpregs_<mode>_r12" [(match_parallel 0 "any_parallel_operand" - [(return) - (clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 12)) - (set (match_operand:DF 3 "gpc_reg_operand" "=d") - (match_operand:DF 4 "memory_operand" "m"))])] + [(return) + (clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 12)) + (set (match_operand:DF 2 "gpc_reg_operand" "=d") + (match_operand:DF 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_fpregs_<mode>_r1" [(match_parallel 0 "any_parallel_operand" - [(return) - (clobber (match_operand:P 1 "register_operand" "=l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) - (use (reg:P 1)) - (set (match_operand:DF 3 "gpc_reg_operand" "=d") - (match_operand:DF 4 "memory_operand" "m"))])] + [(return) + (clobber (reg:P LR_REGNO)) + (use (match_operand:P 1 "symbol_ref_operand" "s")) + (use (reg:P 1)) + (set (match_operand:DF 2 "gpc_reg_operand" "=d") + (match_operand:DF 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_fpregs_aix_<mode>_r11" [(match_parallel 0 "any_parallel_operand" [(return) - (use (match_operand:P 1 "register_operand" "l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) + (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 11)) - (set (match_operand:DF 3 "gpc_reg_operand" "=d") - (match_operand:DF 4 "memory_operand" "m"))])] + (set (match_operand:DF 2 "gpc_reg_operand" "=d") + (match_operand:DF 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) (define_insn "*return_and_restore_fpregs_aix_<mode>_r1" [(match_parallel 0 "any_parallel_operand" [(return) - (use (match_operand:P 1 "register_operand" "l")) - (use (match_operand:P 2 "symbol_ref_operand" "s")) + (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 1)) - (set (match_operand:DF 3 "gpc_reg_operand" "=d") - (match_operand:DF 4 "memory_operand" "m"))])] + (set (match_operand:DF 2 "gpc_reg_operand" "=d") + (match_operand:DF 3 "memory_operand" "m"))])] "" - "b %2" + "b %1" [(set_attr "type" "branch") (set_attr "length" "4")]) diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 87fb787a1c1..4b2220d38bb 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -3464,7 +3464,7 @@ ;; Out-of-line prologues and epilogues. (define_insn "*save_gpregs_spe" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 11)) (set (match_operand:V2SI 2 "memory_operand" "=m") @@ -3476,7 +3476,7 @@ (define_insn "*restore_gpregs_spe" [(match_parallel 0 "any_parallel_operand" - [(clobber (reg:P 65)) + [(clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 11)) (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") @@ -3489,7 +3489,7 @@ (define_insn "*return_and_restore_gpregs_spe" [(match_parallel 0 "any_parallel_operand" [(return) - (clobber (reg:P 65)) + (clobber (reg:P LR_REGNO)) (use (match_operand:P 1 "symbol_ref_operand" "s")) (use (reg:P 11)) (set (match_operand:V2SI 2 "gpc_reg_operand" "=r") diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index fbfa9bf12e4..d42de0f9d3c 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -670,7 +670,7 @@ ;; setting CR6 to indicate a combined status (define_expand "vector_eq_<mode>_p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "") (match_operand:VEC_A 2 "vlogical_operand" ""))] UNSPEC_PREDICATE)) @@ -682,7 +682,7 @@ (define_expand "vector_gt_<mode>_p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "") (match_operand:VEC_A 2 "vlogical_operand" ""))] UNSPEC_PREDICATE)) @@ -694,7 +694,7 @@ (define_expand "vector_ge_<mode>_p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "") (match_operand:VEC_F 2 "vfloat_operand" ""))] UNSPEC_PREDICATE)) @@ -706,7 +706,7 @@ (define_expand "vector_gtu_<mode>_p" [(parallel - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" ""))] UNSPEC_PREDICATE)) @@ -720,14 +720,14 @@ (define_expand "cr6_test_for_zero" [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (reg:CC 74) + (eq:SI (reg:CC CR6_REGNO) (const_int 0)))] "TARGET_ALTIVEC || TARGET_VSX" "") (define_expand "cr6_test_for_zero_reverse" [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (reg:CC 74) + (eq:SI (reg:CC CR6_REGNO) (const_int 0))) (set (match_dup 0) (xor:SI (match_dup 0) @@ -737,14 +737,14 @@ (define_expand "cr6_test_for_lt" [(set (match_operand:SI 0 "register_operand" "=r") - (lt:SI (reg:CC 74) + (lt:SI (reg:CC CR6_REGNO) (const_int 0)))] "TARGET_ALTIVEC || TARGET_VSX" "") (define_expand "cr6_test_for_lt_reverse" [(set (match_operand:SI 0 "register_operand" "=r") - (lt:SI (reg:CC 74) + (lt:SI (reg:CC CR6_REGNO) (const_int 0))) (set (match_dup 0) (xor:SI (match_dup 0) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 60917c541c7..359e424d6b4 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1499,7 +1499,7 @@ ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*vsx_eq_<mode>_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] @@ -1512,7 +1512,7 @@ [(set_attr "type" "<VStype_simple>")]) (define_insn "*vsx_gt_<mode>_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] @@ -1525,7 +1525,7 @@ [(set_attr "type" "<VStype_simple>")]) (define_insn "*vsx_ge_<mode>_p" - [(set (reg:CC 74) + [(set (reg:CC CR6_REGNO) (unspec:CC [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index fecbb886d0f..f611dabd6ad 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -35,59 +35,6 @@ enum sh_function_kind { SFUNC_STATIC }; -/* Atomic model. */ -struct sh_atomic_model -{ - enum enum_type - { - none = 0, - soft_gusa, - hard_llcs, - soft_tcb, - soft_imask, - - num_models - }; - - /* If strict is set, disallow mixing of different models, as it would - happen on SH4A. */ - bool strict; - enum_type type; - - /* Name string as it was specified on the command line. */ - const char* name; - - /* Name string as it is used in C/C++ defines. */ - const char* cdef_name; - - /* GBR offset variable for TCB model. */ - int tcb_gbr_offset; -}; - -extern const sh_atomic_model& selected_atomic_model (void); - -/* Shortcuts to check the currently selected atomic model. */ -#define TARGET_ATOMIC_ANY \ - (selected_atomic_model ().type != sh_atomic_model::none) - -#define TARGET_ATOMIC_STRICT \ - (selected_atomic_model ().strict) - -#define TARGET_ATOMIC_SOFT_GUSA \ - (selected_atomic_model ().type == sh_atomic_model::soft_gusa) - -#define TARGET_ATOMIC_HARD_LLCS \ - (selected_atomic_model ().type == sh_atomic_model::hard_llcs) - -#define TARGET_ATOMIC_SOFT_TCB \ - (selected_atomic_model ().type == sh_atomic_model::soft_tcb) - -#define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \ - GEN_INT (selected_atomic_model ().tcb_gbr_offset) - -#define TARGET_ATOMIC_SOFT_IMASK \ - (selected_atomic_model ().type == sh_atomic_model::soft_imask) - #ifdef RTX_CODE extern rtx sh_fsca_sf2int (void); extern rtx sh_fsca_int2sf (void); diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 0403616785a..25b6cee5852 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -333,6 +333,63 @@ extern enum sh_divide_strategy_e sh_div_strategy; #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1 #endif +#ifdef __cplusplus + +/* Atomic model. */ +struct sh_atomic_model +{ + enum enum_type + { + none = 0, + soft_gusa, + hard_llcs, + soft_tcb, + soft_imask, + + num_models + }; + + /* If strict is set, disallow mixing of different models, as it would + happen on SH4A. */ + bool strict; + enum_type type; + + /* Name string as it was specified on the command line. */ + const char* name; + + /* Name string as it is used in C/C++ defines. */ + const char* cdef_name; + + /* GBR offset variable for TCB model. */ + int tcb_gbr_offset; +}; + +extern const sh_atomic_model& selected_atomic_model (void); + +/* Shortcuts to check the currently selected atomic model. */ +#define TARGET_ATOMIC_ANY \ + (selected_atomic_model ().type != sh_atomic_model::none) + +#define TARGET_ATOMIC_STRICT \ + (selected_atomic_model ().strict) + +#define TARGET_ATOMIC_SOFT_GUSA \ + (selected_atomic_model ().type == sh_atomic_model::soft_gusa) + +#define TARGET_ATOMIC_HARD_LLCS \ + (selected_atomic_model ().type == sh_atomic_model::hard_llcs) + +#define TARGET_ATOMIC_SOFT_TCB \ + (selected_atomic_model ().type == sh_atomic_model::soft_tcb) + +#define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \ + GEN_INT (selected_atomic_model ().tcb_gbr_offset) + +#define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + +#endif // __cplusplus + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 254b72298a3..1932b1bad78 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -827,6 +827,9 @@ char sparc_hard_reg_printed[8]; #define TARGET_MANGLE_TYPE sparc_mangle_type #endif +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index fc791f5515b..28173e5123c 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -7153,6 +7153,9 @@ static const struct attribute_spec spu_attribute_table[] = /* TARGET overrides. */ +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_ADDR_SPACE_POINTER_MODE #define TARGET_ADDR_SPACE_POINTER_MODE spu_addr_space_pointer_mode diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c index 50af15bd7cc..1eb95f57f9f 100644 --- a/gcc/config/stormy16/stormy16.c +++ b/gcc/config/stormy16/stormy16.c @@ -2677,6 +2677,9 @@ xstormy16_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xstormy16_preferred_reload_class +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P xstormy16_legitimate_address_p #undef TARGET_MODE_DEPENDENT_ADDRESS_P diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c index 5508ed8a724..d743c63bd59 100644 --- a/gcc/config/tilegx/tilegx.c +++ b/gcc/config/tilegx/tilegx.c @@ -5625,6 +5625,9 @@ tilegx_file_end (void) #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P tilegx_legitimate_constant_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P tilegx_legitimate_address_p diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c index 7237a600333..33e49936536 100644 --- a/gcc/config/tilepro/tilepro.c +++ b/gcc/config/tilepro/tilepro.c @@ -5017,6 +5017,9 @@ tilepro_file_end (void) #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P tilepro_legitimate_constant_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P tilepro_legitimate_address_p diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c index e0e4215e05f..f1716d1a9cd 100644 --- a/gcc/config/v850/v850.c +++ b/gcc/config/v850/v850.c @@ -3340,6 +3340,9 @@ v850_gen_movdi (rtx * operands) #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P v850_legitimate_constant_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P v850_legitimate_address_p diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h index c326df92e69..ae5e9ce96e9 100644 --- a/gcc/config/v850/v850.h +++ b/gcc/config/v850/v850.h @@ -505,10 +505,8 @@ enum reg_class { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} \ -/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It - specifies the initial difference between the specified pair of - registers. This macro must be defined if `ELIMINABLE_REGS' is - defined. */ +/* This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ { \ diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c index 804f0c7a2e1..06ab5715ec3 100644 --- a/gcc/config/vax/vax.c +++ b/gcc/config/vax/vax.c @@ -96,6 +96,9 @@ static bool vax_mode_dependent_address_p (const_rtx, addr_space_t); #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE #define TARGET_BUILTIN_SETJMP_FRAME_VALUE vax_builtin_setjmp_frame_value +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P vax_legitimate_address_p #undef TARGET_MODE_DEPENDENT_ADDRESS_P diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h index a381039d008..77d9e7f0729 100644 --- a/gcc/config/vax/vax.h +++ b/gcc/config/vax/vax.h @@ -340,16 +340,6 @@ enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES }; #define EXIT_IGNORE_STACK 1 -/* Store in the variable DEPTH the initial difference between the - frame pointer reg contents and the stack pointer reg contents, - as of the start of the function body. This depends on the layout - of the fixed parts of the stack frame and on how registers are saved. - - On the VAX, FRAME_POINTER_REQUIRED is always 1, so the definition of this - macro doesn't matter. But it must be defined. */ - -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0; - /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 15 diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c index 360a6740c78..af58f99aef1 100644 --- a/gcc/config/visium/visium.c +++ b/gcc/config/visium/visium.c @@ -264,6 +264,9 @@ static unsigned int visium_reorg (void); #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P visium_legitimate_constant_p +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P visium_legitimate_address_p diff --git a/gcc/config/visium/visium.h b/gcc/config/visium/visium.h index 0f195c07c66..f7e3da4c069 100644 --- a/gcc/config/visium/visium.h +++ b/gcc/config/visium/visium.h @@ -963,10 +963,8 @@ enum reg_class /* `INITIAL_ELIMINATION_OFFSET (FROM-REG, TO-REG, OFFSET-VAR)' - This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It - specifies the initial difference between the specified pair of - registers. This macro must be defined if `ELIMINABLE_REGS' is - defined. */ + This macro returns the initial difference between the specified pair + of registers. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ (OFFSET = visium_initial_elimination_offset (FROM, TO)) diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c index 917ea94840f..07c9e8f1fb2 100644 --- a/gcc/config/xtensa/xtensa.c +++ b/gcc/config/xtensa/xtensa.c @@ -264,6 +264,9 @@ static void xtensa_conditional_register_usage (void); #undef TARGET_CANNOT_FORCE_CONST_MEM #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem +#undef TARGET_LRA_P +#define TARGET_LRA_P hook_bool_void_false + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p |