aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
diff options
context:
space:
mode:
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/alpha/alpha.c6
-rw-r--r--gcc/config/bfin/bfin.c5
-rw-r--r--gcc/config/darwin.c2
-rw-r--r--gcc/config/frv/frv.c9
-rw-r--r--gcc/config/i386/i386.c21
-rw-r--r--gcc/config/ia64/ia64.c7
-rw-r--r--gcc/config/mips/mips.c6
-rw-r--r--gcc/config/pa/pa.c11
-rw-r--r--gcc/config/picochip/picochip-protos.h4
-rw-r--r--gcc/config/picochip/picochip.c22
-rw-r--r--gcc/config/rs6000/rs6000.c21
-rw-r--r--gcc/config/s390/s390.c6
-rw-r--r--gcc/config/sh/sh-protos.h6
-rw-r--r--gcc/config/sh/sh.c10
-rw-r--r--gcc/config/xtensa/xtensa-protos.h6
-rw-r--r--gcc/config/xtensa/xtensa.c6
16 files changed, 82 insertions, 66 deletions
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index b6a83cba916..a67097a3c2c 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -1569,10 +1569,12 @@ alpha_preferred_reload_class(rtx x, enum reg_class rclass)
RCLASS requires an extra scratch or immediate register. Return the class
needed for the immediate register. */
-static enum reg_class
-alpha_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+alpha_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
+ enum reg_class rclass = (enum reg_class) rclass_i;
+
/* Loading and storing HImode or QImode values to and from memory
usually requires a scratch register. */
if (!TARGET_BWX && (mode == QImode || mode == HImode || mode == CQImode))
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index c187bf3bbc7..1232ecc7378 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -2458,8 +2458,8 @@ bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
RCLASS requires an extra scratch register. Return the class needed for the
scratch register. */
-static enum reg_class
-bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+bfin_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
/* If we have HImode or QImode, we can only use DREGS as secondary registers;
@@ -2467,6 +2467,7 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS;
enum reg_class x_class = NO_REGS;
enum rtx_code code = GET_CODE (x);
+ enum reg_class rclass = (enum reg_class) rclass_i;
if (code == SUBREG)
x = SUBREG_REG (x), code = GET_CODE (x);
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 1adff12ea73..5801e431dfd 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -1864,7 +1864,7 @@ darwin_override_options (void)
/* Disable -freorder-blocks-and-partition for darwin_emit_unwind_label. */
if (flag_reorder_blocks_and_partition
- && (targetm.asm_out.unwind_label == darwin_emit_unwind_label))
+ && (targetm.asm_out.emit_unwind_label == darwin_emit_unwind_label))
{
inform (input_location,
"-freorder-blocks-and-partition does not work with exceptions "
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 057bbdf1452..9454bd25e7b 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -1,5 +1,5 @@
/* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
- 2008, 2009 Free Software Foundation, Inc.
+ 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GCC.
@@ -384,7 +384,7 @@ static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
static void frv_output_dwarf_dtprel (FILE *, int, rtx)
ATTRIBUTE_UNUSED;
-static bool frv_secondary_reload (bool, rtx, enum reg_class,
+static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
secondary_reload_info *);
static bool frv_frame_pointer_required (void);
@@ -6492,12 +6492,13 @@ frv_secondary_reload_class (enum reg_class rclass,
called from init_reg_autoinc() in regclass.c - before the reload optabs
have been initialised. */
-static bool
-frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
+static reg_class_t
+frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
enum machine_mode reload_mode,
secondary_reload_info * sri)
{
enum reg_class rclass = NO_REGS;
+ enum reg_class reload_class = (enum reg_class) reload_class_i;
if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
{
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 8a8b57aee5e..ec2cdd38d83 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -25293,13 +25293,13 @@ ix86_free_from_memory (enum machine_mode mode)
/* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
same. */
-static const enum reg_class *
+static const reg_class_t *
i386_ira_cover_classes (void)
{
- static const enum reg_class sse_fpmath_classes[] = {
+ static const reg_class_t sse_fpmath_classes[] = {
GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
};
- static const enum reg_class no_sse_fpmath_classes[] = {
+ static const reg_class_t no_sse_fpmath_classes[] = {
GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
};
@@ -25409,8 +25409,8 @@ ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
return regclass;
}
-static enum reg_class
-ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
enum machine_mode mode,
secondary_reload_info *sri ATTRIBUTE_UNUSED)
{
@@ -25663,10 +25663,10 @@ inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
}
static int
-ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
+ix86_memory_move_cost (enum machine_mode mode, reg_class_t regclass,
bool in)
{
- return inline_memory_move_cost (mode, regclass, in ? 1 : 0);
+ return inline_memory_move_cost (mode, (enum reg_class) regclass, in ? 1 : 0);
}
@@ -25678,9 +25678,12 @@ ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
general registers. */
static int
-ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
- enum reg_class class2)
+ix86_register_move_cost (enum machine_mode mode, reg_class_t class1_i,
+ reg_class_t class2_i)
{
+ enum reg_class class1 = (enum reg_class) class1_i;
+ enum reg_class class2 = (enum reg_class) class2_i;
+
/* In case we require secondary memory, compute cost of the store followed
by load. In order to avoid bad register allocation choices, we need
for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 511ca155ab1..0b6df619244 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -5207,8 +5207,11 @@ ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
one in class TO, using MODE. */
static int
-ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
- enum reg_class to)
+ia64_register_move_cost (enum machine_mode mode, enum reg_class from_i,
+ enum reg_class to_i)
+{
+ enum reg_class from = (enum reg_class) from_i;
+ enum reg_class to = (enum reg_class) to_i;
{
/* ADDL_REGS is the same as GR_REGS for movement purposes. */
if (to == ADDL_REGS)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 29f0f0b74f3..ccdfbbc3fd1 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -10929,14 +10929,14 @@ mips_register_move_cost (enum machine_mode mode,
/* Implement TARGET_IRA_COVER_CLASSES. */
-static const enum reg_class *
+static const reg_class_t *
mips_ira_cover_classes (void)
{
- static const enum reg_class acc_classes[] = {
+ static const reg_class_t acc_classes[] = {
GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};
- static const enum reg_class no_acc_classes[] = {
+ static const reg_class_t no_acc_classes[] = {
GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 5f42a1ac622..2640f05e1bc 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -155,9 +155,9 @@ static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
static struct machine_function * pa_init_machine_status (void);
-static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- secondary_reload_info *);
+static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ secondary_reload_info *);
static void pa_extra_live_on_entry (bitmap);
static enum machine_mode pa_promote_function_mode (const_tree,
enum machine_mode, int *,
@@ -5688,11 +5688,12 @@ output_arg_descriptor (rtx call_insn)
fputc ('\n', asm_out_file);
}
-static enum reg_class
-pa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
int is_symbolic, regno;
+ enum reg_class rclass = (enum reg_class) rclass_i;
/* Handle the easy stuff first. */
if (rclass == R1_REGS)
diff --git a/gcc/config/picochip/picochip-protos.h b/gcc/config/picochip/picochip-protos.h
index 875bb1d2a31..4a80bd16d5d 100644
--- a/gcc/config/picochip/picochip-protos.h
+++ b/gcc/config/picochip/picochip-protos.h
@@ -73,9 +73,9 @@ extern int picochip_symbol_offset (rtx operand);
extern int picochip_get_function_arg_boundary (enum machine_mode mode);
-extern enum reg_class picochip_secondary_reload(bool in_p,
+extern reg_class_t picochip_secondary_reload(bool in_p,
rtx x,
- enum reg_class cla,
+ reg_class_t cla,
enum machine_mode mode,
secondary_reload_info *sri);
diff --git a/gcc/config/picochip/picochip.c b/gcc/config/picochip/picochip.c
index 499c55d9677..2e8dbb92355 100644
--- a/gcc/config/picochip/picochip.c
+++ b/gcc/config/picochip/picochip.c
@@ -1,5 +1,5 @@
/* Subroutines used for code generation on picoChip processors.
- Copyright (C) 2001,2008, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by picoChip Designs Ltd. (http://www.picochip.com)
Maintained by Daniel Towner (daniel.towner@picochip.com) and
Hariharan Sandanagobalane (hariharan@picochip.com)
@@ -103,12 +103,12 @@ int picochip_legitimize_reload_address (rtx *x, enum machine_mode mode,
rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
bool outgoing ATTRIBUTE_UNUSED);
-enum reg_class
+reg_class_t
picochip_secondary_reload (bool in_p,
- rtx x ATTRIBUTE_UNUSED,
- enum reg_class cla ATTRIBUTE_UNUSED,
- enum machine_mode mode,
- secondary_reload_info *sri);
+ rtx x ATTRIBUTE_UNUSED,
+ reg_class_t cla ATTRIBUTE_UNUSED,
+ enum machine_mode mode,
+ secondary_reload_info *sri);
void
picochip_asm_named_section (const char *name,
unsigned int flags ATTRIBUTE_UNUSED,
@@ -4363,12 +4363,12 @@ picochip_get_high_const (rtx value)
choice of two registers to choose from, so that we a guaranteed to
get at least one register which is different to the output
register. This trick is taken from the alpha implementation. */
-enum reg_class
+reg_class_t
picochip_secondary_reload (bool in_p,
- rtx x ATTRIBUTE_UNUSED,
- enum reg_class cla ATTRIBUTE_UNUSED,
- enum machine_mode mode,
- secondary_reload_info *sri)
+ rtx x ATTRIBUTE_UNUSED,
+ reg_class_t cla ATTRIBUTE_UNUSED,
+ enum machine_mode mode,
+ secondary_reload_info *sri)
{
if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
{
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6222bab60f4..36187c95cd5 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1240,11 +1240,11 @@ bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
enum reg_class)
= rs6000_cannot_change_mode_class;
-static enum reg_class rs6000_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- struct secondary_reload_info *);
+static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ struct secondary_reload_info *);
-static const enum reg_class *rs6000_ira_cover_classes (void);
+static const reg_class_t *rs6000_ira_cover_classes (void);
const int INSN_NOT_AVAILABLE = -1;
static enum machine_mode rs6000_eh_return_filter_mode (void);
@@ -13728,14 +13728,15 @@ rs6000_reload_register_type (enum reg_class rclass)
For VSX and Altivec, we may need a register to convert sp+offset into
reg+sp. */
-static enum reg_class
+static reg_class_t
rs6000_secondary_reload (bool in_p,
rtx x,
- enum reg_class rclass,
+ reg_class_t rclass_i,
enum machine_mode mode,
secondary_reload_info *sri)
{
- enum reg_class ret = ALL_REGS;
+ enum reg_class rclass = (enum reg_class) rclass_i;
+ reg_class_t ret = ALL_REGS;
enum insn_code icode;
bool default_p = false;
@@ -14127,11 +14128,11 @@ rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
account for the Altivec and Floating registers being subsets of the VSX
register set under VSX, but distinct register sets on pre-VSX machines. */
-static const enum reg_class *
+static const reg_class_t *
rs6000_ira_cover_classes (void)
{
- static const enum reg_class cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX;
- static const enum reg_class cover_vsx[] = IRA_COVER_CLASSES_VSX;
+ static const reg_class_t cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX;
+ static const reg_class_t cover_vsx[] = IRA_COVER_CLASSES_VSX;
return (TARGET_VSX) ? cover_vsx : cover_pre_vsx;
}
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 1b742357f26..7ff8cb870cd 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2957,10 +2957,12 @@ s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
RCLASS requires an extra scratch or immediate register. Return the class
needed for the immediate register. */
-static enum reg_class
-s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
+ enum reg_class rclass = (enum reg_class) rclass_i;
+
/* Intermediate register needed. */
if (reg_classes_intersect_p (CC_REGS, rclass))
return GENERAL_REGS;
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index 782a88ea551..dc68af1332b 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -173,9 +173,9 @@ extern int sh_contains_memref_p (rtx);
extern int sh_loads_bankedreg_p (rtx);
extern rtx shmedia_prepare_call_address (rtx fnaddr, int is_sibcall);
struct secondary_reload_info;
-extern enum reg_class sh_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- struct secondary_reload_info *);
+extern reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ struct secondary_reload_info *);
extern int sh2a_get_function_vector_number (rtx);
extern int sh2a_is_function_vector_call (rtx);
extern void sh_fix_range (const char *);
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index d8d3985f0b7..b8d2be17c36 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -225,7 +225,7 @@ static int sh_variable_issue (FILE *, int, rtx, int);
static bool sh_function_ok_for_sibcall (tree, tree);
static bool sh_cannot_modify_jumps_p (void);
-static enum reg_class sh_target_reg_class (void);
+static reg_class_t sh_target_reg_class (void);
static bool sh_optimize_target_register_callee_saved (bool);
static bool sh_ms_bitfield_layout_p (const_tree);
@@ -10519,7 +10519,7 @@ sh_cannot_modify_jumps_p (void)
return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
}
-static enum reg_class
+static reg_class_t
sh_target_reg_class (void)
{
return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
@@ -12158,10 +12158,12 @@ shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
return fnaddr;
}
-enum reg_class
-sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+reg_class_t
+sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
+ enum reg_class rclass = (enum reg_class) rclass_i;
+
if (in_p)
{
if (REGCLASS_HAS_FP_REG (rclass)
diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h
index 6bd1e565fe7..729bc84bbbc 100644
--- a/gcc/config/xtensa/xtensa-protos.h
+++ b/gcc/config/xtensa/xtensa-protos.h
@@ -67,9 +67,9 @@ extern void xtensa_output_literal (FILE *, rtx, enum machine_mode, int);
extern rtx xtensa_return_addr (int, rtx);
extern enum reg_class xtensa_preferred_reload_class (rtx, enum reg_class, int);
struct secondary_reload_info;
-extern enum reg_class xtensa_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- struct secondary_reload_info *);
+extern reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ struct secondary_reload_info *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index fe66711af39..5d891cde044 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -1,5 +1,5 @@
/* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
- Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
@@ -3089,8 +3089,8 @@ xtensa_preferred_reload_class (rtx x, enum reg_class rclass, int isoutput)
}
-enum reg_class
-xtensa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+reg_class_t
+xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
enum machine_mode mode, secondary_reload_info *sri)
{
int regno;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-04 15:52:47 +0000