diff options
Diffstat (limited to 'gcc/config')
34 files changed, 1641 insertions, 1178 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index fb4e59fff47..93c35901116 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -133,7 +133,7 @@ static enum machine_mode arm_promote_function_mode (const_tree, const_tree, int); static bool arm_return_in_memory (const_tree, const_tree); static rtx arm_function_value (const_tree, const_tree, bool); -static rtx arm_libcall_value (enum machine_mode, rtx); +static rtx arm_libcall_value (enum machine_mode, const_rtx); static void arm_internal_label (FILE *, const char *, unsigned long); static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, @@ -1864,6 +1864,16 @@ arm_override_options (void) max_insns_skipped = 3; } + /* Hot/Cold partitioning is not currently supported, since we can't + handle literal pool placement in that case. */ + if (flag_reorder_blocks_and_partition) + { + inform (input_location, + "-freorder-blocks-and-partition not supported on this architecture"); + flag_reorder_blocks_and_partition = 0; + flag_reorder_blocks = 1; + } + /* Ideally we would want to use CFI directives to generate debug info. However this also creates the .eh_frame section, so disable them until GAS can handle @@ -3264,7 +3274,7 @@ add_libcall (htab_t htab, rtx libcall) } static bool -arm_libcall_uses_aapcs_base (rtx libcall) +arm_libcall_uses_aapcs_base (const_rtx libcall) { static bool init_done = false; static htab_t libcall_htab; @@ -3311,7 +3321,7 @@ arm_libcall_uses_aapcs_base (rtx libcall) } rtx -arm_libcall_value (enum machine_mode mode, rtx libcall) +arm_libcall_value (enum machine_mode mode, const_rtx libcall) { if (TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS && GET_MODE_CLASS (mode) == MODE_FLOAT) @@ -12269,7 +12279,7 @@ output_move_neon (rtx *operands) { /* We're only using DImode here because it's a convenient size. */ ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); - ops[1] = adjust_address (mem, SImode, 8 * i); + ops[1] = adjust_address (mem, DImode, 8 * i); if (reg_overlap_mentioned_p (ops[0], mem)) { gcc_assert (overlap == -1); diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 85bc3eed100..7d1ef111339 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -3655,7 +3655,8 @@ UNSPEC_VSHLL_N))] "TARGET_NEON" { - neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode)); + /* The boundaries are: 0 < imm <= size. */ + neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode) + 1); return "vshll.%T3%#<V_sz_elem>\t%q0, %P1, %2"; } [(set_attr "neon_type" "neon_shift_1")] diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 5a15200ffe3..b2d6b44a57d 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -235,7 +235,7 @@ (define_insn "*movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r") - (match_operand:QI 1 "general_operand" "r,i,rL,Qm,r,q,i"))] + (match_operand:QI 1 "general_operand" "rL,i,rL,Qm,r,q,i"))] "(register_operand (operands[0],QImode) || register_operand (operands[1], QImode) || const0_rtx == operands[1])" "* return output_movqi (insn, operands, NULL);" @@ -336,7 +336,7 @@ (define_insn "*movhi" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r") - (match_operand:HI 1 "general_operand" "r,m,rL,i,i,r,q"))] + (match_operand:HI 1 "general_operand" "rL,m,rL,i,i,r,q"))] "(register_operand (operands[0],HImode) || register_operand (operands[1],HImode) || const0_rtx == operands[1])" "* return output_movhi (insn, operands, NULL);" diff --git a/gcc/config/cris/cris-protos.h b/gcc/config/cris/cris-protos.h index db6aa9fe9ce..721c90ff887 100644 --- a/gcc/config/cris/cris-protos.h +++ b/gcc/config/cris/cris-protos.h @@ -71,3 +71,5 @@ extern void cris_override_options (void); extern int cris_initial_elimination_offset (int, int); extern void cris_init_expanders (void); + +extern bool cris_function_value_regno_p (const unsigned int); diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index bf00a57a3b6..225ad403dda 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -130,6 +130,9 @@ static bool cris_frame_pointer_required (void); static void cris_asm_trampoline_template (FILE *); static void cris_trampoline_init (rtx, tree, rtx); +static rtx cris_function_value(const_tree, const_tree, bool); +static rtx cris_libcall_value (enum machine_mode, const_rtx); + /* This is the parsed result of the "-max-stack-stackframe=" option. If it (still) is zero, then there was no such option given. */ int cris_max_stackframe = 0; @@ -197,6 +200,11 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; #undef TARGET_TRAMPOLINE_INIT #define TARGET_TRAMPOLINE_INIT cris_trampoline_init +#undef TARGET_FUNCTION_VALUE +#define TARGET_FUNCTION_VALUE cris_function_value +#undef TARGET_LIBCALL_VALUE +#define TARGET_LIBCALL_VALUE cris_libcall_value + struct gcc_target targetm = TARGET_INITIALIZER; /* Helper for cris_load_multiple_op and cris_ret_movem_op. */ @@ -3777,13 +3785,42 @@ cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, int for_return) { /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even - when modifying FUNCTION_VALUE to return the promoted mode). Maybe - pointless as of now, but let's keep the old behavior. */ + when modifying TARGET_FUNCTION_VALUE to return the promoted mode). + Maybe pointless as of now, but let's keep the old behavior. */ if (for_return == 1) return mode; return CRIS_PROMOTED_MODE (mode, *punsignedp, type); } +/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the + time being. */ + +static rtx +cris_function_value(const_tree type, + const_tree func ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) +{ + return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG); +} + +/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the + time being. */ + +static rtx +cris_libcall_value (enum machine_mode mode, + const_rtx fun ATTRIBUTE_UNUSED) +{ + return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG); +} + +/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the + time being. */ + +bool +cris_function_value_regno_p (const unsigned int regno) +{ + return (regno == CRIS_FIRST_ARG_REG); +} static int cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode, diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 586f7ff2077..0fea7d77b39 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -630,12 +630,17 @@ enum reg_class ? GENERAL_REGS : (CLASS)) /* We can't move special registers to and from memory in smaller than - word_mode. */ -#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ - (((CLASS) != SPECIAL_REGS && (CLASS) != MOF_REGS) \ - || GET_MODE_SIZE (MODE) == 4 \ - || !MEM_P (X) \ - ? NO_REGS : GENERAL_REGS) + word_mode. We also can't move between special registers. Luckily, + -1, as returned by true_regnum for non-sub/registers, is valid as a + parameter to our REGNO_REG_CLASS, returning GENERAL_REGS, so we get + the effect that any X that isn't a special-register is treated as + a non-empty intersection with GENERAL_REGS. */ +#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ + ((((CLASS) == SPECIAL_REGS || (CLASS) == MOF_REGS) \ + && ((GET_MODE_SIZE (MODE) < 4 && MEM_P (X)) \ + || !reg_classes_intersect_p (REGNO_REG_CLASS (true_regnum (X)), \ + GENERAL_REGS))) \ + ? GENERAL_REGS : NO_REGS) /* FIXME: Fix regrename.c; it should check validity of replacements, not just with a silly pass-specific macro. We may miss some @@ -901,14 +906,8 @@ struct cum_args {int regs;}; /* Node: Scalar Return */ -/* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the - time being. */ -#define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx_REG (TYPE_MODE (VALTYPE), CRIS_FIRST_ARG_REG) +#define FUNCTION_VALUE_REGNO_P(N) cris_function_value_regno_p (N) -#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, CRIS_FIRST_ARG_REG) - -#define FUNCTION_VALUE_REGNO_P(N) ((N) == CRIS_FIRST_ARG_REG) /* Node: Aggregate Return */ diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 79eb8da3b0d..bd14a16337e 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -4936,7 +4936,7 @@ ;; It should be: ;; movu.b some_byte,reg_32 ;; and.b const,reg_32 -;; but is turns into: +;; but it turns into: ;; move.b some_byte,reg_32 ;; and.d const,reg_32 ;; Fix it here. @@ -4953,7 +4953,9 @@ "REGNO (operands[2]) == REGNO (operands[0]) && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I') - && !side_effects_p (operands[1])" + && !side_effects_p (operands[1]) + && (!REG_P (operands[1]) + || REGNO (operands[1]) <= CRIS_LAST_GENERAL_REGISTER)" ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE). [(set (match_dup 0) (match_dup 4)) (set (match_dup 5) (match_dup 6))] diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index a8933e66348..b5c4fb8e0d9 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -1697,6 +1697,17 @@ darwin_override_options (void) if (dwarf_strict < 0) dwarf_strict = 1; + /* Disable -freorder-blocks-and-partition for darwin_emit_unwind_label. */ + if (flag_reorder_blocks_and_partition + && (targetm.asm_out.unwind_label == darwin_emit_unwind_label)) + { + inform (input_location, + "-freorder-blocks-and-partition does not work with exceptions " + "on this architecture"); + flag_reorder_blocks_and_partition = 0; + flag_reorder_blocks = 1; + } + if (flag_mkernel || flag_apple_kext) { /* -mkernel implies -fapple-kext for C++ */ diff --git a/gcc/config/darwin10.h b/gcc/config/darwin10.h index 65ba2632a8f..b1edf36ce3d 100644 --- a/gcc/config/darwin10.h +++ b/gcc/config/darwin10.h @@ -23,3 +23,8 @@ unwinder in libSystem is fixed to digest new epilog unwinding notes. */ #undef LIB_SPEC #define LIB_SPEC "%{!static:-no_compact_unwind -lSystem}" + +/* Unwind labels are no longer required in darwin10. */ + +#undef TARGET_ASM_EMIT_UNWIND_LABEL +#define TARGET_ASM_EMIT_UNWIND_LABEL default_emit_unwind_label diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 404595405f3..7bb1e7a6c5c 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -507,6 +507,32 @@ byte_reg (rtx x, int b) && call_used_regs[regno] \ && !current_function_is_leaf))) +/* We use this to wrap all emitted insns in the prologue. */ +static rtx +F (rtx x) +{ + RTX_FRAME_RELATED_P (x) = 1; + return x; +} + +/* Mark all the subexpressions of the PARALLEL rtx PAR as + frame-related. Return PAR. + + dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a + PARALLEL rtx other than the first if they do not have the + FRAME_RELATED flag set on them. */ +static rtx +Fpa (rtx par) +{ + int len = XVECLEN (par, 0); + int i; + + for (i = 0; i < len; i++) + F (XVECEXP (par, 0, i)); + + return par; +} + /* Output assembly language to FILE for the operation OP with operand size SIZE to adjust the stack pointer. */ @@ -526,22 +552,27 @@ h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size) && !(cfun->static_chain_decl != NULL && sign < 0)) { rtx r3 = gen_rtx_REG (Pmode, 3); - emit_insn (gen_movhi (r3, GEN_INT (sign * size))); - emit_insn (gen_addhi3 (stack_pointer_rtx, - stack_pointer_rtx, r3)); + F (emit_insn (gen_movhi (r3, GEN_INT (sign * size)))); + F (emit_insn (gen_addhi3 (stack_pointer_rtx, + stack_pointer_rtx, r3))); } else { /* The stack adjustment made here is further optimized by the splitter. In case of H8/300, the splitter always splits the - addition emitted here to make the adjustment - interrupt-safe. */ + addition emitted here to make the adjustment interrupt-safe. + FIXME: We don't always tag those, because we don't know what + the splitter will do. */ if (Pmode == HImode) - emit_insn (gen_addhi3 (stack_pointer_rtx, - stack_pointer_rtx, GEN_INT (sign * size))); + { + rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx, + stack_pointer_rtx, GEN_INT (sign * size))); + if (size < 4) + F (x); + } else - emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, GEN_INT (sign * size))); + F (emit_insn (gen_addsi3 (stack_pointer_rtx, + stack_pointer_rtx, GEN_INT (sign * size)))); } } @@ -591,7 +622,7 @@ push (int rn) x = gen_push_h8300hs_advanced (reg); else x = gen_push_h8300hs_normal (reg); - x = emit_insn (x); + x = F (emit_insn (x)); REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0); } @@ -634,7 +665,7 @@ h8300_push_pop (int regno, int nregs, int pop_p, int return_p) { int i, j; rtvec vec; - rtx sp, offset; + rtx sp, offset, x; /* See whether we can use a simple push or pop. */ if (!return_p && nregs == 1) @@ -685,7 +716,10 @@ h8300_push_pop (int regno, int nregs, int pop_p, int return_p) RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp, gen_rtx_PLUS (Pmode, sp, offset)); - emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); + x = gen_rtx_PARALLEL (VOIDmode, vec); + if (!pop_p) + x = Fpa (x); + emit_insn (x); } /* Return true if X has the value sp + OFFSET. */ @@ -820,7 +854,7 @@ h8300_expand_prologue (void) { /* Push fp. */ push (HARD_FRAME_POINTER_REGNUM); - emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); + F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx)); } /* Push the rest of the registers in ascending order. */ diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h index e0f0ea62f4e..9757afc2de3 100644 --- a/gcc/config/h8300/h8300.h +++ b/gcc/config/h8300/h8300.h @@ -147,6 +147,17 @@ extern const char * const *h8_reg_names; /* Show we can debug even without a frame pointer. */ /* #define CAN_DEBUG_WITHOUT_FP */ +/* We want dwarf2 info available to gdb... */ +#define DWARF2_DEBUGGING_INFO 1 +/* ... but we don't actually support full dwarf2 EH. */ +#define MUST_USE_SJLJ_EXCEPTIONS 1 + +/* The return address is pushed on the stack. */ +#define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)) +#define INCOMING_FRAME_SP_OFFSET (POINTER_SIZE / 8) + +#define DWARF_CIE_DATA_ALIGNMENT 2 + /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on machines where ordinary constants are expensive diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index 43003cc5cad..cdab21c91a2 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -49,8 +49,9 @@ along with GCC; see the file COPYING3. If not see target, always use the svr4_dbx_register_map for DWARF .eh_frame even if we don't use DWARF .debug_frame. */ #undef DWARF_FRAME_REGNUM -#define DWARF_FRAME_REGNUM(n) TARGET_64BIT \ - ? dbx64_register_map[(n)] : svr4_dbx_register_map[(n)] +#define DWARF_FRAME_REGNUM(n) \ + (TARGET_64BIT ? dbx64_register_map[(n)] \ + : svr4_dbx_register_map[(n)]) #ifdef HAVE_GAS_PE_SECREL32_RELOC /* Use section relative relocations for debugging offsets. Unlike diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index b5bb6a0352f..6065f49a042 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -4774,6 +4774,25 @@ ix86_function_type_abi (const_tree fntype) return ix86_abi; } +static bool +ix86_function_ms_hook_prologue (const_tree fntype) +{ + if (!TARGET_64BIT) + { + if (lookup_attribute ("ms_hook_prologue", DECL_ATTRIBUTES (fntype))) + { + if (decl_function_context (fntype) != NULL_TREE) + { + error_at (DECL_SOURCE_LOCATION (fntype), + "ms_hook_prologue is not compatible with nested function"); + } + + return true; + } + } + return false; +} + static enum calling_abi ix86_function_abi (const_tree fndecl) { @@ -8295,6 +8314,7 @@ ix86_expand_prologue (void) bool pic_reg_used; struct ix86_frame frame; HOST_WIDE_INT allocate; + int gen_frame_pointer = frame_pointer_needed; ix86_finalize_stack_realign_flags (); @@ -8307,6 +8327,46 @@ ix86_expand_prologue (void) ix86_compute_frame_layout (&frame); + if (ix86_function_ms_hook_prologue (current_function_decl)) + { + rtx push, mov; + + /* Make sure the function starts with + 8b ff movl.s %edi,%edi + 55 push %ebp + 8b ec movl.s %esp,%ebp + + This matches the hookable function prologue in Win32 API + functions in Microsoft Windows XP Service Pack 2 and newer. + Wine uses this to enable Windows apps to hook the Win32 API + functions provided by Wine. */ + insn = emit_insn (gen_vswapmov (gen_rtx_REG (SImode, DI_REG), + gen_rtx_REG (SImode, DI_REG))); + push = emit_insn (gen_push (hard_frame_pointer_rtx)); + mov = emit_insn (gen_vswapmov (hard_frame_pointer_rtx, + stack_pointer_rtx)); + + if (frame_pointer_needed && !(crtl->drap_reg + && crtl->stack_realign_needed)) + { + /* The push %ebp and movl.s %esp, %ebp already set up + the frame pointer. No need to do this again. */ + gen_frame_pointer = 0; + RTX_FRAME_RELATED_P (push) = 1; + RTX_FRAME_RELATED_P (mov) = 1; + if (ix86_cfa_state->reg == stack_pointer_rtx) + ix86_cfa_state->reg = hard_frame_pointer_rtx; + } + else + /* If the frame pointer is not needed, pop %ebp again. This + could be optimized for cases where ebp needs to be backed up + for some other reason. If stack realignment is needed, pop + the base pointer again, align the stack, and later regenerate + the frame pointer setup. The frame pointer generated by the + hook prologue is not aligned, so it can't be used. */ + insn = emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx)); + } + /* The first insn of a function that accepts its static chain on the stack is to push the register that would be filled in by a direct call. This insn will be skipped by the trampoline. */ @@ -8378,7 +8438,7 @@ ix86_expand_prologue (void) /* Note: AT&T enter does NOT have reversed args. Enter is probably slower on all targets. Also sdb doesn't like it. */ - if (frame_pointer_needed) + if (gen_frame_pointer) { insn = emit_insn (gen_push (hard_frame_pointer_rtx)); RTX_FRAME_RELATED_P (insn) = 1; @@ -8962,7 +9022,8 @@ ix86_expand_epilogue (int style) 0, red_offset, style == 2); pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (frame.nsseregs * 16 + frame.padding0), + GEN_INT (frame.nsseregs * 16 + + frame.padding0), style, false); } else if (frame.to_allocate || frame.padding0 || frame.nsseregs) @@ -26470,6 +26531,33 @@ ix86_handle_struct_attribute (tree *node, tree name, return NULL_TREE; } +static tree +ix86_handle_fndecl_attribute (tree *node, tree name, + tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) +{ + if (TREE_CODE (*node) != FUNCTION_DECL) + { + warning (OPT_Wattributes, "%qE attribute only applies to functions", + name); + *no_add_attrs = true; + return NULL_TREE; + } + + if (TARGET_64BIT) + { + warning (OPT_Wattributes, "%qE attribute only available for 32-bit", + name); + return NULL_TREE; + } + +#ifndef HAVE_AS_IX86_SWAP + sorry ("ms_hook_prologue attribute needs assembler swap suffix support"); +#endif + + return NULL_TREE; +} + static bool ix86_ms_bitfield_layout_p (const_tree record_type) { @@ -29512,6 +29600,7 @@ static const struct attribute_spec ix86_attribute_table[] = /* ms_abi and sysv_abi calling convention function attributes. */ { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute }, { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute }, + { "ms_hook_prologue", 0, 0, true, false, false, ix86_handle_fndecl_attribute }, /* End element. */ { NULL, 0, 0, false, false, false, NULL } }; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 8d525727eec..33a50771471 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -873,6 +873,9 @@ enum target_cpu_default || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ || (MODE) == XFmode) +/* Cover class containing the stack registers. */ +#define STACK_REG_COVER_CLASS FLOAT_REGS + /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 22ea39cf79b..408787b8ab4 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -241,6 +241,7 @@ (UNSPECV_RDTSC 18) (UNSPECV_RDTSCP 19) (UNSPECV_RDPMC 20) + (UNSPECV_VSWAPMOV 21) ]) ;; Constants to represent pcomtrue/pcomfalse variants @@ -13822,20 +13823,6 @@ operands[2] = gen_lowpart (QImode, operands[0]); }) -(define_insn_and_split "*setcc_<mode>_2" - [(set (match_operand:SWI48 0 "register_operand" "=q") - (match_operator:SWI48 1 "ix86_comparison_operator" - [(reg FLAGS_REG) (const_int 0)]))] - "TARGET_PARTIAL_REG_STALL" - "#" - "&& reload_completed" - [(set (match_dup 0) (const_int 0)) - (set (strict_low_part (match_dup 2)) (match_dup 1))] -{ - PUT_MODE (operands[1], QImode); - operands[2] = gen_lowpart (QImode, operands[0]); -}) - (define_insn "*setcc_qi" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") (match_operator:QI 1 "ix86_comparison_operator" @@ -14893,6 +14880,16 @@ (set_attr "length_immediate" "0") (set_attr "modrm" "0")]) +(define_insn "vswapmov" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r")) + (unspec_volatile [(const_int 0)] UNSPECV_VSWAPMOV)] + "" + "movl.s\t{%1, %0|%0, %1}" + [(set_attr "length" "2") + (set_attr "length_immediate" "0") + (set_attr "modrm" "0")]) + ;; Pad to 16-byte boundary, max skip in op0. Used to avoid ;; branch prediction penalty for the third jump in a 16-byte ;; block on K8. diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h index 9b51496a864..5e2e0136fcb 100644 --- a/gcc/config/i386/linux.h +++ b/gcc/config/i386/linux.h @@ -104,7 +104,7 @@ along with GCC; see the file COPYING3. If not see #undef ASM_SPEC #define ASM_SPEC \ - "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \ + "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} --32 \ %{!mno-sse2avx:%{mavx:-msse2avx}} %{msse2avx:%{!mavx:-msse2avx}}" #undef SUBTARGET_EXTRA_SPECS diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 75c8f0ee6c4..23fc7540ec0 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -5496,6 +5496,14 @@ ia64_override_options (void) if (TARGET_AUTO_PIC) target_flags |= MASK_CONST_GP; + /* Numerous experiment shows that IRA based loop pressure + calculation works better for RTL loop invariant motion on targets + with enough (>= 32) registers. It is an expensive optimization. + So it is on only for peak performance. */ + if (optimize >= 3) + flag_ira_loop_pressure = 1; + + ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload; flag_schedule_insns_after_reload = 0; diff --git a/gcc/config/m32c/m32c-protos.h b/gcc/config/m32c/m32c-protos.h index e571fe9d25e..42b92feb506 100644 --- a/gcc/config/m32c/m32c-protos.h +++ b/gcc/config/m32c/m32c-protos.h @@ -49,7 +49,6 @@ int m32c_trampoline_size (void); #if defined(RTX_CODE) && defined(TREE_CODE) rtx m32c_function_arg (CUMULATIVE_ARGS *, MM, tree, int); -rtx m32c_function_value (const_tree, const_tree); #endif @@ -75,7 +74,7 @@ bool m32c_immd_dbl_mov (rtx *, MM); rtx m32c_incoming_return_addr_rtx (void); int m32c_legitimate_constant_p (rtx); int m32c_legitimize_reload_address (rtx *, MM, int, int, int); -rtx m32c_libcall_value (MM); +bool m32c_function_value_regno_p (const unsigned int); int m32c_limit_reload_class (MM, int); int m32c_memory_move_cost (MM, int, int); int m32c_modes_tieable_p (MM, MM); diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 4eeedb183e7..1085aa7c25a 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -81,6 +81,9 @@ static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *); static rtx m32c_struct_value_rtx (tree, int); static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int); static int need_to_save (int); +static rtx m32c_function_value (const_tree, const_tree, bool); +static rtx m32c_libcall_value (enum machine_mode, const_rtx); + int current_function_special_page_vector (rtx); #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0) @@ -1591,15 +1594,19 @@ m32c_valid_pointer_mode (enum machine_mode mode) /* How Scalar Function Values Are Returned */ -/* Implements LIBCALL_VALUE. Most values are returned in $r0, or some +/* Implements TARGET_LIBCALL_VALUE. Most values are returned in $r0, or some combination of registers starting there (r2r0 for longs, r3r1r2r0 for long long, r3r2r1r0 for doubles), except that that ABI currently doesn't work because it ends up using all available general registers and gcc often can't compile it. So, instead, we return anything bigger than 16 bits in "mem0" (effectively, a memory location). */ -rtx -m32c_libcall_value (enum machine_mode mode) + +#undef TARGET_LIBCALL_VALUE +#define TARGET_LIBCALL_VALUE m32c_libcall_value + +static rtx +m32c_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) { /* return reg or parallel */ #if 0 @@ -1649,14 +1656,28 @@ m32c_libcall_value (enum machine_mode mode) return gen_rtx_REG (mode, R0_REGNO); } -/* Implements FUNCTION_VALUE. Functions and libcalls have the same +/* Implements TARGET_FUNCTION_VALUE. Functions and libcalls have the same conventions. */ -rtx -m32c_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) + +#undef TARGET_FUNCTION_VALUE +#define TARGET_FUNCTION_VALUE m32c_function_value + +static rtx +m32c_function_value (const_tree valtype, + const_tree fn_decl_or_type ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) { /* return reg or parallel */ const enum machine_mode mode = TYPE_MODE (valtype); - return m32c_libcall_value (mode); + return m32c_libcall_value (mode, NULL_RTX); +} + +/* Implements FUNCTION_VALUE_REGNO_P. */ + +bool +m32c_function_value_regno_p (const unsigned int regno) +{ + return (regno == R0_REGNO || regno == MEM0_REGNO); } /* How Large Values Are Returned */ diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h index 0f12158c0e4..c0914d3be02 100644 --- a/gcc/config/m32c/m32c.h +++ b/gcc/config/m32c/m32c.h @@ -533,10 +533,7 @@ typedef struct m32c_cumulative_args /* How Scalar Function Values Are Returned */ -#define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F) -#define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE) - -#define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO) +#define FUNCTION_VALUE_REGNO_P(r) m32c_function_value_regno_p (r) /* How Large Values Are Returned */ diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e44eb49b943..4b4353c95ac 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -3387,10 +3387,11 @@ mips_immediate_operand_p (int code, HOST_WIDE_INT x) /* Return the cost of binary operation X, given that the instruction sequence for a word-sized or smaller operation has cost SINGLE_COST - and that the sequence of a double-word operation has cost DOUBLE_COST. */ + and that the sequence of a double-word operation has cost DOUBLE_COST. + If SPEED is true, optimize for speed otherwise optimize for size. */ static int -mips_binary_cost (rtx x, int single_cost, int double_cost) +mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed) { int cost; @@ -3399,8 +3400,8 @@ mips_binary_cost (rtx x, int single_cost, int double_cost) else cost = single_cost; return (cost - + rtx_cost (XEXP (x, 0), SET, !optimize_size) - + rtx_cost (XEXP (x, 1), GET_CODE (x), !optimize_size)); + + rtx_cost (XEXP (x, 0), SET, speed) + + rtx_cost (XEXP (x, 1), GET_CODE (x), speed)); } /* Return the cost of floating-point multiplications of mode MODE. */ @@ -3470,8 +3471,7 @@ mips_zero_extend_cost (enum machine_mode mode, rtx op) /* Implement TARGET_RTX_COSTS. */ static bool -mips_rtx_costs (rtx x, int code, int outer_code, int *total, - bool speed) +mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed) { enum machine_mode mode = GET_MODE (x); bool float_mode_p = FLOAT_MODE_P (mode); @@ -3527,8 +3527,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total, operand needs to be forced into a register, we will often be able to hoist the constant load out of the loop, so the load should not contribute to the cost. */ - if (!optimize_size - || mips_immediate_operand_p (outer_code, INTVAL (x))) + if (speed || mips_immediate_operand_p (outer_code, INTVAL (x))) { *total = 0; return true; @@ -3626,7 +3625,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total, case IOR: case XOR: /* Double-word operations use two single-word operations. */ - *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2)); + *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2), + speed); return true; case ASHIFT: @@ -3635,9 +3635,11 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total, case ROTATE: case ROTATERT: if (CONSTANT_P (XEXP (x, 1))) - *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4)); + *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), + speed); else - *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12)); + *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12), + speed); return true; case ABS: @@ -3673,7 +3675,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total, *total = mips_cost->fp_add; return false; } - *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4)); + *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), + speed); return true; case MINUS: @@ -3724,7 +3727,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total, an SLTU. The MIPS16 version then needs to move the result of the SLTU from $24 to a MIPS16 register. */ *total = mips_binary_cost (x, COSTS_N_INSNS (1), - COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4)); + COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4), + speed); return true; case NEG: @@ -3760,10 +3764,10 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total, else if (mode == DImode && !TARGET_64BIT) /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions, where the mulsidi3 always includes an MFHI and an MFLO. */ - *total = (optimize_size - ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9) - : mips_cost->int_mult_si * 3 + 6); - else if (optimize_size) + *total = (speed + ? mips_cost->int_mult_si * 3 + 6 + : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)); + else if (!speed) *total = (ISA_HAS_MUL3 ? 1 : 2); else if (mode == DImode) *total = mips_cost->int_mult_di; @@ -3800,7 +3804,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total, case UDIV: case UMOD: - if (optimize_size) + if (!speed) { /* It is our responsibility to make division by a power of 2 as cheap as 2 register additions if we want the division diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 20f64449097..d10a40d55e1 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -7120,17 +7120,6 @@ operands[0] = index; } - /* In 64bit mode we must make sure to wipe the upper bits of the register - just in case the addition overflowed or we had random bits in the - high part of the register. */ - if (TARGET_64BIT) - { - rtx index = gen_reg_rtx (DImode); - - emit_insn (gen_extendsidi2 (index, operands[0])); - operands[0] = gen_rtx_SUBREG (SImode, index, 4); - } - if (!INT_5_BITS (operands[2])) operands[2] = force_reg (SImode, operands[2]); @@ -7149,6 +7138,17 @@ emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4])); } + /* In 64bit mode we must make sure to wipe the upper bits of the register + just in case the addition overflowed or we had random bits in the + high part of the register. */ + if (TARGET_64BIT) + { + rtx index = gen_reg_rtx (DImode); + + emit_insn (gen_extendsidi2 (index, operands[0])); + operands[0] = index; + } + if (TARGET_BIG_SWITCH) { if (TARGET_64BIT) @@ -7209,8 +7209,7 @@ ;;; 64-bit code, 32-bit relative branch table. (define_insn "casesi64p" [(set (pc) (mem:DI (plus:DI - (mult:DI (sign_extend:DI - (match_operand:SI 0 "register_operand" "r")) + (mult:DI (match_operand:DI 0 "register_operand" "r") (const_int 8)) (label_ref (match_operand 1 "" ""))))) (clobber (match_scratch:DI 2 "=&r")) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 53b1054d200..6fbb7cdcdac 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1,5 +1,5 @@ ;; AltiVec patterns. -;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008 +;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 ;; Free Software Foundation, Inc. ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) diff --git a/gcc/config/rs6000/option-defaults.h b/gcc/config/rs6000/option-defaults.h index 682add7605d..7e117d731da 100644 --- a/gcc/config/rs6000/option-defaults.h +++ b/gcc/config/rs6000/option-defaults.h @@ -50,15 +50,15 @@ /* Support for a compile-time default CPU, et cetera. The rules are: --with-cpu is ignored if -mcpu is specified; likewise --with-cpu-32 and --with-cpu-64. - --with-tune is ignored if -mtune is specified; likewise --with-tune-32 - and --with-tune-64. + --with-tune is ignored if -mtune or -mcpu is specified; likewise + --with-tune-32 and --with-tune-64. --with-float is ignored if -mhard-float or -msoft-float are - specified. */ + specified. */ #define OPTION_DEFAULT_SPECS \ + {"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \ + {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ + {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \ {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ {"cpu_32", "%{" OPT_ARCH32 ":%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ {"cpu_64", "%{" OPT_ARCH64 ":%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ - {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ - {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ - {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index d03cce6f8a2..2d8a2a8d5d1 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for POWER and PowerPC. -;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +;; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def new file mode 100644 index 00000000000..f5ad34882d4 --- /dev/null +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -0,0 +1,990 @@ +/* Builtin functions for rs6000/powerpc. + Copyright (C) 2009 + Free Software Foundation, Inc. + Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +/* Before including this file, two macros must be defined: + RS6000_BUILTIN -- 2 arguments, the enum name, and classification + RS6000_BUILTIN_EQUATE -- 2 arguments, enum name and value */ + +/* AltiVec builtins. */ +RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_4si, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_4si, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_8hi, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_8hi, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_16qi, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_16qi, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_4sf, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_4sf, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUBM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUHM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUWM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDCUW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUBS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDSBS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDSHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUWS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDSWS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VAND, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VANDC, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGUB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGSB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGUH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGSH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGUW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VAVGSW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCFUX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCFSX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCTSXS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCTUXS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPBFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGEFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEXPTEFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VLOGEFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMADDFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXUB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXSB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXUH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXSH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXUW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXSW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMAXFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMHADDSHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMHRADDSHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMLADDUHM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGHB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGHH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGHW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGLB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGLH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMRGLW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMUBM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMMBM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMUHM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMSHM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMUHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMSUMSHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINUB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINSB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINUH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINSH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINUW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINSW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMINFP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUB_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULESB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULEUH_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULESH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUB_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOSB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOUH_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VMULOSH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VNMSUBFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VNOR, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VOR, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_2DI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_4SI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_8HI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSEL_16QI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_2DI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_4SI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_8HI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPERM_16QI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUHUM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUWUM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKPX, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUHSS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSHSS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUWSS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSWSS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUHUS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSHUS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKUWUS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VREFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIM, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIN, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRFIZ, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRLW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VRSQRTEFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSL, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLO, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTISB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTISH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSPLTISW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRAB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRAH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRAW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSR, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSRO, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUBM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUHM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUWM, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBFP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBCUW, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUBS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBSBS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBSHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBUWS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUBSWS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM4UBS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM4SBS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM4SHS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUM2SWS, RS6000_BTC_SAT) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSUMSWS, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VXOR, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VSLDOI_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKHSB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKLSB, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKLPX, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VUPKLSH, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_MTVSCR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_MFVSCR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_DSSALL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_DSS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSL, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSR, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_DSTT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_DSTST, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_DSTSTT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_DST, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEBX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEHX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEWX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVXL, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVLX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVLXL, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRXL, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEBX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEHX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEWX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVXL, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLXL, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRX, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRXL, RS6000_BTC_MEM) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPBFP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQFP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUB_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUH_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUW_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGEFP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTFP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSB_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSH_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTSW_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUB_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUH_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGTUW_P, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSS_V4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSS_V8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSS_V16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_ABS_V16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_MASK_FOR_LOAD, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_MASK_FOR_STORE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INIT_V4SF, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SET_V4SF, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(ALTIVEC_BUILTIN_COPYSIGN_V4SF, RS6000_BTC_CONST) + +/* Altivec overloaded builtins. */ +/* For now, don't set the classification for overloaded functions. + The function should be converted to the type specific instruction + before we get to the point about classifying the builtin type. */ +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQ_P, RS6000_BTC_MISC) +RS6000_BUILTIN_EQUATE(ALTIVEC_BUILTIN_OVERLOADED_FIRST, + ALTIVEC_BUILTIN_VCMPEQ_P) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGT_P, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGE_P, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADD, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADDC, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADDS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_AND, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ANDC, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_AVG, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXTRACT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CEIL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQ, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPEQUW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPGE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPGT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPLE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CMPLT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_COPYSIGN, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CTF, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CTS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_CTU, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DST, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DSTST, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DSTSTT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_DSTT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXPTE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_FLOOR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LD, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LDE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LDL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LOGE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEBX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEHX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEWX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLXL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRXL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MADD, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MADDS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MAX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MERGEH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MERGEL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MIN, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MLADD, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MPERM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRADDS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGHB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGHH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGHW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGLB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGLH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MRGLW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MSUM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MSUMS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MTVSCR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MULE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MULO, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_NEARBYINT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_NMSUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_NOR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_OR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACK, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACKPX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACKS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PACKSU, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PERM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RINT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ROUND, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_RSQRTE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SEL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SLD, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SLL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SLO, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_S16, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_S32, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_S8, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_U16, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_U32, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLAT_U8, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLTB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLTH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLTW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SQRT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SRA, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SRL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SRO, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ST, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEBX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEHX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEWX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLXL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRXL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBC, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUM2S, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUM4S, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUMS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_TRUNC, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_UNPACKH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_UNPACKL, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDFP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDSBS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDSHS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDSWS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUBM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUBS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUHM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUHS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUWM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VADDUWS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGSB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGSH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGSW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VAVGUW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCFSX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCFUX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQFP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPEQUW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTFP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTSB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTSH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTSW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VCMPGTUW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXFP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXSB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXSH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXSW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMAXUW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINFP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINSB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINSH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINSW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMINUW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGHB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGHH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGHW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGLB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGLH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMRGLW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMMBM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMSHM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMSHS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMUBM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMUHM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMSUMUHS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULESB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULESH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULEUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULEUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOSB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOSH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOUB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VMULOUH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSHSS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSHUS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSWSS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKSWUS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUHUM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUHUS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUWUM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VPKUWUS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VRLB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VRLH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VRLW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSLB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSLH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSLW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSPLTB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSPLTH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSPLTW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRAB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRAH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRAW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSRW, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBFP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBSBS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBSHS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBSWS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUBM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUBS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUHM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUHS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUWM, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUBUWS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUM4SBS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUM4SHS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VSUM4UBS, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKHPX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKHSB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKHSH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKLPX, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKLSB, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_VUPKLSH, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_XOR, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STEP, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_PROMOTE, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_INSERT, RS6000_BTC_MISC) +RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SPLATS, RS6000_BTC_MISC) +RS6000_BUILTIN_EQUATE(ALTIVEC_BUILTIN_OVERLOADED_LAST, + ALTIVEC_BUILTIN_VEC_SPLATS) + +/* SPE builtins. */ +RS6000_BUILTIN(SPE_BUILTIN_EVADDW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVAND, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVANDC, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVDIVWS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVDIVWU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVEQV, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSADD, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSDIV, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSMUL, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSSUB, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLDDX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLDHX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLDWX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLHHESPLATX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLHHOSSPLATX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLHHOUSPLATX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHEX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHOSX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHOUX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHSPLATX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWWSPLATX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMERGEHI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMERGEHILO, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMERGELO, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMERGELOHI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEGSMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEGUMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEGUMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMFAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMFANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESMIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESSF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESSFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESSFAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESSFANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHESSIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEUMIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEUSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHEUSIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOGSMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOGUMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOGUMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMFAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMFANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSMIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSFAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSFANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOSSIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOUMIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOUSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMHOUSIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLSMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLSMIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLSSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLSSIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLUMIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLUSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWLUSIANW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSSF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSSFA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSSFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWSSFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWUMI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWUMIA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWUMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWUMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVNAND, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVNOR, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVOR, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVORC, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVRLW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSLW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSRWS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSRWU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTDDX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTDHX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTDWX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWHEX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWHOX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWWEX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWWOX, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSUBFW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVXOR, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVABS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVADDSMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVADDSSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVADDUMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVADDUSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVCNTLSW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVCNTLZW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVEXTSB, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVEXTSH, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSABS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCFSF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCFSI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCFUF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCFUI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCTSF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCTSI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCTSIZ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCTUF, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCTUI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCTUIZ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSNABS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSNEG, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMRA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVNEG, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVRNDW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSUBFSMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSUBFSSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSUBFUMIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSUBFUSIAAW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVADDIW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLDD, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLDH, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLDW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLHHESPLAT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLHHOSSPLAT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLHHOUSPLAT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHE, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHOS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHOU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWHSPLAT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVLWWSPLAT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVRLWI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSLWI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSRWIS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSRWIU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTDD, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTDH, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTDW, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWHE, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWHO, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWWE, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSTWWO, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSUBIFW, RS6000_BTC_MISC) + + /* Compares. */ +RS6000_BUILTIN(SPE_BUILTIN_EVCMPEQ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVCMPGTS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVCMPGTU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVCMPLTS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVCMPLTU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCMPEQ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCMPGT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSCMPLT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSTSTEQ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSTSTGT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVFSTSTLT, RS6000_BTC_MISC) + +/* EVSEL compares. */ +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPEQ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPGTS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPGTU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPLTS, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_CMPLTU, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSCMPEQ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSCMPGT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSCMPLT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSTSTEQ, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSTSTGT, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSEL_FSTSTLT, RS6000_BTC_MISC) + +RS6000_BUILTIN(SPE_BUILTIN_EVSPLATFI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVSPLATI, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSMAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHUSIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSSIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHSMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHUSIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHUMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSSFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMFAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGUMIAA, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSSFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMFAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGSMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_EVMWHGUMIAN, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_MTSPEFSCR, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_MFSPEFSCR, RS6000_BTC_MISC) +RS6000_BUILTIN(SPE_BUILTIN_BRINC, RS6000_BTC_MISC) + +/* PAIRED builtins. */ +RS6000_BUILTIN(PAIRED_BUILTIN_DIVV2SF3, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_ABSV2SF2, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_NEGV2SF2, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_SQRTV2SF2, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_ADDV2SF3, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_SUBV2SF3, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_RESV2SF2, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MULV2SF3, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MSUB, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MADD, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_NMSUB, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_NMADD, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_NABSV2SF2, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_SUM0, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_SUM1, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MULS0, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MULS1, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MERGE00, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MERGE01, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MERGE10, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MERGE11, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MADDS0, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_MADDS1, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_STX, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_LX, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_SELV2SF4, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_CMPU0, RS6000_BTC_MISC) +RS6000_BUILTIN(PAIRED_BUILTIN_CMPU1, RS6000_BTC_MISC) + + /* VSX builtins. */ +RS6000_BUILTIN(VSX_BUILTIN_LXSDX, RS6000_BTC_MEM) +RS6000_BUILTIN(VSX_BUILTIN_LXVD2X, RS6000_BTC_MEM) +RS6000_BUILTIN(VSX_BUILTIN_LXVDSX, RS6000_BTC_MEM) +RS6000_BUILTIN(VSX_BUILTIN_LXVW4X, RS6000_BTC_MEM) +RS6000_BUILTIN(VSX_BUILTIN_STXSDX, RS6000_BTC_MEM) +RS6000_BUILTIN(VSX_BUILTIN_STXVD2X, RS6000_BTC_MEM) +RS6000_BUILTIN(VSX_BUILTIN_STXVW4X, RS6000_BTC_MEM) +RS6000_BUILTIN(VSX_BUILTIN_XSABSDP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XSADDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCMPODP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCMPUDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCPSGNDP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XSCVDPSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCVDPSXDS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCVDPSXWS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCVDPUXDS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCVDPUXWS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCVSPDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCVSXDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSCVUXDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSDIVDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMADDADP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMADDMDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMAXDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMINDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMOVDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMSUBADP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMSUBMDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSMULDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSNABSDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSNEGDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSNMADDADP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSNMADDMDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSNMSUBADP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSNMSUBMDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSRDPI, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSRDPIC, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSRDPIM, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSRDPIP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSRDPIZ, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSREDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSRSQRTEDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSSQRTDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSSUBDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_CPSGNDP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_CPSGNSP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XSTDIVDP_FE, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSTDIVDP_FG, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSTSQRTDP_FE, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XSTSQRTDP_FG, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVABSDP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XVABSSP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XVADDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVADDSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGEDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGESP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQDP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPEQSP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGEDP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGESP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTDP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCMPGTSP_P, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCPSGNDP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XVCPSGNSP, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XVCVDPSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVDPSXDS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVDPSXWS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVDPUXDS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVDPUXDS_UNS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVDPUXWS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSPDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSPSXDS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSPSXWS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSPUXDS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSPUXWS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSXDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSXDSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSXWDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVSXWSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVUXDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVUXDDP_UNS, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVUXDSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVUXWDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVCVUXWSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVDIVDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVDIVSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMADDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMADDSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMAXDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMAXSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMINDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMINSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMSUBDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMSUBSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMULDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVMULSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNABSDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNABSSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNEGDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNEGSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNMADDDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNMADDSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNMSUBDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVNMSUBSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRDPI, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRDPIC, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRDPIM, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRDPIP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRDPIZ, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVREDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRESP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRSPI, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRSPIC, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRSPIM, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRSPIP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRSPIZ, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRSQRTEDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVRSQRTESP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVSQRTDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVSQRTSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVSUBDP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVSUBSP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTDIVDP_FE, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTDIVDP_FG, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTDIVSP_FE, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTDIVSP_FG, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTDP_FE, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTDP_FG, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTSP_FE, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XVTSQRTSP_FG, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_2DI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_4SI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_8HI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSEL_16QI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_2DI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_4SI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_8HI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VPERM_16QI_UNS, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXPERMDI_16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_CONCAT_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_CONCAT_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_SET_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_SET_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_SPLAT_2DF, RS6000_BTC_PURE) +RS6000_BUILTIN(VSX_BUILTIN_SPLAT_2DI, RS6000_BTC_PURE) +RS6000_BUILTIN(VSX_BUILTIN_XXMRGHW_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXMRGHW_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXMRGLW_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXMRGLW_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_8HI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_4SI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_4SF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_XXSLDWI_2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VEC_INIT_V2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VEC_INIT_V2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DI, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DF, RS6000_BTC_CONST) +RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DI, RS6000_BTC_CONST) + +/* VSX overloaded builtins, add the overloaded functions not present in + Altivec. */ +RS6000_BUILTIN(VSX_BUILTIN_VEC_MUL, RS6000_BTC_MISC) +RS6000_BUILTIN_EQUATE(VSX_BUILTIN_OVERLOADED_FIRST, + VSX_BUILTIN_VEC_MUL) +RS6000_BUILTIN(VSX_BUILTIN_VEC_MSUB, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_NMADD, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUITLIN_VEC_NMSUB, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_DIV, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_XXMRGHW, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_XXMRGLW, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_XXPERMDI, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSLDWI, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTD, RS6000_BTC_MISC) +RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTW, RS6000_BTC_MISC) +RS6000_BUILTIN_EQUATE(VSX_BUILTIN_OVERLOADED_LAST, + VSX_BUILTIN_VEC_XXSPLTW) + +/* Combined VSX/Altivec builtins. */ +RS6000_BUILTIN(VECTOR_BUILTIN_FLOAT_V4SI_V4SF, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VECTOR_BUILTIN_FIX_V4SF_V4SI, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(VECTOR_BUILTIN_FIXUNS_V4SF_V4SI, RS6000_BTC_FP_PURE) + +/* Power7 builtins, that aren't VSX instructions. */ +RS6000_BUILTIN(POWER7_BUILTIN_BPERMD, RS6000_BTC_CONST) + +/* Miscellaneous builtins. */ +RS6000_BUILTIN(RS6000_BUILTIN_RECIP, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(RS6000_BUILTIN_RECIPF, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(RS6000_BUILTIN_RSQRTF, RS6000_BTC_FP_PURE) +RS6000_BUILTIN(RS6000_BUILTIN_BSWAP_HI, RS6000_BTC_CONST) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index dea4a5334b0..88649ea0735 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -130,6 +130,8 @@ typedef struct GTY(()) machine_function 64-bits wide and is allocated early enough so that the offset does not overflow the 16-bit load/store offset field. */ rtx sdmode_stack_slot; + /* True if any VSX or ALTIVEC vector type was used. */ + bool vsx_or_altivec_used_p; } machine_function; /* Target cpu type */ @@ -836,6 +838,21 @@ struct processor_costs ppca2_cost = { }; +/* Table that classifies rs6000 builtin functions (pure, const, etc.). */ +#undef RS6000_BUILTIN +#undef RS6000_BUILTIN_EQUATE +#define RS6000_BUILTIN(NAME, TYPE) TYPE, +#define RS6000_BUILTIN_EQUATE(NAME, VALUE) + +static const enum rs6000_btc builtin_classify[(int)RS6000_BUILTIN_COUNT] = +{ +#include "rs6000-builtin.def" +}; + +#undef RS6000_BUILTIN +#undef RS6000_BUILTIN_EQUATE + + static bool rs6000_function_ok_for_sibcall (tree, tree); static const char *rs6000_invalid_within_doloop (const_rtx); static bool rs6000_legitimate_address_p (enum machine_mode, rtx, bool); @@ -898,7 +915,7 @@ static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED; #endif static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx); -static void rs6000_alloc_sdmode_stack_slot (void); +static void rs6000_expand_to_rtl_hook (void); static void rs6000_instantiate_decls (void); #if TARGET_XCOFF static void rs6000_xcoff_asm_output_anchor (rtx); @@ -1490,7 +1507,7 @@ static const struct attribute_spec rs6000_attribute_table[] = #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal #undef TARGET_EXPAND_TO_RTL_HOOK -#define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot +#define TARGET_EXPAND_TO_RTL_HOOK rs6000_expand_to_rtl_hook #undef TARGET_INSTANTIATE_DECLS #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls @@ -2266,6 +2283,13 @@ rs6000_override_options (const char *default_cpu) | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE) }; + /* Numerous experiment shows that IRA based loop pressure + calculation works better for RTL loop invariant motion on targets + with enough (>= 32) registers. It is an expensive optimization. + So it is on only for peak performance. */ + if (optimize >= 3) + flag_ira_loop_pressure = 1; + /* Set the pointer size. */ if (TARGET_64BIT) { @@ -8494,13 +8518,54 @@ def_builtin (int mask, const char *name, tree type, int code) { if ((mask & target_flags) || TARGET_PAIRED_FLOAT) { + tree t; if (rs6000_builtin_decls[code]) fatal_error ("internal error: builtin function to %s already processed.", name); - rs6000_builtin_decls[code] = + rs6000_builtin_decls[code] = t = add_builtin_function (name, type, code, BUILT_IN_MD, NULL, NULL_TREE); + + gcc_assert (code >= 0 && code < (int)RS6000_BUILTIN_COUNT); + switch (builtin_classify[code]) + { + default: + gcc_unreachable (); + + /* assume builtin can do anything. */ + case RS6000_BTC_MISC: + break; + + /* const function, function only depends on the inputs. */ + case RS6000_BTC_CONST: + TREE_READONLY (t) = 1; + TREE_NOTHROW (t) = 1; + break; + + /* pure function, function can read global memory. */ + case RS6000_BTC_PURE: + DECL_PURE_P (t) = 1; + TREE_NOTHROW (t) = 1; + break; + + /* Function is a math function. If rounding mode is on, then treat + the function as not reading global memory, but it can have + arbitrary side effects. If it is off, then assume the function is + a const function. This mimics the ATTR_MATHFN_FPROUNDING + attribute in builtin-attribute.def that is used for the math + functions. */ + case RS6000_BTC_FP_PURE: + TREE_NOTHROW (t) = 1; + if (flag_rounding_math) + { + DECL_PURE_P (t) = 1; + DECL_IS_NOVOPS (t) = 1; + } + else + TREE_READONLY (t) = 1; + break; + } } } @@ -13127,6 +13192,38 @@ rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED) return NULL_TREE; } +static tree +rs6000_check_vector_mode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED) +{ + /* Don't walk into types. */ + if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp)) + { + *walk_subtrees = 0; + return NULL_TREE; + } + + switch (TREE_CODE (*tp)) + { + case VAR_DECL: + case PARM_DECL: + case FIELD_DECL: + case RESULT_DECL: + case SSA_NAME: + case REAL_CST: + case INDIRECT_REF: + case ALIGN_INDIRECT_REF: + case MISALIGNED_INDIRECT_REF: + case VIEW_CONVERT_EXPR: + if (VECTOR_MODE_P (TYPE_MODE (TREE_TYPE (*tp)))) + return *tp; + break; + default: + break; + } + + return NULL_TREE; +} + enum reload_reg_type { GPR_REGISTER_TYPE, VECTOR_REGISTER_TYPE, @@ -13567,11 +13664,17 @@ rs6000_ira_cover_classes (void) return (TARGET_VSX) ? cover_vsx : cover_pre_vsx; } -/* Allocate a 64-bit stack slot to be used for copying SDmode - values through if this function has any SDmode references. */ +/* Scan the trees looking for certain types. + + Allocate a 64-bit stack slot to be used for copying SDmode values through if + this function has any SDmode references. + + If VSX, note whether any vector operation was done so we can set VRSAVE to + non-zero, even if we just use the floating point registers to tell the + kernel to save the vector registers. */ static void -rs6000_alloc_sdmode_stack_slot (void) +rs6000_expand_to_rtl_hook (void) { tree t; basic_block bb; @@ -13579,6 +13682,24 @@ rs6000_alloc_sdmode_stack_slot (void) gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX); + /* Check for vectors. */ + if (TARGET_VSX) + { + FOR_EACH_BB (bb) + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) + { + if (walk_gimple_op (gsi_stmt (gsi), rs6000_check_vector_mode, + NULL)) + { + cfun->machine->vsx_or_altivec_used_p = true; + goto found_vector; + } + } + found_vector: + ; + } + + /* Check for SDmode being used. */ FOR_EACH_BB (bb) for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) { @@ -16720,6 +16841,15 @@ compute_vrsave_mask (void) if (df_regs_ever_live_p (i)) mask |= ALTIVEC_REG_BIT (i); + /* If VSX is used, we might have used a traditional floating point register + in a vector mode without using any altivec registers. However the VRSAVE + register does not have room to indicate the floating point registers. + Modern kernels only look to see if the value is non-zero to determine if + they need to save the vector registers, so we just set an arbitrary + value if any vector type was used. */ + if (mask == 0 && TARGET_VSX && cfun->machine->vsx_or_altivec_used_p) + mask = 0xFFF; + if (mask == 0) return mask; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index c8ab4369a39..4b1ca3d635a 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1033,10 +1033,12 @@ extern unsigned rs6000_pointer_size; #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] -#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ - ((TARGET_32BIT && TARGET_POWERPC64 \ - && (GET_MODE_SIZE (MODE) > 4) \ - && INT_REGNO_P (REGNO)) ? 1 : 0) +#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ + (((TARGET_32BIT && TARGET_POWERPC64 \ + && (GET_MODE_SIZE (MODE) > 4) \ + && INT_REGNO_P (REGNO)) ? 1 : 0) \ + || (TARGET_VSX && FP_REGNO_P (REGNO) \ + && GET_MODE_SIZE (MODE) > 8)) #define VSX_VECTOR_MODE(MODE) \ ((MODE) == V4SFmode \ @@ -2424,964 +2426,35 @@ extern int optimize; extern int flag_expensive_optimizations; extern int frame_pointer_needed; +/* Classification of the builtin functions to properly set the declaration tree + flags. */ +enum rs6000_btc +{ + RS6000_BTC_MISC, /* assume builtin can do anything */ + RS6000_BTC_CONST, /* builtin is a 'const' function. */ + RS6000_BTC_PURE, /* builtin is a 'pure' function. */ + RS6000_BTC_FP_PURE /* builtin is 'pure' if rounding math. */ +}; + +/* Convenience macros to document the instruction type. */ +#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches memory */ +#define RS6000_BTC_SAT RS6000_BTC_MISC /* VMX saturate sets VSCR register */ + +#undef RS6000_BUILTIN +#undef RS6000_BUILTIN_EQUATE +#define RS6000_BUILTIN(NAME, TYPE) NAME, +#define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE, + enum rs6000_builtins { - /* AltiVec builtins. */ - ALTIVEC_BUILTIN_ST_INTERNAL_4si, - ALTIVEC_BUILTIN_LD_INTERNAL_4si, - ALTIVEC_BUILTIN_ST_INTERNAL_8hi, - ALTIVEC_BUILTIN_LD_INTERNAL_8hi, - ALTIVEC_BUILTIN_ST_INTERNAL_16qi, - ALTIVEC_BUILTIN_LD_INTERNAL_16qi, - ALTIVEC_BUILTIN_ST_INTERNAL_4sf, - ALTIVEC_BUILTIN_LD_INTERNAL_4sf, - ALTIVEC_BUILTIN_VADDUBM, - ALTIVEC_BUILTIN_VADDUHM, - ALTIVEC_BUILTIN_VADDUWM, - ALTIVEC_BUILTIN_VADDFP, - ALTIVEC_BUILTIN_VADDCUW, - ALTIVEC_BUILTIN_VADDUBS, - ALTIVEC_BUILTIN_VADDSBS, - ALTIVEC_BUILTIN_VADDUHS, - ALTIVEC_BUILTIN_VADDSHS, - ALTIVEC_BUILTIN_VADDUWS, - ALTIVEC_BUILTIN_VADDSWS, - ALTIVEC_BUILTIN_VAND, - ALTIVEC_BUILTIN_VANDC, - ALTIVEC_BUILTIN_VAVGUB, - ALTIVEC_BUILTIN_VAVGSB, - ALTIVEC_BUILTIN_VAVGUH, - ALTIVEC_BUILTIN_VAVGSH, - ALTIVEC_BUILTIN_VAVGUW, - ALTIVEC_BUILTIN_VAVGSW, - ALTIVEC_BUILTIN_VCFUX, - ALTIVEC_BUILTIN_VCFSX, - ALTIVEC_BUILTIN_VCTSXS, - ALTIVEC_BUILTIN_VCTUXS, - ALTIVEC_BUILTIN_VCMPBFP, - ALTIVEC_BUILTIN_VCMPEQUB, - ALTIVEC_BUILTIN_VCMPEQUH, - ALTIVEC_BUILTIN_VCMPEQUW, - ALTIVEC_BUILTIN_VCMPEQFP, - ALTIVEC_BUILTIN_VCMPGEFP, - ALTIVEC_BUILTIN_VCMPGTUB, - ALTIVEC_BUILTIN_VCMPGTSB, - ALTIVEC_BUILTIN_VCMPGTUH, - ALTIVEC_BUILTIN_VCMPGTSH, - ALTIVEC_BUILTIN_VCMPGTUW, - ALTIVEC_BUILTIN_VCMPGTSW, - ALTIVEC_BUILTIN_VCMPGTFP, - ALTIVEC_BUILTIN_VEXPTEFP, - ALTIVEC_BUILTIN_VLOGEFP, - ALTIVEC_BUILTIN_VMADDFP, - ALTIVEC_BUILTIN_VMAXUB, - ALTIVEC_BUILTIN_VMAXSB, - ALTIVEC_BUILTIN_VMAXUH, - ALTIVEC_BUILTIN_VMAXSH, - ALTIVEC_BUILTIN_VMAXUW, - ALTIVEC_BUILTIN_VMAXSW, - ALTIVEC_BUILTIN_VMAXFP, - ALTIVEC_BUILTIN_VMHADDSHS, - ALTIVEC_BUILTIN_VMHRADDSHS, - ALTIVEC_BUILTIN_VMLADDUHM, - ALTIVEC_BUILTIN_VMRGHB, - ALTIVEC_BUILTIN_VMRGHH, - ALTIVEC_BUILTIN_VMRGHW, - ALTIVEC_BUILTIN_VMRGLB, - ALTIVEC_BUILTIN_VMRGLH, - ALTIVEC_BUILTIN_VMRGLW, - ALTIVEC_BUILTIN_VMSUMUBM, - ALTIVEC_BUILTIN_VMSUMMBM, - ALTIVEC_BUILTIN_VMSUMUHM, - ALTIVEC_BUILTIN_VMSUMSHM, - ALTIVEC_BUILTIN_VMSUMUHS, - ALTIVEC_BUILTIN_VMSUMSHS, - ALTIVEC_BUILTIN_VMINUB, - ALTIVEC_BUILTIN_VMINSB, - ALTIVEC_BUILTIN_VMINUH, - ALTIVEC_BUILTIN_VMINSH, - ALTIVEC_BUILTIN_VMINUW, - ALTIVEC_BUILTIN_VMINSW, - ALTIVEC_BUILTIN_VMINFP, - ALTIVEC_BUILTIN_VMULEUB, - ALTIVEC_BUILTIN_VMULEUB_UNS, - ALTIVEC_BUILTIN_VMULESB, - ALTIVEC_BUILTIN_VMULEUH, - ALTIVEC_BUILTIN_VMULEUH_UNS, - ALTIVEC_BUILTIN_VMULESH, - ALTIVEC_BUILTIN_VMULOUB, - ALTIVEC_BUILTIN_VMULOUB_UNS, - ALTIVEC_BUILTIN_VMULOSB, - ALTIVEC_BUILTIN_VMULOUH, - ALTIVEC_BUILTIN_VMULOUH_UNS, - ALTIVEC_BUILTIN_VMULOSH, - ALTIVEC_BUILTIN_VNMSUBFP, - ALTIVEC_BUILTIN_VNOR, - ALTIVEC_BUILTIN_VOR, - ALTIVEC_BUILTIN_VSEL_2DF, /* needed for VSX */ - ALTIVEC_BUILTIN_VSEL_2DI, /* needed for VSX */ - ALTIVEC_BUILTIN_VSEL_4SI, - ALTIVEC_BUILTIN_VSEL_4SF, - ALTIVEC_BUILTIN_VSEL_8HI, - ALTIVEC_BUILTIN_VSEL_16QI, - ALTIVEC_BUILTIN_VSEL_2DI_UNS, - ALTIVEC_BUILTIN_VSEL_4SI_UNS, - ALTIVEC_BUILTIN_VSEL_8HI_UNS, - ALTIVEC_BUILTIN_VSEL_16QI_UNS, - ALTIVEC_BUILTIN_VPERM_2DF, /* needed for VSX */ - ALTIVEC_BUILTIN_VPERM_2DI, /* needed for VSX */ - ALTIVEC_BUILTIN_VPERM_4SI, - ALTIVEC_BUILTIN_VPERM_4SF, - ALTIVEC_BUILTIN_VPERM_8HI, - ALTIVEC_BUILTIN_VPERM_16QI, - ALTIVEC_BUILTIN_VPERM_2DI_UNS, - ALTIVEC_BUILTIN_VPERM_4SI_UNS, - ALTIVEC_BUILTIN_VPERM_8HI_UNS, - ALTIVEC_BUILTIN_VPERM_16QI_UNS, - ALTIVEC_BUILTIN_VPKUHUM, - ALTIVEC_BUILTIN_VPKUWUM, - ALTIVEC_BUILTIN_VPKPX, - ALTIVEC_BUILTIN_VPKUHSS, - ALTIVEC_BUILTIN_VPKSHSS, - ALTIVEC_BUILTIN_VPKUWSS, - ALTIVEC_BUILTIN_VPKSWSS, - ALTIVEC_BUILTIN_VPKUHUS, - ALTIVEC_BUILTIN_VPKSHUS, - ALTIVEC_BUILTIN_VPKUWUS, - ALTIVEC_BUILTIN_VPKSWUS, - ALTIVEC_BUILTIN_VREFP, - ALTIVEC_BUILTIN_VRFIM, - ALTIVEC_BUILTIN_VRFIN, - ALTIVEC_BUILTIN_VRFIP, - ALTIVEC_BUILTIN_VRFIZ, - ALTIVEC_BUILTIN_VRLB, - ALTIVEC_BUILTIN_VRLH, - ALTIVEC_BUILTIN_VRLW, - ALTIVEC_BUILTIN_VRSQRTEFP, - ALTIVEC_BUILTIN_VSLB, - ALTIVEC_BUILTIN_VSLH, - ALTIVEC_BUILTIN_VSLW, - ALTIVEC_BUILTIN_VSL, - ALTIVEC_BUILTIN_VSLO, - ALTIVEC_BUILTIN_VSPLTB, - ALTIVEC_BUILTIN_VSPLTH, - ALTIVEC_BUILTIN_VSPLTW, - ALTIVEC_BUILTIN_VSPLTISB, - ALTIVEC_BUILTIN_VSPLTISH, - ALTIVEC_BUILTIN_VSPLTISW, - ALTIVEC_BUILTIN_VSRB, - ALTIVEC_BUILTIN_VSRH, - ALTIVEC_BUILTIN_VSRW, - ALTIVEC_BUILTIN_VSRAB, - ALTIVEC_BUILTIN_VSRAH, - ALTIVEC_BUILTIN_VSRAW, - ALTIVEC_BUILTIN_VSR, - ALTIVEC_BUILTIN_VSRO, - ALTIVEC_BUILTIN_VSUBUBM, - ALTIVEC_BUILTIN_VSUBUHM, - ALTIVEC_BUILTIN_VSUBUWM, - ALTIVEC_BUILTIN_VSUBFP, - ALTIVEC_BUILTIN_VSUBCUW, - ALTIVEC_BUILTIN_VSUBUBS, - ALTIVEC_BUILTIN_VSUBSBS, - ALTIVEC_BUILTIN_VSUBUHS, - ALTIVEC_BUILTIN_VSUBSHS, - ALTIVEC_BUILTIN_VSUBUWS, - ALTIVEC_BUILTIN_VSUBSWS, - ALTIVEC_BUILTIN_VSUM4UBS, - ALTIVEC_BUILTIN_VSUM4SBS, - ALTIVEC_BUILTIN_VSUM4SHS, - ALTIVEC_BUILTIN_VSUM2SWS, - ALTIVEC_BUILTIN_VSUMSWS, - ALTIVEC_BUILTIN_VXOR, - ALTIVEC_BUILTIN_VSLDOI_16QI, - ALTIVEC_BUILTIN_VSLDOI_8HI, - ALTIVEC_BUILTIN_VSLDOI_4SI, - ALTIVEC_BUILTIN_VSLDOI_4SF, - ALTIVEC_BUILTIN_VUPKHSB, - ALTIVEC_BUILTIN_VUPKHPX, - ALTIVEC_BUILTIN_VUPKHSH, - ALTIVEC_BUILTIN_VUPKLSB, - ALTIVEC_BUILTIN_VUPKLPX, - ALTIVEC_BUILTIN_VUPKLSH, - ALTIVEC_BUILTIN_MTVSCR, - ALTIVEC_BUILTIN_MFVSCR, - ALTIVEC_BUILTIN_DSSALL, - ALTIVEC_BUILTIN_DSS, - ALTIVEC_BUILTIN_LVSL, - ALTIVEC_BUILTIN_LVSR, - ALTIVEC_BUILTIN_DSTT, - ALTIVEC_BUILTIN_DSTST, - ALTIVEC_BUILTIN_DSTSTT, - ALTIVEC_BUILTIN_DST, - ALTIVEC_BUILTIN_LVEBX, - ALTIVEC_BUILTIN_LVEHX, - ALTIVEC_BUILTIN_LVEWX, - ALTIVEC_BUILTIN_LVXL, - ALTIVEC_BUILTIN_LVX, - ALTIVEC_BUILTIN_STVX, - ALTIVEC_BUILTIN_LVLX, - ALTIVEC_BUILTIN_LVLXL, - ALTIVEC_BUILTIN_LVRX, - ALTIVEC_BUILTIN_LVRXL, - ALTIVEC_BUILTIN_STVEBX, - ALTIVEC_BUILTIN_STVEHX, - ALTIVEC_BUILTIN_STVEWX, - ALTIVEC_BUILTIN_STVXL, - ALTIVEC_BUILTIN_STVLX, - ALTIVEC_BUILTIN_STVLXL, - ALTIVEC_BUILTIN_STVRX, - ALTIVEC_BUILTIN_STVRXL, - ALTIVEC_BUILTIN_VCMPBFP_P, - ALTIVEC_BUILTIN_VCMPEQFP_P, - ALTIVEC_BUILTIN_VCMPEQUB_P, - ALTIVEC_BUILTIN_VCMPEQUH_P, - ALTIVEC_BUILTIN_VCMPEQUW_P, - ALTIVEC_BUILTIN_VCMPGEFP_P, - ALTIVEC_BUILTIN_VCMPGTFP_P, - ALTIVEC_BUILTIN_VCMPGTSB_P, - ALTIVEC_BUILTIN_VCMPGTSH_P, - ALTIVEC_BUILTIN_VCMPGTSW_P, - ALTIVEC_BUILTIN_VCMPGTUB_P, - ALTIVEC_BUILTIN_VCMPGTUH_P, - ALTIVEC_BUILTIN_VCMPGTUW_P, - ALTIVEC_BUILTIN_ABSS_V4SI, - ALTIVEC_BUILTIN_ABSS_V8HI, - ALTIVEC_BUILTIN_ABSS_V16QI, - ALTIVEC_BUILTIN_ABS_V4SI, - ALTIVEC_BUILTIN_ABS_V4SF, - ALTIVEC_BUILTIN_ABS_V8HI, - ALTIVEC_BUILTIN_ABS_V16QI, - ALTIVEC_BUILTIN_MASK_FOR_LOAD, - ALTIVEC_BUILTIN_MASK_FOR_STORE, - ALTIVEC_BUILTIN_VEC_INIT_V4SI, - ALTIVEC_BUILTIN_VEC_INIT_V8HI, - ALTIVEC_BUILTIN_VEC_INIT_V16QI, - ALTIVEC_BUILTIN_VEC_INIT_V4SF, - ALTIVEC_BUILTIN_VEC_SET_V4SI, - ALTIVEC_BUILTIN_VEC_SET_V8HI, - ALTIVEC_BUILTIN_VEC_SET_V16QI, - ALTIVEC_BUILTIN_VEC_SET_V4SF, - ALTIVEC_BUILTIN_VEC_EXT_V4SI, - ALTIVEC_BUILTIN_VEC_EXT_V8HI, - ALTIVEC_BUILTIN_VEC_EXT_V16QI, - ALTIVEC_BUILTIN_VEC_EXT_V4SF, - ALTIVEC_BUILTIN_COPYSIGN_V4SF, - - /* Altivec overloaded builtins. */ - ALTIVEC_BUILTIN_VCMPEQ_P, - ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P, - ALTIVEC_BUILTIN_VCMPGT_P, - ALTIVEC_BUILTIN_VCMPGE_P, - ALTIVEC_BUILTIN_VEC_ABS, - ALTIVEC_BUILTIN_VEC_ABSS, - ALTIVEC_BUILTIN_VEC_ADD, - ALTIVEC_BUILTIN_VEC_ADDC, - ALTIVEC_BUILTIN_VEC_ADDS, - ALTIVEC_BUILTIN_VEC_AND, - ALTIVEC_BUILTIN_VEC_ANDC, - ALTIVEC_BUILTIN_VEC_AVG, - ALTIVEC_BUILTIN_VEC_EXTRACT, - ALTIVEC_BUILTIN_VEC_CEIL, - ALTIVEC_BUILTIN_VEC_CMPB, - ALTIVEC_BUILTIN_VEC_CMPEQ, - ALTIVEC_BUILTIN_VEC_CMPEQUB, - ALTIVEC_BUILTIN_VEC_CMPEQUH, - ALTIVEC_BUILTIN_VEC_CMPEQUW, - ALTIVEC_BUILTIN_VEC_CMPGE, - ALTIVEC_BUILTIN_VEC_CMPGT, - ALTIVEC_BUILTIN_VEC_CMPLE, - ALTIVEC_BUILTIN_VEC_CMPLT, - ALTIVEC_BUILTIN_VEC_COPYSIGN, - ALTIVEC_BUILTIN_VEC_CTF, - ALTIVEC_BUILTIN_VEC_CTS, - ALTIVEC_BUILTIN_VEC_CTU, - ALTIVEC_BUILTIN_VEC_DST, - ALTIVEC_BUILTIN_VEC_DSTST, - ALTIVEC_BUILTIN_VEC_DSTSTT, - ALTIVEC_BUILTIN_VEC_DSTT, - ALTIVEC_BUILTIN_VEC_EXPTE, - ALTIVEC_BUILTIN_VEC_FLOOR, - ALTIVEC_BUILTIN_VEC_LD, - ALTIVEC_BUILTIN_VEC_LDE, - ALTIVEC_BUILTIN_VEC_LDL, - ALTIVEC_BUILTIN_VEC_LOGE, - ALTIVEC_BUILTIN_VEC_LVEBX, - ALTIVEC_BUILTIN_VEC_LVEHX, - ALTIVEC_BUILTIN_VEC_LVEWX, - ALTIVEC_BUILTIN_VEC_LVLX, - ALTIVEC_BUILTIN_VEC_LVLXL, - ALTIVEC_BUILTIN_VEC_LVRX, - ALTIVEC_BUILTIN_VEC_LVRXL, - ALTIVEC_BUILTIN_VEC_LVSL, - ALTIVEC_BUILTIN_VEC_LVSR, - ALTIVEC_BUILTIN_VEC_MADD, - ALTIVEC_BUILTIN_VEC_MADDS, - ALTIVEC_BUILTIN_VEC_MAX, - ALTIVEC_BUILTIN_VEC_MERGEH, - ALTIVEC_BUILTIN_VEC_MERGEL, - ALTIVEC_BUILTIN_VEC_MIN, - ALTIVEC_BUILTIN_VEC_MLADD, - ALTIVEC_BUILTIN_VEC_MPERM, - ALTIVEC_BUILTIN_VEC_MRADDS, - ALTIVEC_BUILTIN_VEC_MRGHB, - ALTIVEC_BUILTIN_VEC_MRGHH, - ALTIVEC_BUILTIN_VEC_MRGHW, - ALTIVEC_BUILTIN_VEC_MRGLB, - ALTIVEC_BUILTIN_VEC_MRGLH, - ALTIVEC_BUILTIN_VEC_MRGLW, - ALTIVEC_BUILTIN_VEC_MSUM, - ALTIVEC_BUILTIN_VEC_MSUMS, - ALTIVEC_BUILTIN_VEC_MTVSCR, - ALTIVEC_BUILTIN_VEC_MULE, - ALTIVEC_BUILTIN_VEC_MULO, - ALTIVEC_BUILTIN_VEC_NEARBYINT, - ALTIVEC_BUILTIN_VEC_NMSUB, - ALTIVEC_BUILTIN_VEC_NOR, - ALTIVEC_BUILTIN_VEC_OR, - ALTIVEC_BUILTIN_VEC_PACK, - ALTIVEC_BUILTIN_VEC_PACKPX, - ALTIVEC_BUILTIN_VEC_PACKS, - ALTIVEC_BUILTIN_VEC_PACKSU, - ALTIVEC_BUILTIN_VEC_PERM, - ALTIVEC_BUILTIN_VEC_RE, - ALTIVEC_BUILTIN_VEC_RL, - ALTIVEC_BUILTIN_VEC_RINT, - ALTIVEC_BUILTIN_VEC_ROUND, - ALTIVEC_BUILTIN_VEC_RSQRTE, - ALTIVEC_BUILTIN_VEC_SEL, - ALTIVEC_BUILTIN_VEC_SL, - ALTIVEC_BUILTIN_VEC_SLD, - ALTIVEC_BUILTIN_VEC_SLL, - ALTIVEC_BUILTIN_VEC_SLO, - ALTIVEC_BUILTIN_VEC_SPLAT, - ALTIVEC_BUILTIN_VEC_SPLAT_S16, - ALTIVEC_BUILTIN_VEC_SPLAT_S32, - ALTIVEC_BUILTIN_VEC_SPLAT_S8, - ALTIVEC_BUILTIN_VEC_SPLAT_U16, - ALTIVEC_BUILTIN_VEC_SPLAT_U32, - ALTIVEC_BUILTIN_VEC_SPLAT_U8, - ALTIVEC_BUILTIN_VEC_SPLTB, - ALTIVEC_BUILTIN_VEC_SPLTH, - ALTIVEC_BUILTIN_VEC_SPLTW, - ALTIVEC_BUILTIN_VEC_SQRT, - ALTIVEC_BUILTIN_VEC_SR, - ALTIVEC_BUILTIN_VEC_SRA, - ALTIVEC_BUILTIN_VEC_SRL, - ALTIVEC_BUILTIN_VEC_SRO, - ALTIVEC_BUILTIN_VEC_ST, - ALTIVEC_BUILTIN_VEC_STE, - ALTIVEC_BUILTIN_VEC_STL, - ALTIVEC_BUILTIN_VEC_STVEBX, - ALTIVEC_BUILTIN_VEC_STVEHX, - ALTIVEC_BUILTIN_VEC_STVEWX, - ALTIVEC_BUILTIN_VEC_STVLX, - ALTIVEC_BUILTIN_VEC_STVLXL, - ALTIVEC_BUILTIN_VEC_STVRX, - ALTIVEC_BUILTIN_VEC_STVRXL, - ALTIVEC_BUILTIN_VEC_SUB, - ALTIVEC_BUILTIN_VEC_SUBC, - ALTIVEC_BUILTIN_VEC_SUBS, - ALTIVEC_BUILTIN_VEC_SUM2S, - ALTIVEC_BUILTIN_VEC_SUM4S, - ALTIVEC_BUILTIN_VEC_SUMS, - ALTIVEC_BUILTIN_VEC_TRUNC, - ALTIVEC_BUILTIN_VEC_UNPACKH, - ALTIVEC_BUILTIN_VEC_UNPACKL, - ALTIVEC_BUILTIN_VEC_VADDFP, - ALTIVEC_BUILTIN_VEC_VADDSBS, - ALTIVEC_BUILTIN_VEC_VADDSHS, - ALTIVEC_BUILTIN_VEC_VADDSWS, - ALTIVEC_BUILTIN_VEC_VADDUBM, - ALTIVEC_BUILTIN_VEC_VADDUBS, - ALTIVEC_BUILTIN_VEC_VADDUHM, - ALTIVEC_BUILTIN_VEC_VADDUHS, - ALTIVEC_BUILTIN_VEC_VADDUWM, - ALTIVEC_BUILTIN_VEC_VADDUWS, - ALTIVEC_BUILTIN_VEC_VAVGSB, - ALTIVEC_BUILTIN_VEC_VAVGSH, - ALTIVEC_BUILTIN_VEC_VAVGSW, - ALTIVEC_BUILTIN_VEC_VAVGUB, - ALTIVEC_BUILTIN_VEC_VAVGUH, - ALTIVEC_BUILTIN_VEC_VAVGUW, - ALTIVEC_BUILTIN_VEC_VCFSX, - ALTIVEC_BUILTIN_VEC_VCFUX, - ALTIVEC_BUILTIN_VEC_VCMPEQFP, - ALTIVEC_BUILTIN_VEC_VCMPEQUB, - ALTIVEC_BUILTIN_VEC_VCMPEQUH, - ALTIVEC_BUILTIN_VEC_VCMPEQUW, - ALTIVEC_BUILTIN_VEC_VCMPGTFP, - ALTIVEC_BUILTIN_VEC_VCMPGTSB, - ALTIVEC_BUILTIN_VEC_VCMPGTSH, - ALTIVEC_BUILTIN_VEC_VCMPGTSW, - ALTIVEC_BUILTIN_VEC_VCMPGTUB, - ALTIVEC_BUILTIN_VEC_VCMPGTUH, - ALTIVEC_BUILTIN_VEC_VCMPGTUW, - ALTIVEC_BUILTIN_VEC_VMAXFP, - ALTIVEC_BUILTIN_VEC_VMAXSB, - ALTIVEC_BUILTIN_VEC_VMAXSH, - ALTIVEC_BUILTIN_VEC_VMAXSW, - ALTIVEC_BUILTIN_VEC_VMAXUB, - ALTIVEC_BUILTIN_VEC_VMAXUH, - ALTIVEC_BUILTIN_VEC_VMAXUW, - ALTIVEC_BUILTIN_VEC_VMINFP, - ALTIVEC_BUILTIN_VEC_VMINSB, - ALTIVEC_BUILTIN_VEC_VMINSH, - ALTIVEC_BUILTIN_VEC_VMINSW, - ALTIVEC_BUILTIN_VEC_VMINUB, - ALTIVEC_BUILTIN_VEC_VMINUH, - ALTIVEC_BUILTIN_VEC_VMINUW, - ALTIVEC_BUILTIN_VEC_VMRGHB, - ALTIVEC_BUILTIN_VEC_VMRGHH, - ALTIVEC_BUILTIN_VEC_VMRGHW, - ALTIVEC_BUILTIN_VEC_VMRGLB, - ALTIVEC_BUILTIN_VEC_VMRGLH, - ALTIVEC_BUILTIN_VEC_VMRGLW, - ALTIVEC_BUILTIN_VEC_VMSUMMBM, - ALTIVEC_BUILTIN_VEC_VMSUMSHM, - ALTIVEC_BUILTIN_VEC_VMSUMSHS, - ALTIVEC_BUILTIN_VEC_VMSUMUBM, - ALTIVEC_BUILTIN_VEC_VMSUMUHM, - ALTIVEC_BUILTIN_VEC_VMSUMUHS, - ALTIVEC_BUILTIN_VEC_VMULESB, - ALTIVEC_BUILTIN_VEC_VMULESH, - ALTIVEC_BUILTIN_VEC_VMULEUB, - ALTIVEC_BUILTIN_VEC_VMULEUH, - ALTIVEC_BUILTIN_VEC_VMULOSB, - ALTIVEC_BUILTIN_VEC_VMULOSH, - ALTIVEC_BUILTIN_VEC_VMULOUB, - ALTIVEC_BUILTIN_VEC_VMULOUH, - ALTIVEC_BUILTIN_VEC_VPKSHSS, - ALTIVEC_BUILTIN_VEC_VPKSHUS, - ALTIVEC_BUILTIN_VEC_VPKSWSS, - ALTIVEC_BUILTIN_VEC_VPKSWUS, - ALTIVEC_BUILTIN_VEC_VPKUHUM, - ALTIVEC_BUILTIN_VEC_VPKUHUS, - ALTIVEC_BUILTIN_VEC_VPKUWUM, - ALTIVEC_BUILTIN_VEC_VPKUWUS, - ALTIVEC_BUILTIN_VEC_VRLB, - ALTIVEC_BUILTIN_VEC_VRLH, - ALTIVEC_BUILTIN_VEC_VRLW, - ALTIVEC_BUILTIN_VEC_VSLB, - ALTIVEC_BUILTIN_VEC_VSLH, - ALTIVEC_BUILTIN_VEC_VSLW, - ALTIVEC_BUILTIN_VEC_VSPLTB, - ALTIVEC_BUILTIN_VEC_VSPLTH, - ALTIVEC_BUILTIN_VEC_VSPLTW, - ALTIVEC_BUILTIN_VEC_VSRAB, - ALTIVEC_BUILTIN_VEC_VSRAH, - ALTIVEC_BUILTIN_VEC_VSRAW, - ALTIVEC_BUILTIN_VEC_VSRB, - ALTIVEC_BUILTIN_VEC_VSRH, - ALTIVEC_BUILTIN_VEC_VSRW, - ALTIVEC_BUILTIN_VEC_VSUBFP, - ALTIVEC_BUILTIN_VEC_VSUBSBS, - ALTIVEC_BUILTIN_VEC_VSUBSHS, - ALTIVEC_BUILTIN_VEC_VSUBSWS, - ALTIVEC_BUILTIN_VEC_VSUBUBM, - ALTIVEC_BUILTIN_VEC_VSUBUBS, - ALTIVEC_BUILTIN_VEC_VSUBUHM, - ALTIVEC_BUILTIN_VEC_VSUBUHS, - ALTIVEC_BUILTIN_VEC_VSUBUWM, - ALTIVEC_BUILTIN_VEC_VSUBUWS, - ALTIVEC_BUILTIN_VEC_VSUM4SBS, - ALTIVEC_BUILTIN_VEC_VSUM4SHS, - ALTIVEC_BUILTIN_VEC_VSUM4UBS, - ALTIVEC_BUILTIN_VEC_VUPKHPX, - ALTIVEC_BUILTIN_VEC_VUPKHSB, - ALTIVEC_BUILTIN_VEC_VUPKHSH, - ALTIVEC_BUILTIN_VEC_VUPKLPX, - ALTIVEC_BUILTIN_VEC_VUPKLSB, - ALTIVEC_BUILTIN_VEC_VUPKLSH, - ALTIVEC_BUILTIN_VEC_XOR, - ALTIVEC_BUILTIN_VEC_STEP, - ALTIVEC_BUILTIN_VEC_PROMOTE, - ALTIVEC_BUILTIN_VEC_INSERT, - ALTIVEC_BUILTIN_VEC_SPLATS, - ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_SPLATS, - - /* SPE builtins. */ - SPE_BUILTIN_EVADDW, - SPE_BUILTIN_EVAND, - SPE_BUILTIN_EVANDC, - SPE_BUILTIN_EVDIVWS, - SPE_BUILTIN_EVDIVWU, - SPE_BUILTIN_EVEQV, - SPE_BUILTIN_EVFSADD, - SPE_BUILTIN_EVFSDIV, - SPE_BUILTIN_EVFSMUL, - SPE_BUILTIN_EVFSSUB, - SPE_BUILTIN_EVLDDX, - SPE_BUILTIN_EVLDHX, - SPE_BUILTIN_EVLDWX, - SPE_BUILTIN_EVLHHESPLATX, - SPE_BUILTIN_EVLHHOSSPLATX, - SPE_BUILTIN_EVLHHOUSPLATX, - SPE_BUILTIN_EVLWHEX, - SPE_BUILTIN_EVLWHOSX, - SPE_BUILTIN_EVLWHOUX, - SPE_BUILTIN_EVLWHSPLATX, - SPE_BUILTIN_EVLWWSPLATX, - SPE_BUILTIN_EVMERGEHI, - SPE_BUILTIN_EVMERGEHILO, - SPE_BUILTIN_EVMERGELO, - SPE_BUILTIN_EVMERGELOHI, - SPE_BUILTIN_EVMHEGSMFAA, - SPE_BUILTIN_EVMHEGSMFAN, - SPE_BUILTIN_EVMHEGSMIAA, - SPE_BUILTIN_EVMHEGSMIAN, - SPE_BUILTIN_EVMHEGUMIAA, - SPE_BUILTIN_EVMHEGUMIAN, - SPE_BUILTIN_EVMHESMF, - SPE_BUILTIN_EVMHESMFA, - SPE_BUILTIN_EVMHESMFAAW, - SPE_BUILTIN_EVMHESMFANW, - SPE_BUILTIN_EVMHESMI, - SPE_BUILTIN_EVMHESMIA, - SPE_BUILTIN_EVMHESMIAAW, - SPE_BUILTIN_EVMHESMIANW, - SPE_BUILTIN_EVMHESSF, - SPE_BUILTIN_EVMHESSFA, - SPE_BUILTIN_EVMHESSFAAW, - SPE_BUILTIN_EVMHESSFANW, - SPE_BUILTIN_EVMHESSIAAW, - SPE_BUILTIN_EVMHESSIANW, - SPE_BUILTIN_EVMHEUMI, - SPE_BUILTIN_EVMHEUMIA, - SPE_BUILTIN_EVMHEUMIAAW, - SPE_BUILTIN_EVMHEUMIANW, - SPE_BUILTIN_EVMHEUSIAAW, - SPE_BUILTIN_EVMHEUSIANW, - SPE_BUILTIN_EVMHOGSMFAA, - SPE_BUILTIN_EVMHOGSMFAN, - SPE_BUILTIN_EVMHOGSMIAA, - SPE_BUILTIN_EVMHOGSMIAN, - SPE_BUILTIN_EVMHOGUMIAA, - SPE_BUILTIN_EVMHOGUMIAN, - SPE_BUILTIN_EVMHOSMF, - SPE_BUILTIN_EVMHOSMFA, - SPE_BUILTIN_EVMHOSMFAAW, - SPE_BUILTIN_EVMHOSMFANW, - SPE_BUILTIN_EVMHOSMI, - SPE_BUILTIN_EVMHOSMIA, - SPE_BUILTIN_EVMHOSMIAAW, - SPE_BUILTIN_EVMHOSMIANW, - SPE_BUILTIN_EVMHOSSF, - SPE_BUILTIN_EVMHOSSFA, - SPE_BUILTIN_EVMHOSSFAAW, - SPE_BUILTIN_EVMHOSSFANW, - SPE_BUILTIN_EVMHOSSIAAW, - SPE_BUILTIN_EVMHOSSIANW, - SPE_BUILTIN_EVMHOUMI, - SPE_BUILTIN_EVMHOUMIA, - SPE_BUILTIN_EVMHOUMIAAW, - SPE_BUILTIN_EVMHOUMIANW, - SPE_BUILTIN_EVMHOUSIAAW, - SPE_BUILTIN_EVMHOUSIANW, - SPE_BUILTIN_EVMWHSMF, - SPE_BUILTIN_EVMWHSMFA, - SPE_BUILTIN_EVMWHSMI, - SPE_BUILTIN_EVMWHSMIA, - SPE_BUILTIN_EVMWHSSF, - SPE_BUILTIN_EVMWHSSFA, - SPE_BUILTIN_EVMWHUMI, - SPE_BUILTIN_EVMWHUMIA, - SPE_BUILTIN_EVMWLSMIAAW, - SPE_BUILTIN_EVMWLSMIANW, - SPE_BUILTIN_EVMWLSSIAAW, - SPE_BUILTIN_EVMWLSSIANW, - SPE_BUILTIN_EVMWLUMI, - SPE_BUILTIN_EVMWLUMIA, - SPE_BUILTIN_EVMWLUMIAAW, - SPE_BUILTIN_EVMWLUMIANW, - SPE_BUILTIN_EVMWLUSIAAW, - SPE_BUILTIN_EVMWLUSIANW, - SPE_BUILTIN_EVMWSMF, - SPE_BUILTIN_EVMWSMFA, - SPE_BUILTIN_EVMWSMFAA, - SPE_BUILTIN_EVMWSMFAN, - SPE_BUILTIN_EVMWSMI, - SPE_BUILTIN_EVMWSMIA, - SPE_BUILTIN_EVMWSMIAA, - SPE_BUILTIN_EVMWSMIAN, - SPE_BUILTIN_EVMWHSSFAA, - SPE_BUILTIN_EVMWSSF, - SPE_BUILTIN_EVMWSSFA, - SPE_BUILTIN_EVMWSSFAA, - SPE_BUILTIN_EVMWSSFAN, - SPE_BUILTIN_EVMWUMI, - SPE_BUILTIN_EVMWUMIA, - SPE_BUILTIN_EVMWUMIAA, - SPE_BUILTIN_EVMWUMIAN, - SPE_BUILTIN_EVNAND, - SPE_BUILTIN_EVNOR, - SPE_BUILTIN_EVOR, - SPE_BUILTIN_EVORC, - SPE_BUILTIN_EVRLW, - SPE_BUILTIN_EVSLW, - SPE_BUILTIN_EVSRWS, - SPE_BUILTIN_EVSRWU, - SPE_BUILTIN_EVSTDDX, - SPE_BUILTIN_EVSTDHX, - SPE_BUILTIN_EVSTDWX, - SPE_BUILTIN_EVSTWHEX, - SPE_BUILTIN_EVSTWHOX, - SPE_BUILTIN_EVSTWWEX, - SPE_BUILTIN_EVSTWWOX, - SPE_BUILTIN_EVSUBFW, - SPE_BUILTIN_EVXOR, - SPE_BUILTIN_EVABS, - SPE_BUILTIN_EVADDSMIAAW, - SPE_BUILTIN_EVADDSSIAAW, - SPE_BUILTIN_EVADDUMIAAW, - SPE_BUILTIN_EVADDUSIAAW, - SPE_BUILTIN_EVCNTLSW, - SPE_BUILTIN_EVCNTLZW, - SPE_BUILTIN_EVEXTSB, - SPE_BUILTIN_EVEXTSH, - SPE_BUILTIN_EVFSABS, - SPE_BUILTIN_EVFSCFSF, - SPE_BUILTIN_EVFSCFSI, - SPE_BUILTIN_EVFSCFUF, - SPE_BUILTIN_EVFSCFUI, - SPE_BUILTIN_EVFSCTSF, - SPE_BUILTIN_EVFSCTSI, - SPE_BUILTIN_EVFSCTSIZ, - SPE_BUILTIN_EVFSCTUF, - SPE_BUILTIN_EVFSCTUI, - SPE_BUILTIN_EVFSCTUIZ, - SPE_BUILTIN_EVFSNABS, - SPE_BUILTIN_EVFSNEG, - SPE_BUILTIN_EVMRA, - SPE_BUILTIN_EVNEG, - SPE_BUILTIN_EVRNDW, - SPE_BUILTIN_EVSUBFSMIAAW, - SPE_BUILTIN_EVSUBFSSIAAW, - SPE_BUILTIN_EVSUBFUMIAAW, - SPE_BUILTIN_EVSUBFUSIAAW, - SPE_BUILTIN_EVADDIW, - SPE_BUILTIN_EVLDD, - SPE_BUILTIN_EVLDH, - SPE_BUILTIN_EVLDW, - SPE_BUILTIN_EVLHHESPLAT, - SPE_BUILTIN_EVLHHOSSPLAT, - SPE_BUILTIN_EVLHHOUSPLAT, - SPE_BUILTIN_EVLWHE, - SPE_BUILTIN_EVLWHOS, - SPE_BUILTIN_EVLWHOU, - SPE_BUILTIN_EVLWHSPLAT, - SPE_BUILTIN_EVLWWSPLAT, - SPE_BUILTIN_EVRLWI, - SPE_BUILTIN_EVSLWI, - SPE_BUILTIN_EVSRWIS, - SPE_BUILTIN_EVSRWIU, - SPE_BUILTIN_EVSTDD, - SPE_BUILTIN_EVSTDH, - SPE_BUILTIN_EVSTDW, - SPE_BUILTIN_EVSTWHE, - SPE_BUILTIN_EVSTWHO, - SPE_BUILTIN_EVSTWWE, - SPE_BUILTIN_EVSTWWO, - SPE_BUILTIN_EVSUBIFW, - - /* Compares. */ - SPE_BUILTIN_EVCMPEQ, - SPE_BUILTIN_EVCMPGTS, - SPE_BUILTIN_EVCMPGTU, - SPE_BUILTIN_EVCMPLTS, - SPE_BUILTIN_EVCMPLTU, - SPE_BUILTIN_EVFSCMPEQ, - SPE_BUILTIN_EVFSCMPGT, - SPE_BUILTIN_EVFSCMPLT, - SPE_BUILTIN_EVFSTSTEQ, - SPE_BUILTIN_EVFSTSTGT, - SPE_BUILTIN_EVFSTSTLT, - - /* EVSEL compares. */ - SPE_BUILTIN_EVSEL_CMPEQ, - SPE_BUILTIN_EVSEL_CMPGTS, - SPE_BUILTIN_EVSEL_CMPGTU, - SPE_BUILTIN_EVSEL_CMPLTS, - SPE_BUILTIN_EVSEL_CMPLTU, - SPE_BUILTIN_EVSEL_FSCMPEQ, - SPE_BUILTIN_EVSEL_FSCMPGT, - SPE_BUILTIN_EVSEL_FSCMPLT, - SPE_BUILTIN_EVSEL_FSTSTEQ, - SPE_BUILTIN_EVSEL_FSTSTGT, - SPE_BUILTIN_EVSEL_FSTSTLT, - - SPE_BUILTIN_EVSPLATFI, - SPE_BUILTIN_EVSPLATI, - SPE_BUILTIN_EVMWHSSMAA, - SPE_BUILTIN_EVMWHSMFAA, - SPE_BUILTIN_EVMWHSMIAA, - SPE_BUILTIN_EVMWHUSIAA, - SPE_BUILTIN_EVMWHUMIAA, - SPE_BUILTIN_EVMWHSSFAN, - SPE_BUILTIN_EVMWHSSIAN, - SPE_BUILTIN_EVMWHSMFAN, - SPE_BUILTIN_EVMWHSMIAN, - SPE_BUILTIN_EVMWHUSIAN, - SPE_BUILTIN_EVMWHUMIAN, - SPE_BUILTIN_EVMWHGSSFAA, - SPE_BUILTIN_EVMWHGSMFAA, - SPE_BUILTIN_EVMWHGSMIAA, - SPE_BUILTIN_EVMWHGUMIAA, - SPE_BUILTIN_EVMWHGSSFAN, - SPE_BUILTIN_EVMWHGSMFAN, - SPE_BUILTIN_EVMWHGSMIAN, - SPE_BUILTIN_EVMWHGUMIAN, - SPE_BUILTIN_MTSPEFSCR, - SPE_BUILTIN_MFSPEFSCR, - SPE_BUILTIN_BRINC, - - /* PAIRED builtins. */ - PAIRED_BUILTIN_DIVV2SF3, - PAIRED_BUILTIN_ABSV2SF2, - PAIRED_BUILTIN_NEGV2SF2, - PAIRED_BUILTIN_SQRTV2SF2, - PAIRED_BUILTIN_ADDV2SF3, - PAIRED_BUILTIN_SUBV2SF3, - PAIRED_BUILTIN_RESV2SF2, - PAIRED_BUILTIN_MULV2SF3, - PAIRED_BUILTIN_MSUB, - PAIRED_BUILTIN_MADD, - PAIRED_BUILTIN_NMSUB, - PAIRED_BUILTIN_NMADD, - PAIRED_BUILTIN_NABSV2SF2, - PAIRED_BUILTIN_SUM0, - PAIRED_BUILTIN_SUM1, - PAIRED_BUILTIN_MULS0, - PAIRED_BUILTIN_MULS1, - PAIRED_BUILTIN_MERGE00, - PAIRED_BUILTIN_MERGE01, - PAIRED_BUILTIN_MERGE10, - PAIRED_BUILTIN_MERGE11, - PAIRED_BUILTIN_MADDS0, - PAIRED_BUILTIN_MADDS1, - PAIRED_BUILTIN_STX, - PAIRED_BUILTIN_LX, - PAIRED_BUILTIN_SELV2SF4, - PAIRED_BUILTIN_CMPU0, - PAIRED_BUILTIN_CMPU1, - - RS6000_BUILTIN_RECIP, - RS6000_BUILTIN_RECIPF, - RS6000_BUILTIN_RSQRTF, - RS6000_BUILTIN_BSWAP_HI, - - /* VSX builtins. */ - VSX_BUILTIN_LXSDX, - VSX_BUILTIN_LXVD2X, - VSX_BUILTIN_LXVDSX, - VSX_BUILTIN_LXVW4X, - VSX_BUILTIN_STXSDX, - VSX_BUILTIN_STXVD2X, - VSX_BUILTIN_STXVW4X, - VSX_BUILTIN_XSABSDP, - VSX_BUILTIN_XSADDDP, - VSX_BUILTIN_XSCMPODP, - VSX_BUILTIN_XSCMPUDP, - VSX_BUILTIN_XSCPSGNDP, - VSX_BUILTIN_XSCVDPSP, - VSX_BUILTIN_XSCVDPSXDS, - VSX_BUILTIN_XSCVDPSXWS, - VSX_BUILTIN_XSCVDPUXDS, - VSX_BUILTIN_XSCVDPUXWS, - VSX_BUILTIN_XSCVSPDP, - VSX_BUILTIN_XSCVSXDDP, - VSX_BUILTIN_XSCVUXDDP, - VSX_BUILTIN_XSDIVDP, - VSX_BUILTIN_XSMADDADP, - VSX_BUILTIN_XSMADDMDP, - VSX_BUILTIN_XSMAXDP, - VSX_BUILTIN_XSMINDP, - VSX_BUILTIN_XSMOVDP, - VSX_BUILTIN_XSMSUBADP, - VSX_BUILTIN_XSMSUBMDP, - VSX_BUILTIN_XSMULDP, - VSX_BUILTIN_XSNABSDP, - VSX_BUILTIN_XSNEGDP, - VSX_BUILTIN_XSNMADDADP, - VSX_BUILTIN_XSNMADDMDP, - VSX_BUILTIN_XSNMSUBADP, - VSX_BUILTIN_XSNMSUBMDP, - VSX_BUILTIN_XSRDPI, - VSX_BUILTIN_XSRDPIC, - VSX_BUILTIN_XSRDPIM, - VSX_BUILTIN_XSRDPIP, - VSX_BUILTIN_XSRDPIZ, - VSX_BUILTIN_XSREDP, - VSX_BUILTIN_XSRSQRTEDP, - VSX_BUILTIN_XSSQRTDP, - VSX_BUILTIN_XSSUBDP, - VSX_BUILTIN_CPSGNDP, - VSX_BUILTIN_CPSGNSP, - VSX_BUILTIN_XSTDIVDP_FE, - VSX_BUILTIN_XSTDIVDP_FG, - VSX_BUILTIN_XSTSQRTDP_FE, - VSX_BUILTIN_XSTSQRTDP_FG, - VSX_BUILTIN_XVABSDP, - VSX_BUILTIN_XVABSSP, - VSX_BUILTIN_XVADDDP, - VSX_BUILTIN_XVADDSP, - VSX_BUILTIN_XVCMPEQDP, - VSX_BUILTIN_XVCMPEQSP, - VSX_BUILTIN_XVCMPGEDP, - VSX_BUILTIN_XVCMPGESP, - VSX_BUILTIN_XVCMPGTDP, - VSX_BUILTIN_XVCMPGTSP, - VSX_BUILTIN_XVCMPEQDP_P, - VSX_BUILTIN_XVCMPEQSP_P, - VSX_BUILTIN_XVCMPGEDP_P, - VSX_BUILTIN_XVCMPGESP_P, - VSX_BUILTIN_XVCMPGTDP_P, - VSX_BUILTIN_XVCMPGTSP_P, - VSX_BUILTIN_XVCPSGNDP, - VSX_BUILTIN_XVCPSGNSP, - VSX_BUILTIN_XVCVDPSP, - VSX_BUILTIN_XVCVDPSXDS, - VSX_BUILTIN_XVCVDPSXWS, - VSX_BUILTIN_XVCVDPUXDS, - VSX_BUILTIN_XVCVDPUXDS_UNS, - VSX_BUILTIN_XVCVDPUXWS, - VSX_BUILTIN_XVCVSPDP, - VSX_BUILTIN_XVCVSPSXDS, - VSX_BUILTIN_XVCVSPSXWS, - VSX_BUILTIN_XVCVSPUXDS, - VSX_BUILTIN_XVCVSPUXWS, - VSX_BUILTIN_XVCVSXDDP, - VSX_BUILTIN_XVCVSXDSP, - VSX_BUILTIN_XVCVSXWDP, - VSX_BUILTIN_XVCVSXWSP, - VSX_BUILTIN_XVCVUXDDP, - VSX_BUILTIN_XVCVUXDDP_UNS, - VSX_BUILTIN_XVCVUXDSP, - VSX_BUILTIN_XVCVUXWDP, - VSX_BUILTIN_XVCVUXWSP, - VSX_BUILTIN_XVDIVDP, - VSX_BUILTIN_XVDIVSP, - VSX_BUILTIN_XVMADDDP, - VSX_BUILTIN_XVMADDSP, - VSX_BUILTIN_XVMAXDP, - VSX_BUILTIN_XVMAXSP, - VSX_BUILTIN_XVMINDP, - VSX_BUILTIN_XVMINSP, - VSX_BUILTIN_XVMSUBDP, - VSX_BUILTIN_XVMSUBSP, - VSX_BUILTIN_XVMULDP, - VSX_BUILTIN_XVMULSP, - VSX_BUILTIN_XVNABSDP, - VSX_BUILTIN_XVNABSSP, - VSX_BUILTIN_XVNEGDP, - VSX_BUILTIN_XVNEGSP, - VSX_BUILTIN_XVNMADDDP, - VSX_BUILTIN_XVNMADDSP, - VSX_BUILTIN_XVNMSUBDP, - VSX_BUILTIN_XVNMSUBSP, - VSX_BUILTIN_XVRDPI, - VSX_BUILTIN_XVRDPIC, - VSX_BUILTIN_XVRDPIM, - VSX_BUILTIN_XVRDPIP, - VSX_BUILTIN_XVRDPIZ, - VSX_BUILTIN_XVREDP, - VSX_BUILTIN_XVRESP, - VSX_BUILTIN_XVRSPI, - VSX_BUILTIN_XVRSPIC, - VSX_BUILTIN_XVRSPIM, - VSX_BUILTIN_XVRSPIP, - VSX_BUILTIN_XVRSPIZ, - VSX_BUILTIN_XVRSQRTEDP, - VSX_BUILTIN_XVRSQRTESP, - VSX_BUILTIN_XVSQRTDP, - VSX_BUILTIN_XVSQRTSP, - VSX_BUILTIN_XVSUBDP, - VSX_BUILTIN_XVSUBSP, - VSX_BUILTIN_XVTDIVDP_FE, - VSX_BUILTIN_XVTDIVDP_FG, - VSX_BUILTIN_XVTDIVSP_FE, - VSX_BUILTIN_XVTDIVSP_FG, - VSX_BUILTIN_XVTSQRTDP_FE, - VSX_BUILTIN_XVTSQRTDP_FG, - VSX_BUILTIN_XVTSQRTSP_FE, - VSX_BUILTIN_XVTSQRTSP_FG, - VSX_BUILTIN_XXSEL_2DI, - VSX_BUILTIN_XXSEL_2DF, - VSX_BUILTIN_XXSEL_4SI, - VSX_BUILTIN_XXSEL_4SF, - VSX_BUILTIN_XXSEL_8HI, - VSX_BUILTIN_XXSEL_16QI, - VSX_BUILTIN_XXSEL_2DI_UNS, - VSX_BUILTIN_XXSEL_4SI_UNS, - VSX_BUILTIN_XXSEL_8HI_UNS, - VSX_BUILTIN_XXSEL_16QI_UNS, - VSX_BUILTIN_VPERM_2DI, - VSX_BUILTIN_VPERM_2DF, - VSX_BUILTIN_VPERM_4SI, - VSX_BUILTIN_VPERM_4SF, - VSX_BUILTIN_VPERM_8HI, - VSX_BUILTIN_VPERM_16QI, - VSX_BUILTIN_VPERM_2DI_UNS, - VSX_BUILTIN_VPERM_4SI_UNS, - VSX_BUILTIN_VPERM_8HI_UNS, - VSX_BUILTIN_VPERM_16QI_UNS, - VSX_BUILTIN_XXPERMDI_2DF, - VSX_BUILTIN_XXPERMDI_2DI, - VSX_BUILTIN_XXPERMDI_4SF, - VSX_BUILTIN_XXPERMDI_4SI, - VSX_BUILTIN_XXPERMDI_8HI, - VSX_BUILTIN_XXPERMDI_16QI, - VSX_BUILTIN_CONCAT_2DF, - VSX_BUILTIN_CONCAT_2DI, - VSX_BUILTIN_SET_2DF, - VSX_BUILTIN_SET_2DI, - VSX_BUILTIN_SPLAT_2DF, - VSX_BUILTIN_SPLAT_2DI, - VSX_BUILTIN_XXMRGHW_4SF, - VSX_BUILTIN_XXMRGHW_4SI, - VSX_BUILTIN_XXMRGLW_4SF, - VSX_BUILTIN_XXMRGLW_4SI, - VSX_BUILTIN_XXSLDWI_16QI, - VSX_BUILTIN_XXSLDWI_8HI, - VSX_BUILTIN_XXSLDWI_4SI, - VSX_BUILTIN_XXSLDWI_4SF, - VSX_BUILTIN_XXSLDWI_2DI, - VSX_BUILTIN_XXSLDWI_2DF, - VSX_BUILTIN_VEC_INIT_V2DF, - VSX_BUILTIN_VEC_INIT_V2DI, - VSX_BUILTIN_VEC_SET_V2DF, - VSX_BUILTIN_VEC_SET_V2DI, - VSX_BUILTIN_VEC_EXT_V2DF, - VSX_BUILTIN_VEC_EXT_V2DI, - - /* VSX overloaded builtins, add the overloaded functions not present in - Altivec. */ - VSX_BUILTIN_VEC_MUL, - VSX_BUILTIN_OVERLOADED_FIRST = VSX_BUILTIN_VEC_MUL, - VSX_BUILTIN_VEC_MSUB, - VSX_BUILTIN_VEC_NMADD, - VSX_BUITLIN_VEC_NMSUB, - VSX_BUILTIN_VEC_DIV, - VSX_BUILTIN_VEC_XXMRGHW, - VSX_BUILTIN_VEC_XXMRGLW, - VSX_BUILTIN_VEC_XXPERMDI, - VSX_BUILTIN_VEC_XXSLDWI, - VSX_BUILTIN_VEC_XXSPLTD, - VSX_BUILTIN_VEC_XXSPLTW, - VSX_BUILTIN_OVERLOADED_LAST = VSX_BUILTIN_VEC_XXSPLTW, - - /* Combined VSX/Altivec builtins. */ - VECTOR_BUILTIN_FLOAT_V4SI_V4SF, - VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF, - VECTOR_BUILTIN_FIX_V4SF_V4SI, - VECTOR_BUILTIN_FIXUNS_V4SF_V4SI, - - /* Power7 builtins, that aren't VSX instructions. */ - POWER7_BUILTIN_BPERMD, +#include "rs6000-builtin.def" RS6000_BUILTIN_COUNT }; +#undef RS6000_BUILTIN +#undef RS6000_BUILTIN_EQUATE + enum rs6000_builtin_type_index { RS6000_BTI_NOT_OPAQUE, diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index 66a367a7b62..773d710fa3f 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -19,6 +19,8 @@ # along with GCC; see the file COPYING3. If not see # <http://www.gnu.org/licenses/>. +TM_H += $(srcdir)/config/rs6000/rs6000-builtin.def + rs6000.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(RTL_H) $(REGS_H) hard-reg-set.h \ real.h insn-config.h conditions.h insn-attr.h flags.h $(RECOG_H) \ @@ -56,6 +58,7 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rios1.md \ $(srcdir)/config/rs6000/power7.md \ $(srcdir)/config/rs6000/cell.md \ $(srcdir)/config/rs6000/xfpu.md \ + $(srcdir)/config/rs6000/a2.md \ $(srcdir)/config/rs6000/predicates.md \ $(srcdir)/config/rs6000/constraints.md \ $(srcdir)/config/rs6000/darwin.md \ diff --git a/gcc/config/s390/2097.md b/gcc/config/s390/2097.md index eb7240effd4..56893596a74 100644 --- a/gcc/config/s390/2097.md +++ b/gcc/config/s390/2097.md @@ -57,7 +57,8 @@ z10_int_fr_A3" "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \ z10_int_super, z10_int_super_E1, \ - z10_lr, z10_store_super") + z10_lr, z10_store_super" + " ! s390_agen_dep_p") ; Forwarding from z10_super to frz10_ and z10_rec. @@ -68,7 +69,8 @@ z10_store_super" "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ - z10_other_fr_E1, z10_store_rec") + z10_other_fr_E1, z10_store_rec" + " ! s390_agen_dep_p") ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr. @@ -84,7 +86,8 @@ z10_int_fr_A3" "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ - z10_other_fr_E1, z10_store_rec") + z10_other_fr_E1, z10_store_rec" + " ! s390_agen_dep_p") ; @@ -205,15 +208,12 @@ (and (eq_attr "type" "lr") (eq_attr "z10prop" "z10_fr"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") (define_insn_reservation "z10_lr_fr_E1" 6 (and (eq_attr "cpu" "z10") (and (eq_attr "type" "lr") (eq_attr "z10prop" "z10_fr_E1"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") - (define_insn_reservation "z10_la" 6 (and (eq_attr "cpu" "z10") @@ -227,14 +227,12 @@ (and (eq_attr "type" "la") (eq_attr "z10prop" "z10_fwd"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") (define_insn_reservation "z10_la_fwd_A1" 6 (and (eq_attr "cpu" "z10") (and (eq_attr "type" "la") (eq_attr "z10prop" "z10_fwd_A1"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") ; larl-type instructions @@ -666,13 +664,14 @@ ; Address-related bypasses ; -; Here is the cycle diagram for Address-related bypasses: +; Here is the cycle diagram for address-related bypasses: ; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ... -; ^ ^ ^ ^ ^ -; | | | | E1-type bypasses provide the new addr AFTER this cycle -; | | | A3-type bypasses provide the new addr AFTER this cycle -; | | A1-type bypasses provide the new addr AFTER this cycle -; | AGI resolution, actual USE of address is DURING this cycle +; ^ ^ ^ ^ ^ ^ +; | | | | | without bypass, its available AFTER this cycle +; | | | | E1-type bypasses provide the new value AFTER this cycle +; | | | A3-type bypasses provide the new value AFTER this cycle +; | | A1-type bypasses provide the new value AFTER this cycle +; | AGI resolution, actual USE of new value is DURING this cycle ; AGI detection (define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \ @@ -682,7 +681,6 @@ z10_cs, z10_stm, z10_other" "s390_agen_dep_p") - (define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \ z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3" "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ @@ -699,6 +697,12 @@ z10_cs, z10_stm, z10_other" "s390_agen_dep_p") +(define_bypass 9 "z10_int_super, z10_int_fwd, z10_int_fr" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + ; diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index e439b01709f..a4334819203 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -9003,6 +9003,7 @@ s390_encode_section_info (tree decl, rtx rtl, int first) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0)) && (MEM_ALIGN (rtl) == 0 + || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl)))) SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED; } @@ -9863,9 +9864,12 @@ s390_z10_optimize_cmp (rtx insn) if (!REG_P (*op0) || !REG_P (*op1)) return false; + if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT) + return false; + /* Swap the COMPARE arguments and its mask if there is a conflicting access in the previous insn. */ - prev_insn = PREV_INSN (insn); + prev_insn = prev_active_insn (insn); if (prev_insn != NULL_RTX && INSN_P (prev_insn) && reg_referenced_p (*op1, PATTERN (prev_insn))) s390_swap_cmp (cond, op0, op1, insn); @@ -9876,7 +9880,7 @@ s390_z10_optimize_cmp (rtx insn) the operands, or if swapping them would cause a conflict with the previous insn, issue a NOP after the COMPARE in order to separate the two instuctions. */ - next_insn = NEXT_INSN (insn); + next_insn = next_active_insn (insn); if (next_insn != NULL_RTX && INSN_P (next_insn) && s390_non_addr_reg_read_p (*op1, next_insn)) { diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 90ed18b0f0d..8f4a71feb3f 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -220,7 +220,7 @@ ;; reg: Instruction does not use the agen unit (define_attr "atype" "agen,reg" - (if_then_else (eq_attr "op_type" "E,RR,RI,RRE") + (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") (const_string "reg") (const_string "agen"))) diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 679cf11e83e..26bceea670d 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -222,7 +222,9 @@ static bool sh_optimize_target_register_callee_saved (bool); static bool sh_ms_bitfield_layout_p (const_tree); static void sh_init_builtins (void); +static tree sh_builtin_decl (unsigned, bool); static void sh_media_init_builtins (void); +static tree sh_media_builtin_decl (unsigned, bool); static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int); static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); static void sh_file_start (void); @@ -416,6 +418,8 @@ static const struct attribute_spec sh_attribute_table[] = #undef TARGET_INIT_BUILTINS #define TARGET_INIT_BUILTINS sh_init_builtins +#undef TARGET_BUILTIN_DECL +#define TARGET_BUILTIN_DECL sh_builtin_decl #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN sh_expand_builtin @@ -9427,6 +9431,7 @@ nonpic_symbol_mentioned_p (rtx x) || XINT (x, 1) == UNSPEC_GOTPLT || XINT (x, 1) == UNSPEC_GOTTPOFF || XINT (x, 1) == UNSPEC_DTPOFF + || XINT (x, 1) == UNSPEC_TPOFF || XINT (x, 1) == UNSPEC_PLT || XINT (x, 1) == UNSPEC_SYMOFF || XINT (x, 1) == UNSPEC_PCREL_SYMOFF)) @@ -10520,6 +10525,7 @@ struct builtin_description const enum insn_code icode; const char *const name; int signature; + tree fndecl; }; /* describe number and signedness of arguments; arg[0] == result @@ -10586,99 +10592,99 @@ static const char signature_args[][4] = /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */ /* mshards_q: returns signed short. */ /* nsb: takes long long arg, returns unsigned char. */ -static const struct builtin_description bdesc[] = -{ - { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 }, - { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 }, - { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 }, - { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 }, - { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 }, - { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 }, - { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 }, - { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV }, - { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 }, - { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 }, - { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 }, - { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 }, - { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 }, - { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 }, - { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU }, - { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 }, - { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI }, - { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI }, - { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 }, - { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 }, - { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 }, - { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 }, - { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 }, - { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 }, - { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 }, - { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI }, - { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI }, - { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, }, - { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 }, - { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 }, - { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 }, - { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 }, - { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI }, - { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI }, - { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU }, - { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI }, - { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU }, - { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI }, - { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI }, - { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI }, - { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI }, - { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS }, - { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 }, - { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 }, - { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 }, - { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 }, - { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 }, - { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 }, - { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI }, - { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI }, - { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI }, - { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI }, - { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 }, - { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 }, - { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 }, - { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 }, - { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 }, - { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF }, - { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF }, - { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 }, - { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 }, - { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 }, - { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 }, - { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 }, - { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 }, - { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L }, - { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q }, - { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L }, - { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q }, - { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L }, - { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q }, - { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L }, - { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q }, - { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 }, - { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 }, - { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 }, - { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 }, - { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 }, - { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 }, - { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 }, - { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 }, - { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU }, - { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 }, - { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV }, +static struct builtin_description bdesc[] = +{ + { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 }, + { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 }, + { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 }, + { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 }, + { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 }, + { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 }, + { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 }, + { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 }, + { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 }, + { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 }, + { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 }, + { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 }, + { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 }, + { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 }, + { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 }, + { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 }, + { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 }, + { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 }, + { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 }, + { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 }, + { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 }, + { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 }, + { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 }, + { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 }, + { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 }, + { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 }, + { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 }, + { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 }, + { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 }, + { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 }, + { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3, 0 }, + { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 }, + { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 }, + { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 }, + { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 }, + { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 }, + { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 }, + { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 }, + { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 }, + { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 }, + { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 }, + { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 }, + { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 }, + { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 }, + { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 }, + { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 }, + { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 }, + { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 }, + { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 }, + { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 }, + { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 }, + { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 }, + { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 }, }; static void sh_media_init_builtins (void) { tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES]; - const struct builtin_description *d; + struct builtin_description *d; memset (shared, 0, sizeof shared); for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++) @@ -10724,11 +10730,23 @@ sh_media_init_builtins (void) if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES) shared[signature] = type; } - add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD, - NULL, NULL_TREE); + d->fndecl = + add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD, + NULL, NULL_TREE); } } +/* Returns the shmedia builtin decl for CODE. */ + +static tree +sh_media_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) +{ + if (code >= ARRAY_SIZE (bdesc)) + return error_mark_node; + + return bdesc[code].fndecl; +} + /* Implements target hook vector_mode_supported_p. */ bool sh_vector_mode_supported_p (enum machine_mode mode) @@ -10767,6 +10785,17 @@ sh_init_builtins (void) sh_media_init_builtins (); } +/* Returns the sh builtin decl for CODE. */ + +static tree +sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) +{ + if (TARGET_SHMEDIA) + return sh_media_builtin_decl (code, initialize_p); + + return error_mark_node; +} + /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index a05e1d804d7..ed5d6c59345 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -2368,7 +2368,7 @@ get_branch_target (rtx branch) return 0; /* ASM GOTOs. */ - if (GET_CODE (PATTERN (branch)) == ASM_OPERANDS) + if (extract_asm_operands (PATTERN (branch)) != NULL) return NULL; set = single_set (branch); |