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-rw-r--r--gcc/config/arm/arm_cmse.h7
-rw-r--r--gcc/config/i386/sse.md9
-rw-r--r--gcc/config/riscv/t-rtems25
-rw-r--r--gcc/config/rs6000/rs6000-c.c9
-rw-r--r--gcc/config/rs6000/rs6000.c26
-rw-r--r--gcc/config/rs6000/rs6000.h6
-rw-r--r--gcc/config/rs6000/rs6000.md4
-rw-r--r--gcc/config/rtems.h4
-rw-r--r--gcc/config/s390/s390-builtin-types.def1
-rw-r--r--gcc/config/s390/s390-builtins.def2
-rw-r--r--gcc/config/xtensa/xtensa.md46
11 files changed, 114 insertions, 25 deletions
diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h
index 8fde2736a2a..427647fb981 100644
--- a/gcc/config/arm/arm_cmse.h
+++ b/gcc/config/arm/arm_cmse.h
@@ -35,7 +35,6 @@ extern "C" {
#if __ARM_FEATURE_CMSE & 1
#include <stddef.h>
-#include <stdint.h>
#ifdef __ARM_BIG_ENDIAN
@@ -174,9 +173,9 @@ cmse_nonsecure_caller (void)
#define CMSE_MPU_NONSECURE 16
#define CMSE_NONSECURE 18
-#define cmse_nsfptr_create(p) ((typeof ((p))) ((intptr_t) (p) & ~1))
+#define cmse_nsfptr_create(p) ((__typeof__ ((p))) ((__INTPTR_TYPE__) (p) & ~1))
-#define cmse_is_nsfptr(p) (!((intptr_t) (p) & 1))
+#define cmse_is_nsfptr(p) (!((__INTPTR_TYPE__) (p) & 1))
#endif /* __ARM_FEATURE_CMSE & 2 */
@@ -188,7 +187,7 @@ __extension__ void *
cmse_check_address_range (void *, size_t, int);
#define cmse_check_pointed_object(p, f) \
- ((typeof ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f)))
+ ((__typeof__ ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f)))
#endif /* __ARM_FEATURE_CMSE & 1 */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1cd6efb300e..0ed1ac053c5 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1134,11 +1134,8 @@
operands[2]));
}
else if (memory_operand (operands[1], DImode))
- {
- rtx tmp = gen_reg_rtx (V2DImode);
- emit_insn (gen_vec_concatv2di (tmp, operands[1], const0_rtx));
- emit_move_insn (operands[0], gen_lowpart (V4SImode, tmp));
- }
+ emit_insn (gen_vec_concatv2di (gen_lowpart (V2DImode, operands[0]),
+ operands[1], const0_rtx));
else
gcc_unreachable ();
DONE;
@@ -4398,7 +4395,7 @@
(match_operand:VF_128 1 "register_operand" "v")
(const_int 1)))]
"TARGET_AVX512F && TARGET_64BIT"
- "vcvtusi2<ssescalarmodesuffix>\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
+ "vcvtusi2<ssescalarmodesuffix>{q}\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
diff --git a/gcc/config/riscv/t-rtems b/gcc/config/riscv/t-rtems
new file mode 100644
index 00000000000..41f5927fc87
--- /dev/null
+++ b/gcc/config/riscv/t-rtems
@@ -0,0 +1,25 @@
+MULTILIB_OPTIONS =
+MULTILIB_DIRNAMES =
+
+MULTILIB_OPTIONS += march=rv32i/march=rv32im/march=rv32imafd/march=rv32iac/march=rv32imac/march=rv32imafc/march=rv64imafd/march=rv64imac/march=rv64imafdc
+MULTILIB_DIRNAMES += rv32i rv32im rv32imafd rv32iac rv32imac rv32imafc rv64imafd rv64imac rv64imafdc
+
+MULTILIB_OPTIONS += mabi=ilp32/mabi=ilp32f/mabi=ilp32d/mabi=lp64/mabi=lp64d
+MULTILIB_DIRNAMES += ilp32 ilp32f ilp32d lp64 lp64d
+
+MULTILIB_OPTIONS += mcmodel=medany
+MULTILIB_DIRNAMES += medany
+
+MULTILIB_REQUIRED =
+MULTILIB_REQUIRED += march=rv32i/mabi=ilp32
+MULTILIB_REQUIRED += march=rv32im/mabi=ilp32
+MULTILIB_REQUIRED += march=rv32imafd/mabi=ilp32d
+MULTILIB_REQUIRED += march=rv32iac/mabi=ilp32
+MULTILIB_REQUIRED += march=rv32imac/mabi=ilp32
+MULTILIB_REQUIRED += march=rv32imafc/mabi=ilp32f
+MULTILIB_REQUIRED += march=rv64imafd/mabi=lp64d
+MULTILIB_REQUIRED += march=rv64imafd/mabi=lp64d/mcmodel=medany
+MULTILIB_REQUIRED += march=rv64imac/mabi=lp64
+MULTILIB_REQUIRED += march=rv64imac/mabi=lp64/mcmodel=medany
+MULTILIB_REQUIRED += march=rv64imafdc/mabi=lp64d
+MULTILIB_REQUIRED += march=rv64imafdc/mabi=lp64d/mcmodel=medany
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index c6fd52439eb..24904d1bd74 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -6075,6 +6075,15 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
stmt = build_indirect_ref (loc, stmt, RO_NULL);
+ /* PR83660: We mark this as having side effects so that
+ downstream in fold_build_cleanup_point_expr () it will get a
+ CLEANUP_POINT_EXPR. If it does not we can run into an ICE
+ later in gimplify_cleanup_point_expr (). Potentially this
+ causes missed optimization because the actually is no side
+ effect. */
+ if (c_dialect_cxx ())
+ TREE_SIDE_EFFECTS (stmt) = 1;
+
return stmt;
}
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index edddff7aeca..01ae6ad8787 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1372,6 +1372,7 @@ static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
int, int, int *);
static bool rs6000_mode_dependent_address (const_rtx);
static bool rs6000_debug_mode_dependent_address (const_rtx);
+static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
static enum reg_class rs6000_secondary_reload_class (enum reg_class,
machine_mode, rtx);
static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
@@ -8564,10 +8565,15 @@ mem_operand_gpr (rtx op, machine_mode mode)
int extra;
rtx addr = XEXP (op, 0);
- /* Don't allow altivec type addresses like (mem (and (plus ...))).
- See PR target/84279. */
+ /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
+ if (TARGET_UPDATE
+ && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
+ && mode_supports_pre_incdec_p (mode)
+ && legitimate_indirect_address_p (XEXP (addr, 0), false))
+ return true;
- if (GET_CODE (addr) == AND)
+ /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
+ if (!rs6000_offsettable_memref_p (op, mode, false))
return false;
op = address_offset (addr);
@@ -10340,7 +10346,7 @@ rs6000_find_base_term (rtx op)
in 32-bit mode, that the recog predicate rejects. */
static bool
-rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
+rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
{
bool worst_case;
@@ -10348,7 +10354,7 @@ rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
return false;
/* First mimic offsettable_memref_p. */
- if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
+ if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
return true;
/* offsettable_address_p invokes rs6000_mode_dependent_address, but
@@ -10362,7 +10368,7 @@ rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
|| GET_MODE_SIZE (reg_mode) == 4);
return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
- true, worst_case);
+ strict, worst_case);
}
/* Determine the reassociation width to be used in reassociate_bb.
@@ -23281,7 +23287,7 @@ rs6000_output_move_128bit (rtx operands[])
}
else if (TARGET_ALTIVEC && src_vmx_p
- && altivec_indexed_or_indirect_operand (src, mode))
+ && altivec_indexed_or_indirect_operand (dest, mode))
return "stvx %1,%y0";
else if (TARGET_VSX && src_vsx_p)
@@ -26559,7 +26565,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_add3_insn (breg, breg, delta_rtx));
src = replace_equiv_address (src, breg);
}
- else if (! rs6000_offsettable_memref_p (src, reg_mode))
+ else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
{
if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
{
@@ -26626,7 +26632,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_add3_insn (breg, breg, delta_rtx));
dst = replace_equiv_address (dst, breg);
}
- else if (!rs6000_offsettable_memref_p (dst, reg_mode)
+ else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
&& GET_CODE (XEXP (dst, 0)) != LO_SUM)
{
if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
@@ -26665,7 +26671,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
}
}
else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
- gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
+ gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
}
for (i = 0; i < nregs; i++)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 76c44ef31b3..ba234fda718 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -110,7 +110,8 @@
/* Common ASM definitions used by ASM_SPEC among the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
- you make changes here, make them also there. */
+ you make changes here, make them also there. PR63177: Do not pass -mpower8
+ to the assembler if -mpower9-vector was also used. */
#define ASM_CPU_SPEC \
"%{!mcpu*: \
%{mpowerpc64*: -mppc64} \
@@ -124,7 +125,7 @@
%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
%{mcpu=power7: %(asm_cpu_power7)} \
-%{mcpu=power8: %(asm_cpu_power8)} \
+%{mcpu=power8: %{!mpower9-vector: %(asm_cpu_power8)}} \
%{mcpu=power9: %(asm_cpu_power9)} \
%{mcpu=a2: -ma2} \
%{mcpu=powerpc: -mppc} \
@@ -173,6 +174,7 @@
%{maltivec: -maltivec} \
%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
+%{mpower9-vector: %{!mcpu*|mcpu=power8: %(asm_cpu_power9)}} \
-many"
#define CPP_DEFAULT_SPEC ""
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 40eda587137..ca7c04e275a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8640,14 +8640,14 @@
;; FPR->GPR GPR->FPR VSX->GPR GPR->VSX
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=Y, r, r, r, r, r,
+ "=YZ, r, r, r, r, r,
^m, ^d, ^d, ^wY, $Z, $wb,
$wv, ^wi, *wo, *wo, *wv, *wi,
*wi, *wv, *wv, r, *h, *h,
?*r, ?*wg, ?*r, ?*wj")
(match_operand:DI 1 "input_operand"
- "r, Y, r, I, L, nF,
+ "r, YZ, r, I, L, nF,
d, m, d, wb, wv, wY,
Z, wi, Oj, wM, OjwM, Oj,
wM, wS, wB, *h, r, 0,
diff --git a/gcc/config/rtems.h b/gcc/config/rtems.h
index 439199d4cbb..35026efa2c7 100644
--- a/gcc/config/rtems.h
+++ b/gcc/config/rtems.h
@@ -48,3 +48,7 @@
-latomic -lc -lgcc --end-group %{!qnolinkcmds: -T linkcmds%s}}}"
#define TARGET_POSIX_IO
+
+/* Prefer int for int32_t (see stdint-newlib.h). */
+#undef STDINT_LONG32
+#define STDINT_LONG32 (INT_TYPE_SIZE != 32 && LONG_TYPE_SIZE == 32)
diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def
index b7f33030eb9..915b050b2fb 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -124,6 +124,7 @@ DEF_OPAQUE_VECTOR_TYPE (BT_OUV4SI, BT_UINT, 4)
DEF_OPAQUE_VECTOR_TYPE (BT_BV4SI, BT_BINT, 4)
DEF_FN_TYPE_0 (BT_FN_INT, BT_INT)
DEF_FN_TYPE_0 (BT_FN_UINT, BT_UINT)
+DEF_FN_TYPE_0 (BT_FN_VOID, BT_VOID)
DEF_FN_TYPE_1 (BT_FN_INT_INT, BT_INT, BT_INT)
DEF_FN_TYPE_1 (BT_FN_INT_VOIDPTR, BT_INT, BT_VOIDPTR)
DEF_FN_TYPE_1 (BT_FN_OV4SI_INT, BT_OV4SI, BT_INT)
diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def
index 9046cb08f94..c2f278dc9c3 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -294,7 +294,7 @@
flags: Flags applying to all its variants should be mentioned in the OB_DEF line instead. */
-B_DEF (tbeginc, tbeginc, 0, B_HTM, 0, BT_FN_INT)
+B_DEF (tbeginc, tbeginc, 0, B_HTM, 0, BT_FN_VOID)
B_DEF (tbegin, tbegin, returns_twice_attr, B_HTM, 0, BT_FN_INT_VOIDPTR)
B_DEF (tbegin_nofloat, tbegin_nofloat, returns_twice_attr, B_HTM, 0, BT_FN_INT_VOIDPTR)
B_DEF (tbegin_retry, tbegin_retry, returns_twice_attr, B_HTM, 0, BT_FN_INT_VOIDPTR_INT)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index d5596e25d82..0eba10b742c 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -38,6 +38,7 @@
(UNSPEC_MEMW 11)
(UNSPEC_LSETUP_START 12)
(UNSPEC_LSETUP_END 13)
+ (UNSPEC_FRAME_BLOCKAGE 14)
(UNSPECV_SET_FP 1)
(UNSPECV_ENTRY 2)
@@ -1676,6 +1677,32 @@
;; Miscellaneous instructions.
+;; In windowed ABI stack pointer adjustment must happen before any access
+;; to the space allocated on stack is allowed, otherwise register spill
+;; area may be clobbered. That's what frame blockage is supposed to enforce.
+
+(define_expand "allocate_stack"
+ [(set (match_operand 0 "nonimmed_operand")
+ (minus (reg A1_REG) (match_operand 1 "add_operand")))
+ (set (reg A1_REG)
+ (minus (reg A1_REG) (match_dup 1)))]
+ "TARGET_WINDOWED_ABI"
+{
+ if (CONST_INT_P (operands[1]))
+ {
+ rtx neg_op0 = GEN_INT (-INTVAL (operands[1]));
+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
+ }
+ else
+ {
+ emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
+ operands[1]));
+ }
+ emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+ emit_insn (gen_frame_blockage ());
+ DONE;
+})
+
(define_expand "prologue"
[(const_int 0)]
""
@@ -1767,6 +1794,25 @@
[(set_attr "length" "0")
(set_attr "type" "nop")])
+;; Do not schedule instructions accessing memory before this point.
+
+(define_expand "frame_blockage"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 1)] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+ operands[1] = stack_pointer_rtx;
+})
+
+(define_insn "*frame_blockage"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_operand:SI 1 "" "")] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]
""
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-08 03:00:55 +0000