diff options
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 41 |
1 files changed, 33 insertions, 8 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 36b820a1bb3..2779580daf9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -788,8 +788,9 @@ Objective-C and Objective-C++ Dialects}. -minterlink-mips16 -mno-interlink-mips16 @gol -mabi=@var{abi} -mabicalls -mno-abicalls @gol -mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol --mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol +-mgp32 -mgp64 -mfp32 -mfpxx -mfp64 -mhard-float -msoft-float @gol -mno-float -msingle-float -mdouble-float @gol +-modd-spreg -mno-odd-spreg @gol -mabs=@var{mode} -mnan=@var{encoding} @gol -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol -mmcu -mmno-mcu @gol @@ -13041,13 +13042,11 @@ off by default. @item -masm-syntax-unified @opindex masm-syntax-unified -Assume the Thumb1 inline assembly code are using unified syntax. -The default is currently off, which means divided syntax is assumed. +Assume inline assembler is using unified asm syntax. The default is +currently off which implies divided syntax. Currently this option is +available only for Thumb1 and has no effect on ARM state and Thumb2. However, this may change in future releases of GCC. Divided syntax -should be considered deprecated. This option has no effect when -generating Thumb2 code. Thumb2 assembly code always uses unified syntax. -This option has no effect for ARM state assembly code which will still -uses divided syntax. +should be considered deprecated. @item -mrestrict-it @opindex mrestrict-it @@ -17748,7 +17747,20 @@ same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in @samp{$f0} only, not a @samp{$f0}/@samp{$f1} pair. The set of call-saved registers also -remains the same, but all 64 bits are saved. +remains the same in that the even-numbered double-precision registers +are saved. + +Two additional variants of the o32 ABI are supported to enable +a transition from 32-bit to 64-bit registers. These are FPXX +(@option{-mfpxx}) and FP64A (@option{-mfp64} @option{-mno-odd-spreg}). +The FPXX extension mandates that all code must execute correctly +when run using 32-bit or 64-bit registers. The code can be interlinked +with either FP32 or FP64, but not both. +The FP64A extension is similar to the FP64 extension but forbids the +use of odd-numbered single-precision registers. This can be used +in conjunction with the @code{FRE} mode of FPUs in MIPS32R5 +processors and allows both FP32 and FP64A code to interlink and +run in the same process without changing FPU modes. @item -mabicalls @itemx -mno-abicalls @@ -17837,6 +17849,10 @@ Assume that floating-point registers are 32 bits wide. @opindex mfp64 Assume that floating-point registers are 64 bits wide. +@item -mfpxx +@opindex mfpxx +Do not assume the width of floating-point registers. + @item -mhard-float @opindex mhard-float Use floating-point coprocessor instructions. @@ -17868,6 +17884,15 @@ operations. Assume that the floating-point coprocessor supports double-precision operations. This is the default. +@item -modd-spreg +@itemx -mno-odd-spreg +@opindex modd-spreg +@opindex mno-odd-spreg +Enable the use of odd-numbered single-precision floating-point registers +for the o32 ABI. This is the default for processors that are known to +support these registers. When using the o32 FPXX ABI, @code{-mno-odd-spreg} +is set by default. + @item -mabs=2008 @itemx -mabs=legacy @opindex mabs=2008 |