diff options
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/extend.texi | 147 | ||||
| -rw-r--r-- | gcc/doc/generic.texi | 17 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 152 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 21 | ||||
| -rw-r--r-- | gcc/doc/tm.texi | 9 | ||||
| -rw-r--r-- | gcc/doc/tm.texi.in | 2 |
6 files changed, 224 insertions, 124 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index b6244a09d41..b253cccfa62 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -2984,6 +2984,19 @@ asm (""); (@pxref{Extended Asm}) in the called function, to serve as a special side-effect. +@item noipa +@cindex @code{noipa} function attribute +Disable interprocedural optimizations between the function with this +attribute and its callers, as if the body of the function is not available +when optimizing callers and the callers are unavailable when optimizing +the body. This attribute implies @code{noinline}, @code{noclone} and +@code{no_icf} attributes. However, this attribute is not equivalent +to a combination of other attributes, because its purpose is to suppress +existing and future optimizations employing interprocedural analysis, +including those that do not have an attribute suitable for disabling +them individually. This attribute is supported mainly for the purpose +of testing the compiler. + @item nonnull (@var{arg-index}, @dots{}) @cindex @code{nonnull} function attribute @cindex functions with non-null pointer arguments @@ -3105,6 +3118,27 @@ that affect more than one function. This attribute should be used for debugging purposes only. It is not suitable in production code. +@item patchable_function_entry +@cindex @code{patchable_function_entry} function attribute +@cindex extra NOP instructions at the function entry point +In case the target's text segment can be made writable at run time by +any means, padding the function entry with a number of NOPs can be +used to provide a universal tool for instrumentation. + +The @code{patchable_function_entry} function attribute can be used to +change the number of NOPs to any desired value. The two-value syntax +is the same as for the command-line switch +@option{-fpatchable-function-entry=N,M}, generating @var{N} NOPs, with +the function entry point before the @var{M}th NOP instruction. +@var{M} defaults to 0 if omitted e.g. function entry point is before +the first NOP. + +If patchable function entries are enabled globally using the command-line +option @option{-fpatchable-function-entry=N,M}, then you must disable +instrumentation on all functions that are part of the instrumentation +framework with the attribute @code{patchable_function_entry (0)} +to prevent recursion. + @item pure @cindex @code{pure} function attribute @cindex functions that have no side effects @@ -5336,6 +5370,17 @@ this function attribute to make GCC generate the ``hot-patching'' function prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2 and newer. +@item naked +@cindex @code{naked} function attribute, x86 +This attribute allows the compiler to construct the +requisite function declaration, while allowing the body of the +function to be assembly code. The specified function will not have +prologue/epilogue sequences generated by the compiler. Only basic +@code{asm} statements can safely be included in naked functions +(@pxref{Basic Asm}). While using extended @code{asm} or a mixture of +basic @code{asm} and C code may appear to work, they cannot be +depended upon to work reliably and are not supported. + @item regparm (@var{number}) @cindex @code{regparm} function attribute, x86 @cindex functions that are passed arguments in registers on x86-32 @@ -12748,54 +12793,37 @@ or if not a specific built-in is implemented or not. For example, if @code{__builtin_avr_nop} is available the macro @code{__BUILTIN_AVR_NOP} is defined to @code{1} and undefined otherwise. -The following built-in functions map to the respective machine +@table @code + +@item void __builtin_avr_nop (void) +@itemx void __builtin_avr_sei (void) +@itemx void __builtin_avr_cli (void) +@itemx void __builtin_avr_sleep (void) +@itemx void __builtin_avr_wdr (void) +@itemx unsigned char __builtin_avr_swap (unsigned char) +@itemx unsigned int __builtin_avr_fmul (unsigned char, unsigned char) +@itemx int __builtin_avr_fmuls (char, char) +@itemx int __builtin_avr_fmulsu (char, unsigned char) +These built-in functions map to the respective machine instruction, i.e.@: @code{nop}, @code{sei}, @code{cli}, @code{sleep}, @code{wdr}, @code{swap}, @code{fmul}, @code{fmuls} resp. @code{fmulsu}. The three @code{fmul*} built-ins are implemented as library call if no hardware multiplier is available. -@smallexample -void __builtin_avr_nop (void) -void __builtin_avr_sei (void) -void __builtin_avr_cli (void) -void __builtin_avr_sleep (void) -void __builtin_avr_wdr (void) -unsigned char __builtin_avr_swap (unsigned char) -unsigned int __builtin_avr_fmul (unsigned char, unsigned char) -int __builtin_avr_fmuls (char, char) -int __builtin_avr_fmulsu (char, unsigned char) -@end smallexample - -In order to delay execution for a specific number of cycles, GCC -implements -@smallexample -void __builtin_avr_delay_cycles (unsigned long ticks) -@end smallexample - -@noindent -@code{ticks} is the number of ticks to delay execution. Note that this +@item void __builtin_avr_delay_cycles (unsigned long ticks) +Delay execution for @var{ticks} cycles. Note that this built-in does not take into account the effect of interrupts that -might increase delay time. @code{ticks} must be a compile-time +might increase delay time. @var{ticks} must be a compile-time integer constant; delays with a variable number of cycles are not supported. -@smallexample -char __builtin_avr_flash_segment (const __memx void*) -@end smallexample - -@noindent +@item char __builtin_avr_flash_segment (const __memx void*) This built-in takes a byte address to the 24-bit @ref{AVR Named Address Spaces,address space} @code{__memx} and returns the number of the flash segment (the 64 KiB chunk) where the address points to. Counting starts at @code{0}. If the address does not point to flash memory, return @code{-1}. -@smallexample -unsigned char __builtin_avr_insert_bits (unsigned long map, - unsigned char bits, - unsigned char val) -@end smallexample - -@noindent +@item uint8_t __builtin_avr_insert_bits (uint32_t map, uint8_t bits, uint8_t val) Insert bits from @var{bits} into @var{val} and return the resulting value. The nibbles of @var{map} determine how the insertion is performed: Let @var{X} be the @var{n}-th nibble of @var{map} @@ -12840,13 +12868,29 @@ __builtin_avr_insert_bits (0xffff3210, bits, val) __builtin_avr_insert_bits (0x01234567, bits, 0) @end smallexample -@smallexample -void __builtin_avr_nops (unsigned count) -@end smallexample +@item void __builtin_avr_nops (unsigned count) +Insert @var{count} @code{NOP} instructions. +The number of instructions must be a compile-time integer constant. + +@end table @noindent -Insert @code{count} @code{NOP} instructions. -The number of instructions must be a compile-time integer constant. +There are many more AVR-specific built-in functions that are used to +implement the ISO/IEC TR 18037 ``Embedded C'' fixed-point functions of +section 7.18a.6. You don't need to use these built-ins directly. +Instead, use the declarations as supplied by the @code{stdfix.h} header +with GNU-C99: + +@smallexample +#include <stdfix.h> + +// Re-interpret the bit representation of unsigned 16-bit +// integer @var{uval} as Q-format 0.16 value. +unsigned fract get_bits (uint_ur_t uval) +@{ + return urbits (uval); +@} +@end smallexample @node Blackfin Built-in Functions @subsection Blackfin Built-in Functions @@ -15433,6 +15477,15 @@ vector bool short vec_cmpnez (vector unsigned short arg1, vector unsigned short vector bool int vec_cmpnez (vector signed int arg1, vector signed int arg2); vector bool int vec_cmpnez (vector unsigned int, vector unsigned int); +vector signed char vec_cnttz (vector signed char); +vector unsigned char vec_cnttz (vector unsigned char); +vector signed short vec_cnttz (vector signed short); +vector unsigned short vec_cnttz (vector unsigned short); +vector signed int vec_cnttz (vector signed int); +vector unsigned int vec_cnttz (vector unsigned int); +vector signed long long vec_cnttz (vector signed long long); +vector unsigned long long vec_cnttz (vector unsigned long long); + signed int vec_cntlz_lsbb (vector signed char); signed int vec_cntlz_lsbb (vector unsigned char); @@ -15441,6 +15494,19 @@ signed int vec_cnttz_lsbb (vector unsigned char); vector unsigned short vec_pack_to_short_fp32 (vector float, vector float); +vector signed char vec_xl_be (signed long long, signed char *); +vector unsigned char vec_xl_be (signed long long, unsigned char *); +vector signed int vec_xl_be (signed long long, signed int *); +vector unsigned int vec_xl_be (signed long long, unsigned int *); +vector signed __int128 vec_xl_be (signed long long, signed __int128 *); +vector unsigned __int128 vec_xl_be (signed long long, unsigned __int128 *); +vector signed long long vec_xl_be (signed long long, signed long long *); +vector unsigned long long vec_xl_be (signed long long, unsigned long long *); +vector signed short vec_xl_be (signed long long, signed short *); +vector unsigned short vec_xl_be (signed long long, unsigned short *); +vector double vec_xl_be (signed long long, double *); +vector float vec_xl_be (signed long long, float *); + vector signed char vec_xl_len (signed char *addr, size_t len); vector unsigned char vec_xl_len (unsigned char *addr, size_t len); vector signed int vec_xl_len (signed int *addr, size_t len); @@ -18307,6 +18373,9 @@ vector bool short vec_cmpne (vector bool short, vector bool short); vector bool int vec_cmpne (vector bool int, vector bool int); vector bool long long vec_cmpne (vector bool long long, vector bool long long); +vector float vec_extract_fp32_from_shorth (vector unsigned short); +vector float vec_extract_fp32_from_shortl (vector unsigned short); + vector long long vec_vctz (vector long long); vector unsigned long long vec_vctz (vector unsigned long long); vector int vec_vctz (vector int); diff --git a/gcc/doc/generic.texi b/gcc/doc/generic.texi index 858521688b4..874d46440f4 100644 --- a/gcc/doc/generic.texi +++ b/gcc/doc/generic.texi @@ -2820,7 +2820,6 @@ This function cannot be used with namespaces that have @findex BINFO_TYPE @findex TYPE_FIELDS @findex TYPE_VFIELD -@findex TYPE_METHODS Besides namespaces, the other high-level scoping construct in C++ is the class. (Throughout this manual the term @dfn{class} is used to mean the @@ -2837,7 +2836,7 @@ macro to discern whether or not a particular type is a @code{class} as opposed to a @code{struct}. This macro will be true only for classes declared with the @code{class} tag. -Almost all non-function members are available on the @code{TYPE_FIELDS} +Almost all members are available on the @code{TYPE_FIELDS} list. Given one member, the next can be found by following the @code{TREE_CHAIN}. You should not depend in any way on the order in which fields appear on this list. All nodes on this list will be @@ -2849,7 +2848,11 @@ list, if the enumeration type was declared in the class. (Of course, the @code{TYPE_DECL} for the enumeration type will appear here as well.) There are no entries for base classes on this list. In particular, there is no @code{FIELD_DECL} for the ``base-class portion'' of an -object. +object. If a function member is overloaded, each of the overloaded +functions appears; no @code{OVERLOAD} nodes appear on the @code{TYPE_FIELDS} +list. Implicitly declared functions (including default constructors, +copy constructors, assignment operators, and destructors) will appear on +this list as well. The @code{TYPE_VFIELD} is a compiler-generated field used to point to virtual function tables. It may or may not appear on the @@ -2857,14 +2860,6 @@ virtual function tables. It may or may not appear on the @code{TYPE_VFIELD} just like all the entries on the @code{TYPE_FIELDS} list. -The function members are available on the @code{TYPE_METHODS} list. -Again, subsequent members are found by following the @code{TREE_CHAIN} -field. If a function is overloaded, each of the overloaded functions -appears; no @code{OVERLOAD} nodes appear on the @code{TYPE_METHODS} -list. Implicitly declared functions (including default constructors, -copy constructors, assignment operators, and destructors) will appear on -this list as well. - Every class has an associated @dfn{binfo}, which can be obtained with @code{TYPE_BINFO}. Binfos are used to represent base-classes. The binfo given by @code{TYPE_BINFO} is the degenerate case, whereby every diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index dfde403cbf2..ec29f1d629e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1045,14 +1045,10 @@ See RS/6000 and PowerPC Options. -mquad-memory -mno-quad-memory @gol -mquad-memory-atomic -mno-quad-memory-atomic @gol -mcompat-align-parm -mno-compat-align-parm @gol --mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol --mupper-regs-di -mno-upper-regs-di @gol --mupper-regs -mno-upper-regs @gol -mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol -mgnu-attribute -mno-gnu-attribute @gol -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol --mstack-protector-guard-offset=@var{offset} @gol --mlra -mno-lra} +-mstack-protector-guard-offset=@var{offset}} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -1127,7 +1123,7 @@ See RS/6000 and PowerPC Options. -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -mvis4 -mno-vis4 -mvis4b -mno-vis4b @gol --mcbcond -mno-cbcond -mfmaf -mno-fmaf @gol +-mcbcond -mno-cbcond -mfmaf -mno-fmaf -mfsmuld -mno-fsmuld @gol -mpopc -mno-popc -msubxc -mno-subxc @gol -mfix-at697f -mfix-ut699 -mfix-ut700 -mfix-gr712rc @gol -mlra -mno-lra} @@ -1219,7 +1215,10 @@ See RS/6000 and PowerPC Options. -msse2avx -mfentry -mrecord-mcount -mnop-mcount -m8bit-idiv @gol -mavx256-split-unaligned-load -mavx256-split-unaligned-store @gol -malign-data=@var{type} -mstack-protector-guard=@var{guard} @gol --mmitigate-rop -mgeneral-regs-only -mcall-ms2sysv-xlogues} +-mstack-protector-guard-reg=@var{reg} @gol +-mstack-protector-guard-offset=@var{offset} @gol +-mstack-protector-guard-symbol=@var{symbol} -mmitigate-rop @gol +-mgeneral-regs-only -mcall-ms2sysv-xlogues} @emph{x86 Windows Options} @gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll @gol @@ -7252,13 +7251,20 @@ invoking @option{-O2} on programs that use computed gotos. @item -O3 @opindex O3 Optimize yet more. @option{-O3} turns on all optimizations specified -by @option{-O2} and also turns on the @option{-finline-functions}, -@option{-funswitch-loops}, @option{-fpredictive-commoning}, -@option{-fgcse-after-reload}, @option{-ftree-loop-vectorize}, -@option{-ftree-loop-distribute-patterns}, @option{-fsplit-paths} -@option{-ftree-slp-vectorize}, @option{-fvect-cost-model}, -@option{-ftree-partial-pre}, @option{-fpeel-loops} -and @option{-fipa-cp-clone} options. +by @option{-O2} and also turns on the following optimization flags: +@gccoptlist{-finline-functions @gol +-funswitch-loops @gol +-fpredictive-commoning @gol +-fgcse-after-reload @gol +-ftree-loop-vectorize @gol +-ftree-loop-distribution @gol +-ftree-loop-distribute-patterns @gol +-fsplit-paths @gol +-ftree-slp-vectorize @gol +-fvect-cost-model @gol +-ftree-partial-pre @gol +-fpeel-loops @gol +-fipa-cp-clone} @item -O0 @opindex O0 @@ -7282,7 +7288,8 @@ Disregard strict standards compliance. @option{-Ofast} enables all @option{-O3} optimizations. It also enables optimizations that are not valid for all standard-compliant programs. It turns on @option{-ffast-math} and the Fortran-specific -@option{-fno-protect-parens} and @option{-fstack-arrays}. +@option{-fstack-arrays}, unless @option{-fmax-stack-var-size} is +specified, and @option{-fno-protect-parens}. @item -Og @opindex Og @@ -7360,6 +7367,10 @@ size) for 32-bit GNU/Linux x86 and 32-bit Darwin x86 targets is @option{-fomit-frame-pointer}. You can configure GCC with the @option{--enable-frame-pointer} configure option to change the default. +Note that @option{-fno-omit-frame-pointer} doesn't force a new stack +frame for all functions if it isn't otherwise needed, and hence doesn't +guarantee a new frame pointer for all functions. + Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}. @item -foptimize-sibling-calls @@ -11522,6 +11533,34 @@ of the function name, it is considered to be a match. For C99 and C++ extended identifiers, the function name must be given in UTF-8, not using universal character names. +@item -fpatchable-function-entry=@var{N}[,@var{M}] +@opindex fpatchable-function-entry +Generate @var{N} NOPs right at the beginning +of each function, with the function entry point before the @var{M}th NOP. +If @var{M} is omitted, it defaults to @code{0} so the +function entry points to the address just at the first NOP. +The NOP instructions reserve extra space which can be used to patch in +any desired instrumentation at run time, provided that the code segment +is writable. The amount of space is controllable indirectly via +the number of NOPs; the NOP instruction used corresponds to the instruction +emitted by the internal GCC back-end interface @code{gen_nop}. This behavior +is target-specific and may also depend on the architecture variant and/or +other compilation options. + +For run-time identification, the starting addresses of these areas, +which correspond to their respective function entries minus @var{M}, +are additionally collected in the @code{__patchable_function_entries} +section of the resulting binary. + +Note that the value of @code{__attribute__ ((patchable_function_entry +(N,M)))} takes precedence over command-line option +@option{-fpatchable-function-entry=N,M}. This can be used to increase +the area size or to remove it completely on a single function. +If @code{N=0}, no pad location is recorded. + +The NOP instructions are inserted at---and maybe before, depending on +@var{M}---the function entry address, even before the prologue. + @end table @@ -14084,7 +14123,7 @@ support for the ARMv8.2-A architecture extensions. The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler support for the ARMv8.1-A architecture extension. In particular, it -enables the @samp{+crc} and @samp{+lse} features. +enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features. The value @samp{native} is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture of the host system. This @@ -14202,6 +14241,9 @@ instructions. This is on by default for all possible values for options @item lse Enable Large System Extension instructions. This is on by default for @option{-march=armv8.1-a}. +@item rdma +Enable Round Double Multiply Accumulate instructions. This is on by default +for @option{-march=armv8.1-a}. @item fp16 Enable FP16 extension. This also enables floating-point instructions. @item rcpc @@ -15711,6 +15753,8 @@ incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions. +This option is deprecated. + @item -mabort-on-noreturn @opindex mabort-on-noreturn Generate a call to the function @code{abort} at the end of a @@ -21811,11 +21855,6 @@ This switch enables or disables the generation of ISEL instructions. This switch has been deprecated. Use @option{-misel} and @option{-mno-isel} instead. -@item -mlra -@opindex mlra -Enable Local Register Allocation. By default the port uses LRA. -(i.e. @option{-mno-lra}). - @item -mspe @itemx -mno-spe @opindex mspe @@ -21899,50 +21938,6 @@ Generate code that uses (does not use) the atomic quad word memory instructions. The @option{-mquad-memory-atomic} option requires use of 64-bit mode. -@item -mupper-regs-di -@itemx -mno-upper-regs-di -@opindex mupper-regs-di -@opindex mno-upper-regs-di -Generate code that uses (does not use) the scalar instructions that -target all 64 registers in the vector/scalar floating point register -set that were added in version 2.06 of the PowerPC ISA when processing -integers. @option{-mupper-regs-di} is turned on by default if you use -any of the @option{-mcpu=power7}, @option{-mcpu=power8}, -@option{-mcpu=power9}, or @option{-mvsx} options. - -@item -mupper-regs-df -@itemx -mno-upper-regs-df -@opindex mupper-regs-df -@opindex mno-upper-regs-df -Generate code that uses (does not use) the scalar double precision -instructions that target all 64 registers in the vector/scalar -floating point register set that were added in version 2.06 of the -PowerPC ISA. @option{-mupper-regs-df} is turned on by default if you -use any of the @option{-mcpu=power7}, @option{-mcpu=power8}, -@option{-mcpu=power9}, or @option{-mvsx} options. - -@item -mupper-regs-sf -@itemx -mno-upper-regs-sf -@opindex mupper-regs-sf -@opindex mno-upper-regs-sf -Generate code that uses (does not use) the scalar single precision -instructions that target all 64 registers in the vector/scalar -floating point register set that were added in version 2.07 of the -PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you -use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or -@option{-mcpu=power9} options. - -@item -mupper-regs -@itemx -mno-upper-regs -@opindex mupper-regs -@opindex mno-upper-regs -Generate code that uses (does not use) the scalar -instructions that target all 64 registers in the vector/scalar -floating point register set, depending on the model of the machine. - -If the @option{-mno-upper-regs} option is used, it turns off both -@option{-mupper-regs-sf} and @option{-mupper-regs-df} options. - @item -mfloat128 @itemx -mno-float128 @opindex mfloat128 @@ -22763,9 +22758,11 @@ The @option{-mno-compat-align-parm} option is the default. @item -mstack-protector-guard=@var{guard} @itemx -mstack-protector-guard-reg=@var{reg} @itemx -mstack-protector-guard-offset=@var{offset} +@itemx -mstack-protector-guard-symbol=@var{symbol} @opindex mstack-protector-guard @opindex mstack-protector-guard-reg @opindex mstack-protector-guard-offset +@opindex mstack-protector-guard-symbol Generate stack protection code using canary at @var{guard}. Supported locations are @samp{global} for global canary or @samp{tls} for per-thread canary in the TLS block (the default with GNU libc version 2.4 or later). @@ -22775,7 +22772,8 @@ With the latter choice the options @option{-mstack-protector-guard-offset=@var{offset}} furthermore specify which register to use as base register for reading the canary, and from what offset from that base register. The default for those is as specified in the -relevant ABI. +relevant ABI. @option{-mstack-protector-guard-symbol=@var{symbol}} overrides +the offset with a symbol reference to a canary in the TLS block. @end table @node RX Options @@ -24083,6 +24081,15 @@ Fused Multiply-Add Floating-point instructions. The default is @option{-mfmaf} when targeting a CPU that supports such instructions, such as Niagara-3 and later. +@item -mfsmuld +@itemx -mno-fsmuld +@opindex mfsmuld +@opindex mno-fsmuld +With @option{-mfsmuld}, GCC generates code that takes advantage of the +Floating-point Multiply Single to Double (FsMULd) instruction. The default is +@option{-mfsmuld} when targeting a CPU supporting the architecture versions V8 +or V9 with FPU except @option{-mcpu=leon}. + @item -mpopc @itemx -mno-popc @opindex mpopc @@ -26150,12 +26157,23 @@ to 255, 8-bit unsigned integer divide is used instead of Split 32-byte AVX unaligned load and store. @item -mstack-protector-guard=@var{guard} -@opindex mstack-protector-guard=@var{guard} +@itemx -mstack-protector-guard-reg=@var{reg} +@itemx -mstack-protector-guard-offset=@var{offset} +@opindex mstack-protector-guard +@opindex mstack-protector-guard-reg +@opindex mstack-protector-guard-offset Generate stack protection code using canary at @var{guard}. Supported locations are @samp{global} for global canary or @samp{tls} for per-thread canary in the TLS block (the default). This option has effect only when @option{-fstack-protector} or @option{-fstack-protector-all} is specified. +With the latter choice the options +@option{-mstack-protector-guard-reg=@var{reg}} and +@option{-mstack-protector-guard-offset=@var{offset}} furthermore specify +which segment register (@code{%fs} or @code{%gs}) to use as base register +for reading the canary, and from what offset from that base register. +The default for those is as specified in the relevant ABI. + @item -mmitigate-rop @opindex mmitigate-rop Try to avoid generating code sequences that contain unintended return diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 5a00a2c45c7..ea959208c98 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4871,15 +4871,22 @@ This pattern is not allowed to @code{FAIL}. Set given field in the vector value. Operand 0 is the vector to modify, operand 1 is new value of field and operand 2 specify the field index. -@cindex @code{vec_extract@var{m}} instruction pattern -@item @samp{vec_extract@var{m}} +@cindex @code{vec_extract@var{m}@var{n}} instruction pattern +@item @samp{vec_extract@var{m}@var{n}} Extract given field from the vector value. Operand 1 is the vector, operand 2 -specify field index and operand 0 place to store value into. - -@cindex @code{vec_init@var{m}} instruction pattern -@item @samp{vec_init@var{m}} +specify field index and operand 0 place to store value into. The +@var{n} mode is the mode of the field or vector of fields that should be +extracted, should be either element mode of the vector mode @var{m}, or +a vector mode with the same element mode and smaller number of elements. +If @var{n} is a vector mode, the index is counted in units of that mode. + +@cindex @code{vec_init@var{m}@var{n}} instruction pattern +@item @samp{vec_init@var{m}@var{n}} Initialize the vector to given values. Operand 0 is the vector to initialize -and operand 1 is parallel containing values for individual fields. +and operand 1 is parallel containing values for individual fields. The +@var{n} mode is the mode of the elements, should be either element mode of +the vector mode @var{m}, or a vector mode with the same element mode and +smaller number of elements. @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern @item @samp{vec_cmp@var{m}@var{n}} diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 795e49246af..23e85c7afea 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -4573,6 +4573,15 @@ will select the smallest suitable mode. This section describes the macros that output function entry (@dfn{prologue}) and exit (@dfn{epilogue}) code. +@deftypefn {Target Hook} void TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY (FILE *@var{file}, unsigned HOST_WIDE_INT @var{patch_area_size}, bool @var{record_p}) +Generate a patchable area at the function start, consisting of +@var{patch_area_size} NOP instructions. If the target supports named +sections and if @var{record_p} is true, insert a pointer to the current +location in the table of patchable functions. The default implementation +of the hook places the table of pointers in the special section named +@code{__patchable_function_entries}. +@end deftypefn + @deftypefn {Target Hook} void TARGET_ASM_FUNCTION_PROLOGUE (FILE *@var{file}, HOST_WIDE_INT @var{size}) If defined, a function that outputs the assembler code for entry to a function. The prologue is responsible for setting up the stack frame, diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 98f2e6bce5f..6df08a2c477 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -3650,6 +3650,8 @@ will select the smallest suitable mode. This section describes the macros that output function entry (@dfn{prologue}) and exit (@dfn{epilogue}) code. +@hook TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY + @hook TARGET_ASM_FUNCTION_PROLOGUE @hook TARGET_ASM_FUNCTION_END_PROLOGUE |