diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/aarch64')
28 files changed, 560 insertions, 21 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_1.c b/gcc/testsuite/gcc.target/aarch64/_Float16_1.c index 320f154acf2..00c1a81cf7f 100644 --- a/gcc/testsuite/gcc.target/aarch64/_Float16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/_Float16_1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=armv8.2-a+nofp16" } */ +/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */ #pragma GCC target ("arch=armv8.2-a+nofp16") diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_2.c b/gcc/testsuite/gcc.target/aarch64/_Float16_2.c index 8b2aa1e784c..061606e0b55 100644 --- a/gcc/testsuite/gcc.target/aarch64/_Float16_2.c +++ b/gcc/testsuite/gcc.target/aarch64/_Float16_2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=armv8.2-a+nofp16 -fpermitted-flt-eval-methods=c11" } */ +/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */ #pragma GCC target ("arch=armv8.2-a+nofp16") diff --git a/gcc/testsuite/gcc.target/aarch64/_Float16_3.c b/gcc/testsuite/gcc.target/aarch64/_Float16_3.c index 2d202503850..92d6dd9647d 100644 --- a/gcc/testsuite/gcc.target/aarch64/_Float16_3.c +++ b/gcc/testsuite/gcc.target/aarch64/_Float16_3.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=armv8.2-a+nofp16 -std=c11 -ffp-contract=fast" } */ +/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */ #pragma GCC target ("arch=armv8.2-a+nofp16") diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c index 15606b68990..f2a21ddf2e1 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -march=armv8-a+nolse" } */ +/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */ int foo (int *a) diff --git a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c index b14a7c29437..8d2ae67dfbe 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -march=armv8-a+nolse" } */ +/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */ int foo (int *a) diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c new file mode 100644 index 00000000000..e8dd01db056 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-skip-if "Tiny model won't generate adrp" { *-*-* } { "-mcmodel=tiny" } { "" } } */ + +double d0(void) +{ + double x = 0.0d; + return x; +} + +double dn1(void) +{ + double x = -0.0d; + return x; +} + + +double d1(void) +{ + double x = 1.5d; + return x; +} + +double d2(void) +{ + double x = 123256.0d; + return x; +} + +double d3(void) +{ + double x = 123256123456.0d; + return x; +} + +double d4(void) +{ + double x = 123456123456123456.0d; + return x; +} + +/* { dg-final { scan-assembler-times "movi\td\[0-9\]+, #?0" 1 } } */ + +/* { dg-final { scan-assembler-times "adrp\tx\[0-9\]+, \.LC\[0-9\]" 2 } } */ +/* { dg-final { scan-assembler-times "ldr\td\[0-9\]+, \\\[x\[0-9\], #:lo12:\.LC\[0-9\]\\\]" 2 } } */ + +/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, 1\\\.5e\\\+0" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808" 1 } } */ +/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c new file mode 100644 index 00000000000..1ed3831e139 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +extern __fp16 foo (); +extern void bar (__fp16* x); + +void f1 () +{ + volatile __fp16 a = 17.0; +} + + +void f2 (__fp16 *a) +{ + *a = 17.0; +} + +void f3 () +{ + __fp16 b = foo (); + b = 17.0; + bar (&b); +} + +__fp16 f4 () +{ + __fp16 a = 0; + __fp16 b = 1; + __fp16 c = 2; + __fp16 d = 4; + + __fp16 z = a + b; + z = z + c; + z = z - d; + return z; +} + +__fp16 f5 () +{ + __fp16 a = 16; + bar (&a); + return a; +} + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, #?19520" 3 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0xbc, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x4c, lsl 8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c new file mode 100644 index 00000000000..6f44821e9d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */ +/* { dg-add-options arm_v8_2a_fp16_scalar } */ + +#include <arm_fp16.h> + +float16_t f0(void) +{ + float16_t x = 0.0f; + return x; +} + +float16_t fn1(void) +{ + float16_t x = -0.0f; + return x; +} + +float16_t f1(void) +{ + float16_t x = 256.0f; + return x; +} + +float16_t f2(void) +{ + float16_t x = 123256.0f; + return x; +} + +float16_t f3(void) +{ + float16_t x = 17.0; + return x; +} + +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.4h, ?#0" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x5c, lsl 8" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x7c, lsl 8" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 19520" 1 } } */ +/* { dg-final { scan-assembler-times "fmov\th\[0-9\], w\[0-9\]+" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c new file mode 100644 index 00000000000..7b92a5ae40f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +float f0(void) +{ + float x = 0.0f; + return x; +} + +float fn1(void) +{ + float x = -0.0f; + return x; +} + +float f1(void) +{ + float x = 256.0f; + return x; +} + +float f2(void) +{ + float x = 123256.0f; + return x; +} + +float f3(void) +{ + float x = 2.0f; + return x; +} + +float f4(void) +{ + float x = -20000.1; + return x; +} + + +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, ?#0" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1 } } */ +/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 48128" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0x47f0, lsl 16" 1 } } */ + +/* { dg-final { scan-assembler-times "fmov\ts\[0-9\]+, 2\\\.0e\\\+0" 1 } } */ + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 16435" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0xc69c, lsl 16" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c new file mode 100644 index 00000000000..6ac9065037f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/int_mov_immediate_1.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3" } */ + +long long f1(void) +{ + return 0xffff6666; +} + +int f3(void) +{ + return 0xffff6666; +} + + +long f2(void) +{ + return 0x11110000ffff6666; +} + +long f4(void) +{ + return 0x11110001ffff6666; +} + +long f5(void) +{ + return 0x111100001ff6666; +} + +long f6(void) +{ + return 0x00001111ffff6666; +} + +long f7(void) +{ + return 0x000011116666ffff; +} + +long f8(void) +{ + return 0x0f0011116666ffff; +} + +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, -39322" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 4294927974" 3 } } */ +/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 1718026239" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -2576941057" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -39322" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 26214" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0xf00, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 48" 2 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1000, lsl 32" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1111, lsl 32" 3 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x111, lsl 48" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1ff, lsl 16" 1 } } */ +/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x1, lsl 32" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c index c917f81c022..114d8c1a6c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr63304_1.c +++ b/gcc/testsuite/gcc.target/aarch64/pr63304_1.c @@ -4,10 +4,10 @@ #pragma GCC target ("+nothing+simd, cmodel=small") int -cal (float a) +cal (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else @@ -19,11 +19,11 @@ cal (float a) #pragma GCC target ("cmodel=large") int -cal2 (float a) +cal2 (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else @@ -33,11 +33,11 @@ cal2 (float a) #pragma GCC pop_options int -cal3 (float a) +cal3 (double a) { - float b = 1.2; - float c = 2.2; + double b = 3.2; + double c = 2.2; if ((a + b) != c) return 0; else diff --git a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c new file mode 100644 index 00000000000..a889dfdd895 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */ +/* { dg-require-effective-target lp64 } */ + +__int128 +t (void) +{ + return (__int128)1 << 80; +} + +/* { dg-final { scan-assembler "adr" } } */ +/* { dg-final { scan-assembler-not "adrp" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr81414.C b/gcc/testsuite/gcc.target/aarch64/pr81414.C new file mode 100644 index 00000000000..53dfc7cf800 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr81414.C @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=cortex-a57" } */ + +typedef __Float32x2_t float32x2_t; +float32x2_t +foo1 (float32x2_t __a, float32x2_t __b, float32x2_t __c) { + return __b * __c + __a; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c new file mode 100644 index 00000000000..df777581ab4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vmla_elem_1.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +typedef short int __attribute__ ((vector_size (16))) v8hi; + +v8hi +mla8hi (v8hi v0, v8hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + + +v8hi +mls8hi (v8hi v0, v8hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.8h, v\[0-9\]\+\\.8h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef short int __attribute__ ((vector_size (8))) v4hi; + +v4hi +mla4hi (v4hi v0, v4hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v4hi +mls4hi (v4hi v0, v4hi v1, short int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4h, v\[0-9\]\+\\.4h, v\[0-9\]\+\\.h\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef int __attribute__ ((vector_size (16))) v4si; + +v4si +mla4si (v4si v0, v4si v1, int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v4si +mls4si (v4si v0, v4si v1, int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.4s, v\[0-9\]\+\\.4s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 - v1 * v2; +} + +typedef int __attribute__((vector_size (8))) v2si; + +v2si +mla2si (v2si v0, v2si v1, int v2) +{ + /* { dg-final { scan-assembler "mla\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 + v1 * v2; +} + +v2si +mls2si (v2si v0, v2si v1, int v2) +{ + /* { dg-final { scan-assembler "mls\\tv\[0-9\]\+\\.2s, v\[0-9\]\+\\.2s, v\[0-9\]\+\\.s\\\[0\\\]" } } */ + return v0 - v1 * v2; +} diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c index 0527d0c3d61..4a3a1ee233a 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_1.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx -dA" } */ +/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */ /* Test that cpu attribute overrides the command-line -mcpu. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c index 6d0577178f0..18499047112 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=armv8-a+simd" } */ +/* { dg-options "-O2 -march=armv8-a+simd -mcpu=generic" } */ /* Using a SIMD intrinsic from a function tagged with nosimd should fail due to inlining rules. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_13.c b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c index 0f81e9aa587..d5bee3a7b90 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_13.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */ +/* { dg-options "-O2 -march=armv8-a+crc+crypto -mcpu=generic" } */ #include "arm_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_15.c b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c index 2d8c7b955ce..108b372e4cc 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_15.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-march=armv8-a+crypto -save-temps" } */ +/* { dg-options "-march=armv8-a+crypto -mcpu=generic -save-temps" } */ /* Check that "+nothing" clears the ISA flags. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c index 39bb6e7dd36..f84342d889f 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_2.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -march=armv8-a -ftree-vectorize -fdump-tree-vect-all" } */ /* The various ways to turn off simd availability should turn off vectorization. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_3.c b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c index 9f9c27654f6..eacec5a6552 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_3.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */ +/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -march=armv8-a -mcpu=generic -save-temps" } */ /* Check that the attribute overrides the command line option and the fix is applied once. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_4.c b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c index d98ba42303f..e0114084800 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_4.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */ +/* { dg-options "-O2 -march=armv8-a+nocrc -mcpu=generic -save-temps" } */ #include "arm_acle.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_7.c b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c index 818d327705f..6067ffed30e 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_7.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx -dA" } */ +/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */ /* Make sure that #pragma overrides command line option and target attribute overrides the pragma. */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c index 42f14c461a2..c74cc900f98 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c index d6e7b681832..d0a62b83351 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ /* Make sure that we don't ICE when dealing with vector parameters in a simd-tagged function within a non-simd translation unit. */ diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c new file mode 100644 index 00000000000..33a2c0f45af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +f (unsigned char *p) +{ + return p[0] == 50 || p[0] == 52; +} + +int +g (unsigned char *p) +{ + return (p[0] >> 4 & 0xfd) == 0; +} + +/* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr 4" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-xorsign_exec.c b/gcc/testsuite/gcc.target/aarch64/vect-xorsign_exec.c new file mode 100644 index 00000000000..cfa22115831 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-xorsign_exec.c @@ -0,0 +1,58 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details --save-temps" } */ + +extern void abort (); + +#define N 16 +float a[N] = {-0.1f, -3.2f, -6.3f, -9.4f, + -12.5f, -15.6f, -18.7f, -21.8f, + 24.9f, 27.1f, 30.2f, 33.3f, + 36.4f, 39.5f, 42.6f, 45.7f}; +float b[N] = {-1.2f, 3.4f, -5.6f, 7.8f, + -9.0f, 1.0f, -2.0f, 3.0f, + -4.0f, -5.0f, 6.0f, 7.0f, + -8.0f, -9.0f, 10.0f, 11.0f}; +float r[N]; + +double ad[N] = {-0.1d, -3.2d, -6.3d, -9.4d, + -12.5d, -15.6d, -18.7d, -21.8d, + 24.9d, 27.1d, 30.2d, 33.3d, + 36.4d, 39.5d, 42.6d, 45.7d}; +double bd[N] = {-1.2d, 3.4d, -5.6d, 7.8d, + -9.0d, 1.0d, -2.0d, 3.0d, + -4.0d, -5.0d, 6.0d, 7.0d, + -8.0d, -9.0d, 10.0d, 11.0d}; +double rd[N]; + +int +main (void) +{ + int i; + + for (i = 0; i < N; i++) + r[i] = a[i] * __builtin_copysignf (1.0f, b[i]); + + /* check results: */ + for (i = 0; i < N; i++) + if (r[i] != a[i] * __builtin_copysignf (1.0f, b[i])) + abort (); + + for (i = 0; i < N; i++) + rd[i] = ad[i] * __builtin_copysign (1.0d, bd[i]); + + /* check results: */ + for (i = 0; i < N; i++) + if (rd[i] != ad[i] * __builtin_copysign (1.0d, bd[i])) + abort (); + + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { scan-assembler "\[ \t\]?eor\[ \t\]?" } } */ +/* { dg-final { scan-assembler "\[ \t\]?and\[ \t\]?" } } */ +/* { dg-final { scan-assembler-not "copysign" } } */ +/* { dg-final { scan-assembler-not "\[ \t\]?orr\[ \t\]?" } } */ +/* { dg-final { scan-assembler-not "\[ \t\]?fmul\[ \t\]?" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/xorsign.c b/gcc/testsuite/gcc.target/aarch64/xorsign.c new file mode 100644 index 00000000000..22c5829449d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xorsign.c @@ -0,0 +1,86 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +double +check_d_pos (double x, double y) +{ + return x * __builtin_copysign (1.0, y); +} + +float +check_f_pos (float x, float y) +{ + return x * __builtin_copysignf (1.0f, y); +} + +long double +check_l_pos (long double x, long double y) +{ + return x * __builtin_copysignl (1.0, y); +} + +/* --------------- */ + +double +check_d_neg (double x, double y) +{ + return x * __builtin_copysign (-1.0, y); +} + +float +check_f_neg (float x, float y) +{ + return x * __builtin_copysignf (-1.0f, y); +} + +long double +check_l_neg (long double x, long double y) +{ + return x * __builtin_copysignl (-1.0, y); +} + +/* --------------- */ + +double +check_d_pos_rev (double x, double y) +{ + return __builtin_copysign (1.0, y) * x; +} + +float +check_f_pos_rev (float x, float y) +{ + return __builtin_copysignf (1.0f, y) * x; +} + +long double +check_l_pos_rev (long double x, long double y) +{ + return __builtin_copysignl (1.0, y) * x; +} + +/* --------------- */ + +double +check_d_neg_rev (double x, double y) +{ + return __builtin_copysign (-1.0, y) * x; +} + +float +check_f_neg_rev (float x, float y) +{ + return __builtin_copysignf (-1.0f, y) * x; +} + +long double +check_l_neg_rev (long double x, long double y) +{ + return __builtin_copysignl (-1.0, y) * x; +} + +/* { dg-final { scan-assembler "\[ \t\]?eor\[ \t\]?" } } */ +/* { dg-final { scan-assembler "\[ \t\]?and\[ \t\]?" } } */ +/* { dg-final { scan-assembler-not "copysign" } } */ +/* { dg-final { scan-assembler-not "\[ \t\]?orr\[ \t\]?" } } */ +/* { dg-final { scan-assembler-not "\[ \t\]?fmul\[ \t\]?" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xorsign_exec.c b/gcc/testsuite/gcc.target/aarch64/xorsign_exec.c new file mode 100644 index 00000000000..64bf8044cbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xorsign_exec.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O -ffast-math" } */ + +#include <math.h> + +extern void abort(void); + +static double x = 2.0; +static float y = 2.0; + +int main() +{ + if ((2.5 * __builtin_copysign(1.0d, x)) != 2.5) + abort(); + + if ((2.5 * __builtin_copysign(1.0f, y)) != 2.5) + abort(); + + if ((2.5 * __builtin_copysignf(1.0d, -x)) != -2.5) + abort(); + + if ((2.5 * __builtin_copysignf(1.0f, -y)) != -2.5) + abort(); + + return 0; +} |