diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
30 files changed, 332 insertions, 9 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/ands_3.c b/gcc/testsuite/gcc.target/aarch64/ands_3.c new file mode 100644 index 00000000000..42cb7f0f0bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ands_3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +f9 (unsigned char x, int y) +{ + if (y > 1 && x == 0) + return 10; + return x; +} + +/* { dg-final { scan-assembler "ands\t(x|w)\[0-9\]+,\[ \t\]*(x|w)\[0-9\]+,\[ \t\]*255" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c b/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c index a0f59825227..0d60ef59509 100644 --- a/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c +++ b/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c @@ -1,4 +1,4 @@ -/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */ +/* { dg-error "unknown" "" {target "aarch64*-*-*" } 0 } */ /* { dg-options "-O2 -march=dummy" } */ void f () diff --git a/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c b/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c index f1f3ea38c2a..cecba918818 100644 --- a/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c +++ b/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c @@ -1,4 +1,4 @@ -/* { dg-error "missing" "" {target "aarch64*-*-*" } } */ +/* { dg-error "missing" "" {target "aarch64*-*-*" } 0 } */ /* { dg-options "-O2 -march=+dummy" } */ void f () diff --git a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c index ddba6554471..4f330e8fda7 100644 --- a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c +++ b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c @@ -1,4 +1,4 @@ -/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */ +/* { dg-error "unknown" "" {target "aarch64*-*-*" } 0 } */ /* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */ /* { dg-options "-O2 -mcpu=dummy" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c index ae42436031b..3701b10ac20 100644 --- a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c +++ b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c @@ -1,4 +1,4 @@ -/* { dg-error "missing" "" {target "aarch64*-*-*" } } */ +/* { dg-error "missing" "" {target "aarch64*-*-*" } 0 } */ /* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */ /* { dg-options "-O2 -mcpu=cortex-a53+no" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c index 8bc6e2fe049..04acba67353 100644 --- a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c +++ b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c @@ -1,4 +1,4 @@ -/* { dg-error "invalid feature" "" {target "aarch64*-*-*" } } */ +/* { dg-error "invalid feature" "" {target "aarch64*-*-*" } 0 } */ /* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */ /* { dg-options "-O2 -mcpu=cortex-a53+dummy" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c index 58355b42f84..268321e16e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c +++ b/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c @@ -1,4 +1,4 @@ -/* { dg-error "missing" "" {target "aarch64*-*-*" } } */ +/* { dg-error "missing" "" {target "aarch64*-*-*" } 0 } */ /* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "" } } */ /* { dg-options "-O2 -mcpu=+dummy" } */ diff --git a/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c b/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c new file mode 100644 index 00000000000..14b1f736093 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=thunderx" } */ + +struct ldp +{ + long long c; + int a, b; +}; + + +int f(struct ldp *a) +{ + return a->a + a->b; +} + + +/* We know the alignement of a->a to be 8 byte aligned so it is profitable + to do ldp. */ +/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c b/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c new file mode 100644 index 00000000000..3093ad0e1f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=thunderx" } */ + +struct noldp +{ + int a, b; +}; + + +int f(struct noldp *a) +{ + return a->a + a->b; +} + +/* We know the alignement of a->a to be 4 byte aligned so it is not profitable + to do ldp. */ +/* { dg-final { scan-assembler-not "ldp\tw\[0-9\]+, w\[0-9\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr77476.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr77476.c new file mode 100644 index 00000000000..bae00e4ee51 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr77476.c @@ -0,0 +1,9 @@ +/* PR target/77476 */ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512bw" } */ +/* { dg-require-effective-target avx512bw } */ + +#include "avx512bw-check.h" +#define PR77476_TEST avx512bw_test + +#include "avx512f-pr77476.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-pr77476.c b/gcc/testsuite/gcc.target/i386/avx512dq-pr77476.c new file mode 100644 index 00000000000..77d024e053e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-pr77476.c @@ -0,0 +1,9 @@ +/* PR target/77476 */ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512dq" } */ +/* { dg-require-effective-target avx512dq } */ + +#include "avx512dq-check.h" +#define PR77476_TEST avx512dq_test + +#include "avx512f-pr77476.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c b/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c index feff9558a15..ec09e4c6182 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c @@ -51,7 +51,7 @@ avx512f_test (void) dst = _mm512_kunpackb (src1, src2); x = _mm512_mask_add_ps (x, dst, x, x); - dst_ref = ((src2 << 8) | src1) & 0xFFFF; + dst_ref = ((src1 << 8) | src2) & 0xFFFF; if (dst != dst_ref) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr77476.c b/gcc/testsuite/gcc.target/i386/avx512f-pr77476.c new file mode 100644 index 00000000000..f3bd509535a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr77476.c @@ -0,0 +1,76 @@ +/* PR target/77476 */ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-require-effective-target avx512f } */ + +#ifndef PR77476_TEST +#include "avx512f-check.h" +#define PR77476_TEST avx512f_test +#endif + +unsigned short s; +unsigned int i; +unsigned long long l; + +void +f1 (void) +{ + unsigned char a = 0xff; + asm volatile ("" : "+Yk" (a)); + s = a; +} + +void +f2 (void) +{ + unsigned char a = 0xff; + asm volatile ("" : "+Yk" (a)); + i = a; +} + +void +f3 (void) +{ + unsigned char a = 0xff; + asm volatile ("" : "+Yk" (a)); + l = a; +} + +void +f4 (void) +{ + unsigned short a = 0xffff; + asm volatile ("" : "+Yk" (a)); + i = a; +} + +void +f5 (void) +{ + unsigned short a = 0xffff; + asm volatile ("" : "+Yk" (a)); + l = a; +} + +#ifdef __AVX512BW__ +void +f6 (void) +{ + unsigned int a = 0xffffffff; + asm volatile ("" : "+Yk" (a)); + l = a; +} +#endif + +static void +PR77476_TEST () +{ + f1 (); if (s != 0xff) __builtin_abort (); s = 0; + f2 (); if (i != 0xff) __builtin_abort (); i = 0; + f3 (); if (l != 0xff) __builtin_abort (); l = 0; + f4 (); if (i != 0xffff) __builtin_abort (); i = 0; + f5 (); if (l != 0xffff) __builtin_abort (); l = 0; +#ifdef __AVX512BW__ + f6 (); if (l != 0xffffffff) __builtin_abort (); l = 0; +#endif +} diff --git a/gcc/testsuite/gcc.target/i386/pr65990.c b/gcc/testsuite/gcc.target/i386/pr65990.c index c0e5bb6fdf7..0ec8fadacf7 100644 --- a/gcc/testsuite/gcc.target/i386/pr65990.c +++ b/gcc/testsuite/gcc.target/i386/pr65990.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mtune=btver2 -mmemcpy-strategy=rep_8byte:-1:noalign" } -/* { dg-error "stringop strategy name rep_8byte specified for option -mmemcpy_strategy= not supported for 32-bit code" "" { target ia32 } 0 } */ +/* { dg-error "strategy name 'rep_8byte' specified for option '-mmemcpy_strategy=' not supported for 32-bit code" "" { target ia32 } 0 } */ struct U9 { diff --git a/gcc/testsuite/gcc.target/i386/pr68633.c b/gcc/testsuite/gcc.target/i386/pr68633.c index d7f513d276a..f2b594c3bc4 100644 --- a/gcc/testsuite/gcc.target/i386/pr68633.c +++ b/gcc/testsuite/gcc.target/i386/pr68633.c @@ -19,6 +19,6 @@ TEST () __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (2) ); k3 = _mm512_kunpackb (k1, k2); - if (k3 != 0x201) + if (k3 != 0x102) abort (); } diff --git a/gcc/testsuite/gcc.target/i386/pr69255-1.c b/gcc/testsuite/gcc.target/i386/pr69255-1.c new file mode 100644 index 00000000000..7a666d34298 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr69255-1.c @@ -0,0 +1,17 @@ +/* PR target/69255 */ +/* { dg-do compile } */ +/* { dg-options "-msse4 -mno-avx" } */ + +#pragma GCC target "avx512vl" +#pragma GCC target "no-avx512vl" +__attribute__ ((__vector_size__ (32))) long long a; +__attribute__ ((__vector_size__ (16))) int b; + +void +foo (const long long *p) +{ + a = __builtin_ia32_gather3siv4di (a, p, b, 1, 1); /* { dg-error "needs isa option -m32 -mavx512vl" } */ +} + +/* { dg-warning "AVX vector return without AVX enabled changes the ABI" "" { target *-*-* } 13 } */ +/* { dg-warning "AVX vector argument without AVX enabled changes the ABI" "" { target *-*-* } 13 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr69255-2.c b/gcc/testsuite/gcc.target/i386/pr69255-2.c new file mode 100644 index 00000000000..28eb57bbfcc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr69255-2.c @@ -0,0 +1,17 @@ +/* PR target/69255 */ +/* { dg-do compile } */ +/* { dg-options "-msse4 -mno-avx" } */ + +#pragma GCC target "avx512vl" +#pragma GCC target "" +__attribute__ ((__vector_size__ (32))) long long a; +__attribute__ ((__vector_size__ (16))) int b; + +void +foo (const long long *p) +{ + __builtin_ia32_gather3siv4di (a, p, b, 1, 1); /* { dg-error "needs isa option -m32 -mavx512vl" } */ +} + +/* { dg-warning "AVX vector return without AVX enabled changes the ABI" "" { target *-*-* } 13 } */ +/* { dg-warning "AVX vector argument without AVX enabled changes the ABI" "" { target *-*-* } 13 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr69255-3.c b/gcc/testsuite/gcc.target/i386/pr69255-3.c new file mode 100644 index 00000000000..41fb4a2cf50 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr69255-3.c @@ -0,0 +1,17 @@ +/* PR target/69255 */ +/* { dg-do compile } */ +/* { dg-options "-msse4 -mno-avx" } */ + +#pragma GCC target "avx512vl" +#pragma GCC target "" +__attribute__ ((__vector_size__ (32))) long long a; +__attribute__ ((__vector_size__ (16))) int b; + +void +foo (const long long *p, __attribute__ ((__vector_size__ (32))) long long *q) +{ + *q = __builtin_ia32_gather3siv4di (a, p, b, 1, 1); /* { dg-error "needs isa option -m32 -mavx512vl" } */ +} + +/* { dg-warning "AVX vector return without AVX enabled changes the ABI" "" { target *-*-* } 13 } */ +/* { dg-warning "AVX vector argument without AVX enabled changes the ABI" "" { target *-*-* } 13 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr77452.c b/gcc/testsuite/gcc.target/i386/pr77452.c new file mode 100644 index 00000000000..89c5329ff89 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr77452.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O -mavx512f -fno-split-wide-types --param max-combine-insns=2" } */ + +typedef unsigned int U __attribute__((vector_size(64))); +typedef unsigned __int128 V __attribute__((vector_size(64))); + +V +foo(V v) +{ + v[0] = 1u << (( ((V)(U){1, 1, v[0]})[0]) & 0xf) + >> ((-~((V)(U){1, 1, v[0]})[0]) & 0xf); + return v; +} diff --git a/gcc/testsuite/gcc.target/i386/pr77526.c b/gcc/testsuite/gcc.target/i386/pr77526.c new file mode 100644 index 00000000000..91b946a3660 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr77526.c @@ -0,0 +1,13 @@ +/* PR target/77526 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-Os -fno-forward-propagate -fno-gcse -fno-rerun-cse-after-loop -mstringop-strategy=byte_loop -Wno-psabi" } */ + +typedef char U __attribute__((vector_size(64))); +typedef __int128 V __attribute__((vector_size(64))); + +V +foo (int a, int b, __int128 c, U u) +{ + u = (u >> (u & 7)) | (u << -(u & 7)); + return a + b + c + (V)u; +} diff --git a/gcc/testsuite/gcc.target/i386/pr77594.c b/gcc/testsuite/gcc.target/i386/pr77594.c new file mode 100644 index 00000000000..96c51fd71fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr77594.c @@ -0,0 +1,11 @@ +/* PR middle-end/77594 */ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +int +foo (int a, int *b) +{ + return __builtin_sub_overflow (0, a, b); +} + +/* { dg-final { scan-assembler-times "\tjn?o\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/spellcheck-options-1.c b/gcc/testsuite/gcc.target/i386/spellcheck-options-1.c new file mode 100644 index 00000000000..275f86c178d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/spellcheck-options-1.c @@ -0,0 +1,7 @@ +/* Verify that we provide a hint if the user misspells an option argument + (PR middle-end/77475). */ + +/* { dg-do compile } */ +/* { dg-options "-march=hasvel" } */ +/* { dg-error "bad value .'hasvel'. for '-march=' switch" "" { target *-*-* } 0 } */ +/* { dg-message "valid arguments to '-march=' switch are: \[^\n\r]*; did you mean 'haswell'?" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/spellcheck-options-2.c b/gcc/testsuite/gcc.target/i386/spellcheck-options-2.c new file mode 100644 index 00000000000..848906245af --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/spellcheck-options-2.c @@ -0,0 +1,7 @@ +/* Verify that we provide a hint if the user misspells an option argument + (PR middle-end/77475). */ + +/* { dg-do compile } */ +/* { dg-options "-mtune=hasvel" } */ +/* { dg-error "bad value .'hasvel'. for '-mtune=' switch" "" { target *-*-* } 0 } */ +/* { dg-message "valid arguments to '-mtune=' switch are: \[^\n\r]*; did you mean 'haswell'?" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/spellcheck-options-3.c b/gcc/testsuite/gcc.target/i386/spellcheck-options-3.c new file mode 100644 index 00000000000..115cef178bd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/spellcheck-options-3.c @@ -0,0 +1,7 @@ +/* Verify that we provide a hint if the user misspells an option argument + (PR middle-end/77475). */ + +/* { dg-do compile } */ +/* { dg-options "-mmemcpy-strategy=unroled_looop:8:align" } */ +/* { dg-error "wrong strategy name 'unroled_looop' specified for option '-mmemcpy_strategy='" "" { target *-*-* } 0 } */ +/* { dg-message "valid arguments to '-mmemcpy_strategy=' are: \[^\n\r]*; did you mean 'unrolled_loop'?" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/spellcheck-options-4.c b/gcc/testsuite/gcc.target/i386/spellcheck-options-4.c new file mode 100644 index 00000000000..d39bd239f89 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/spellcheck-options-4.c @@ -0,0 +1,7 @@ +/* Verify that we provide a hint if the user misspells an option argument + (PR middle-end/77475). */ + +/* { dg-do compile } */ + +__attribute__((target ("arch=hasvel"))) void foo (void) {} /* { dg-error "bad value .'hasvel'. for 'target..arch=..' attribute" } */ +/* { dg-message "valid arguments to 'target..arch=..' attribute are: \[^\n\r]*; did you mean 'haswell'?" "" { target *-*-* } 6 } */ diff --git a/gcc/testsuite/gcc.target/msp430/function-attributes-1.c b/gcc/testsuite/gcc.target/msp430/function-attributes-1.c new file mode 100644 index 00000000000..7a3b7bea885 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/function-attributes-1.c @@ -0,0 +1,9 @@ +void __attribute__((weak, interrupt)) +weak_interrupt (void) { +} + +void __attribute__((interrupt(11))) +interrupt_number (void) { +} + +/* { dg-final { scan-assembler-times "__interrupt_vector_" 1 } } */ diff --git a/gcc/testsuite/gcc.target/msp430/function-attributes-2.c b/gcc/testsuite/gcc.target/msp430/function-attributes-2.c new file mode 100644 index 00000000000..fcb2fb2f011 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/function-attributes-2.c @@ -0,0 +1,3 @@ +void __attribute__((weak, interrupt(10))) +weak_interrupt_number (void) { +} /* { dg-error "argument to interrupt attribute is unsupported for weak functions" } */ diff --git a/gcc/testsuite/gcc.target/msp430/function-attributes-3.c b/gcc/testsuite/gcc.target/msp430/function-attributes-3.c new file mode 100644 index 00000000000..b0acf4aae52 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/function-attributes-3.c @@ -0,0 +1,3 @@ +void __attribute__((interrupt("nmi"))) __attribute__((weak)) +interrupt_name_weak (void) { +} /* { dg-error "argument to interrupt attribute is unsupported for weak functions" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr77289.c b/gcc/testsuite/gcc.target/powerpc/pr77289.c new file mode 100644 index 00000000000..f8ebf1f9309 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr77289.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mlra -mupdate -fno-auto-inc-dec" } */ + +/* PR 77289: LRA ICEs due to invalid constraint checking. */ + +void dummy0 (float *); +float bar0 (float); +void +foo0 (long a, long b) +{ + float c[0]; + b = 0; + for (; b < a; b++) + c[b] = bar0 (c[b]); + dummy0 (c); +} + +void dummy1 (long *); +long bar1 (long); +void +foo1 (long a, long b) +{ + long array[128]; + long *c = array; + for (b=0; b < a; b++) + c[b] = bar1 (c[b]); + dummy1 (c); +} diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c new file mode 100644 index 00000000000..5b999488539 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O3 " } */ +/* { dg-final { scan-assembler "lxvd2x" } } */ +/* { dg-final { scan-assembler "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "xxpermdi" } } */ + +/* Verify that swap optimization works correctly for a truncating splat. */ + +/* Test case to resolve PR77613. */ + +void pr77613 (signed short a, signed short *x, signed short *y) +{ + unsigned long i; + + for (i = 0; i < 1024; i++) + y[i] = a * x[i] + y[i]; +} |