diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
61 files changed, 637 insertions, 41 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_3.c b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_3.c new file mode 100644 index 00000000000..ca772cb999e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O3 -fno-math-errno -fno-fp-int-builtin-inexact" } */ + +#define TEST(name, float_type, int_type, fn) void f_##name (float_type x) \ +{ \ + volatile int_type b = __builtin_##fn (x); \ +} + +TEST (dld, double, long, lrint) +TEST (flf, float , long, lrintf) + +TEST (did, double, int, lrint) +TEST (fif, float , int, lrintf) + +/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, \[d,s\]\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "bl\tlrint" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/nosplit-di-const-volatile_1.c b/gcc/testsuite/gcc.target/aarch64/nosplit-di-const-volatile_1.c new file mode 100644 index 00000000000..da5975ad165 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/nosplit-di-const-volatile_1.c @@ -0,0 +1,15 @@ +/* Check that storing the 64-bit immediate to a volatile location is done + with a single store. */ + +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned long long u64; + +void bar (u64 *x) +{ + *(volatile u64 *)x = 0xabcdef10abcdef10ULL; +} + +/* { dg-final { scan-assembler-times "str\tx..?, .*" 1 } } */ +/* { dg-final { scan-assembler-not "str\tw..?, .*" } } */ diff --git a/gcc/testsuite/gcc.target/arc/delay-slot-limm.c b/gcc/testsuite/gcc.target/arc/delay-slot-limm.c new file mode 100644 index 00000000000..e5de3c4badd --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/delay-slot-limm.c @@ -0,0 +1,52 @@ +/* We have encountered an issue that a "mov_s.ne" instruction * + * with an immediate value was put in the delay slot of a * + * branch: * + * * + * bne.d @.L1 # 33 [c=20 l=4] *branch_insn * + * mov_s.ne r0,7 # 35 [c=0 l=6] *movsi_ne/2 * + * * + * This is not sanctioned and must not happen. The test below * + * is a reduced version of the source code leading to the * + * problem. */ + +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=archs -Og" } */ +typedef struct +{ + struct + { + int length; + } table; +} room; + +struct house +{ + room *r; +}; + +int glob; + +_Bool bar(); + +int func(struct house *h, int i, int whatever) +{ + for (;;) + { + _Bool a; + if (h && h->r[i].table.length == glob) + { + if (whatever) + { + a = bar(); + if (__builtin_expect(!a, 0)) + return 7; + } + break; + } + } + return 0; +} + +/* no 'mov_s.ne r,limm' in a delay slot */ +/* { dg-final { scan-assembler-not "bne.d\.*\n\\s\+mov_s.ne\\s+r\[0-9\]+,7" } } */ diff --git a/gcc/testsuite/gcc.target/arc/pic-2.c b/gcc/testsuite/gcc.target/arc/pic-2.c new file mode 100644 index 00000000000..4b0e17126e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/pic-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-skip-if "PIC not available for ARC6xx" { arc6xx } } */ +/* { dg-options "-mno-sdata -O2 -fpic -fno-builtin" } */ + +/* Check if we resolve correctly complex PIC addresses. */ + +char *foo (unsigned size) +{ + static char buf[32]; + register int i; + + if (size > 31) + size = 31; + + for (i = 0; i < size; i++) + { + buf[i] = ' '; + } + buf[size] = '\0'; + return buf; +} + +/* { dg-final { scan-assembler "@buf.\[0-9\]\+@pcl-1" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/crc_hf_1.c b/gcc/testsuite/gcc.target/arm/acle/crc_hf_1.c new file mode 100644 index 00000000000..e6cbfc0b33e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/crc_hf_1.c @@ -0,0 +1,14 @@ +/* Test that using an Armv8-a hard-float target doesn't + break CRC intrinsics. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_hard_vfp_ok } */ +/* { dg-options "-mfloat-abi=hard -march=armv8-a+simd+crc" } */ + +#include <arm_acle.h> + +uint32_t +foo (uint32_t a, uint32_t b) +{ + return __crc32cw (a, b); +} diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp index d82306ed630..dcea829965e 100644 --- a/gcc/testsuite/gcc.target/arm/multilib.exp +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -753,6 +753,28 @@ if {[multilib_config "rmprofile"] } { {-march=armv8-m.main+fp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" {-march=armv8-m.main+fp+dsp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv7-r+fp -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp" + {-march=armv7-r+fp -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard" + {-march=armv7-r+fp+idiv -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp" + {-march=armv7-r+fp+idiv -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard" + {-march=armv7-r+vfpv3-d16-fp16 -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp" + {-march=armv7-r+vfpv3-d16-fp16 -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard" + {-march=armv7-r+vfpv3-d16-fp16+idiv -mfpu=auto -mfloat-abi=softfp} "thumb/v7+fp/softfp" + {-march=armv7-r+vfpv3-d16-fp16+idiv -mfpu=auto -mfloat-abi=hard} "thumb/v7+fp/hard" + {-march=armv7-r+fp.sp -mfpu=auto -mfloat-abi=softfp} "thumb/v7-r+fp.sp/softfp" + {-march=armv7-r+fp.sp -mfpu=auto -mfloat-abi=hard} "thumb/v7-r+fp.sp/hard" + {-march=armv7-r+fp.sp+idiv -mfpu=auto -mfloat-abi=softfp} "thumb/v7-r+fp.sp/softfp" + {-march=armv7-r+fp.sp+idiv -mfpu=auto -mfloat-abi=hard} "thumb/v7-r+fp.sp/hard" + {-march=armv7-r+vfpv3xd -mfpu=auto -mfloat-abi=softfp} "thumb/v7-r+fp.sp/softfp" + {-march=armv7-r+vfpv3xd -mfpu=auto -mfloat-abi=hard} "thumb/v7-r+fp.sp/hard" + {-march=armv7-r+vfpv3xd+idiv -mfpu=auto -mfloat-abi=softfp} "thumb/v7-r+fp.sp/softfp" + {-march=armv7-r+vfpv3xd+idiv -mfpu=auto -mfloat-abi=hard} "thumb/v7-r+fp.sp/hard" + {-march=armv7-r+vfpv3xd-fp16+idiv -mfpu=auto -mfloat-abi=softfp} "thumb/v7-r+fp.sp/softfp" + {-march=armv7-r+vfpv3xd-fp16+idiv -mfpu=auto -mfloat-abi=hard} "thumb/v7-r+fp.sp/hard" + {-march=armv8-r+fp.sp -mfpu=auto -mfloat-abi=softfp} "thumb/v7-r+fp.sp/softfp" + {-march=armv8-r+fp.sp -mfpu=auto -mfloat-abi=hard} "thumb/v7-r+fp.sp/hard" + {-march=armv8-r+crc+fp.sp -mfpu=auto -mfloat-abi=softfp} "thumb/v7-r+fp.sp/softfp" + {-march=armv8-r+crc+fp.sp -mfpu=auto -mfloat-abi=hard} "thumb/v7-r+fp.sp/hard" } { check_multi_dir $opts $dir } diff --git a/gcc/testsuite/gcc.target/arm/pr88167-1.c b/gcc/testsuite/gcc.target/arm/pr88167-1.c new file mode 100644 index 00000000000..517a86d6e4b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr88167-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-options "-O2 -mthumb" } */ + +void *retaddr; + +void foo (void) { + retaddr = __builtin_return_address (0); + + /* Used for enforcing registers stacking. */ + asm volatile ("" : : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12"); +} + +/* { dg-final { scan-assembler-not "mov\tlr," } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr88167-2.c b/gcc/testsuite/gcc.target/arm/pr88167-2.c new file mode 100644 index 00000000000..6a303345eb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr88167-2.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +int __attribute__((noclone, noinline)) +foo (int a, long long b) { + /* Used for enforcing registers stacking. */ + asm volatile ("" : : : "r0", "r1", "r2", "r3", + "r8", "r9", "r10", "r11", "r12"); + return (int) b; +} + +int main () +{ + if (foo (1, 0x1000000000000003LL) != 3) + __builtin_abort (); + __builtin_exit (0); +} diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c index 052d24dabdf..e2914a8333c 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-1.c @@ -14,7 +14,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "jmp\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c index 2cfbd728b4b..d2b7c74b143 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-2.c @@ -14,7 +14,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "jmp\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c index 59bb08613b7..129fb2125f0 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-3.c @@ -15,7 +15,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c index 59640fab8f1..01996fb029f 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-4.c @@ -15,7 +15,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c index 8620bf1d836..1493e18243b 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-1.c @@ -17,7 +17,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "jmp\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c index 42e83416965..3ddd4980b69 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-2.c @@ -15,7 +15,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "jmp\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c index 6a9c51337d9..43d5f95b4fb 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-3.c @@ -17,7 +17,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler-times {jmp[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler-times {call[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler {\tpause} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c index 85ec57b5a8d..bf62636c63c 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-4.c @@ -16,7 +16,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler-times {jmp[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler-times {call[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler {\tpause} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c index db1d8fb9979..27ba82932e4 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-5.c @@ -17,7 +17,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */ /* { dg-final { scan-assembler-not {jmp[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c index 24fc43b3ba5..bdf15d36bac 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-attr-6.c @@ -16,7 +16,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */ /* { dg-final { scan-assembler-not {jmp[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c index 3dc02f80ff5..c30c331c23b 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-1.c @@ -14,7 +14,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "jmp\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */ /* { dg-final { scan-assembler-not {jmp[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c index c4adae23dd3..7edd7313027 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-2.c @@ -14,7 +14,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "jmp\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */ /* { dg-final { scan-assembler-not {jmp[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c index b800b40b055..8e391797c5e 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-3.c @@ -15,7 +15,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */ /* { dg-final { scan-assembler-not {jmp[ \t]*\.?LIND} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c index f68902ddc25..6033d13e8a7 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-extern-4.c @@ -15,6 +15,6 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not {\t(lfence|pause)} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c index 7301490d49c..ef3577d2934 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-1.c @@ -14,7 +14,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {\tpause} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c index ef1ba02978d..f26a5fb9015 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-2.c @@ -14,7 +14,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler {jmp[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler {\tpause} } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c index 58de8f0393e..3b8a1eeaffb 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-3.c @@ -15,7 +15,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler-times {jmp[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler-times {call[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler-times {\tpause} 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c index 3be3ce07527..40d31803a2e 100644 --- a/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-inline-4.c @@ -15,7 +15,7 @@ male_indirect_jump (long offset) /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*dispatch" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_dispatch} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_dispatch\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler-times {jmp[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler-times {call[ \t]*\.?LIND} 2 } } */ /* { dg-final { scan-assembler-times {\tpause} 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr32219-2.c b/gcc/testsuite/gcc.target/i386/pr32219-2.c index cb587db47aa..b6212f7dd4c 100644 --- a/gcc/testsuite/gcc.target/i386/pr32219-2.c +++ b/gcc/testsuite/gcc.target/i386/pr32219-2.c @@ -20,5 +20,5 @@ foo () /* { dg-final { scan-assembler "movl\[ \t\]xxx@GOT\\(%\[^,\]*\\), %" { target { ia32 && { ! *-*-darwin* } } } } } */ /* Darwin m32 defaults to PIC but common symbols need to be indirected. */ -/* { dg-final { scan-assembler {movl[ \t]l_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t][Ll]_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr32219-3.c b/gcc/testsuite/gcc.target/i386/pr32219-3.c index f9cfca7d72c..a1b0df28d0d 100644 --- a/gcc/testsuite/gcc.target/i386/pr32219-3.c +++ b/gcc/testsuite/gcc.target/i386/pr32219-3.c @@ -24,4 +24,4 @@ foo () /* For Darwin, we need PIC to allow PIE, but also we must indirect weak symbols so that they can be indirected. Again, dyld knows how to deal with this. */ -/* { dg-final { scan-assembler {movl[ \t]l_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t][Ll]_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr32219-4.c b/gcc/testsuite/gcc.target/i386/pr32219-4.c index 0ac0674ae17..31d0710b7ed 100644 --- a/gcc/testsuite/gcc.target/i386/pr32219-4.c +++ b/gcc/testsuite/gcc.target/i386/pr32219-4.c @@ -21,4 +21,4 @@ foo () /* { dg-final { scan-assembler "movl\[ \t\]xxx@GOT\\(%\[^,\]*\\), %" { target { ia32 && { ! *-*-darwin* } } } } } */ /* Darwin m32 equivalent (indirect and PIC). */ -/* { dg-final { scan-assembler {movl[ \t]l_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t][Ll]_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr32219-7.c b/gcc/testsuite/gcc.target/i386/pr32219-7.c index 469e9e38b07..20fef8dd063 100644 --- a/gcc/testsuite/gcc.target/i386/pr32219-7.c +++ b/gcc/testsuite/gcc.target/i386/pr32219-7.c @@ -23,4 +23,4 @@ foo () /* { dg-final { scan-assembler-not "movl\[ \t\]xxx@GOT\\(%\[^,\]*\\), %eax" { target { ia32 && { ! *-*-darwin* } } } } } */ /* Darwin m32 equivalent (indirect and PIC). */ -/* { dg-final { scan-assembler {movl[ \t]l_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t][Ll]_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr32219-8.c b/gcc/testsuite/gcc.target/i386/pr32219-8.c index 75eb287fc59..767928f049e 100644 --- a/gcc/testsuite/gcc.target/i386/pr32219-8.c +++ b/gcc/testsuite/gcc.target/i386/pr32219-8.c @@ -21,4 +21,4 @@ foo () /* { dg-final { scan-assembler "movl\[ \t\]xxx@GOT\\(%\[^,\]*\\), %" { target { ia32 && { ! *-*-darwin* } } } } } */ /* Darwin m32 default to PIC but needs indirection for the weak symbol. */ -/* { dg-final { scan-assembler {movl[ \t]l_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t][Ll]_xxx\$non_lazy_ptr-L1\$pb\(%eax\),[ \t]%eax} { target { ia32 && *-*-darwin* } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr87853.c b/gcc/testsuite/gcc.target/i386/pr87853.c new file mode 100644 index 00000000000..9a288879679 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr87853.c @@ -0,0 +1,20 @@ +/* PR target/87853 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -funsigned-char -msse2 -mno-sse3 -masm=att" } */ +/* { dg-final { scan-assembler-times "\tpcmpgtb\t%xmm" 2 } } */ +/* { dg-final { scan-assembler-not "\tpsubusb\t" } } */ +/* { dg-final { scan-assembler-not "\tpcmpeqb\t" } } */ + +#include <x86intrin.h> + +__m128i +foo (__m128i x, __m128i y) +{ + return _mm_cmpgt_epi8 (x, y); +} + +__m128i +bar (__m128i x, __m128i y) +{ + return _mm_cmplt_epi8 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/pr90867.c b/gcc/testsuite/gcc.target/i386/pr90867.c new file mode 100644 index 00000000000..1ed96b582ed --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90867.c @@ -0,0 +1,30 @@ +/* PR target/90867 */ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -msse2" } */ + +unsigned long long freq = 3600000000UL; /* 3.6 GHz = 3600.0 MHz */ + +__attribute__((noipa)) void +bar (double x) +{ + static double d = 3600000000.0; + if (x != d) + __builtin_abort (); + d /= 1000.0; +} + +__attribute__ ((target ("arch=x86-64"))) int +foo () +{ + bar ((double) freq); + bar (1e-3 * freq); + bar (1e-6 * freq); + bar (1e-9 * freq); + return 0; +} + +int +main () +{ + return foo (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr91623.c b/gcc/testsuite/gcc.target/i386/pr91623.c new file mode 100644 index 00000000000..94de4f91c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr91623.c @@ -0,0 +1,32 @@ +/* PR middle-end/91623 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse4.1 -mno-sse4.2" } */ + +typedef long long V __attribute__((__vector_size__(16))); +V e, h; +int d; +const int i; + +void foo (void); + +void +bar (int k, int l) +{ + if (d && 0 <= k - 1 && l) + foo (); +} + +void +baz (void) +{ + V n = (V) { 1 }; + V g = (V) {}; + V o = g; + for (int f = 0; f < i; ++f) + { + V a = o == n; + h = a; + bar (f, i); + o = e; + } +} diff --git a/gcc/testsuite/gcc.target/i386/pr91704.c b/gcc/testsuite/gcc.target/i386/pr91704.c new file mode 100644 index 00000000000..b996e24ad74 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr91704.c @@ -0,0 +1,14 @@ +/* PR target/91704 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -funsigned-char -mavx2 -mavx512f -masm=att" } */ +/* { dg-final { scan-assembler-times "\tvpcmpgtb\t%ymm" 1 } } */ +/* { dg-final { scan-assembler-not "\tvpsubusb\t" } } */ +/* { dg-final { scan-assembler-not "\tvpcmpeqb\t" } } */ + +#include <x86intrin.h> + +__m256i +foo (__m256i x, __m256i y) +{ + return _mm256_cmpgt_epi8 (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/pr92225.c b/gcc/testsuite/gcc.target/i386/pr92225.c new file mode 100644 index 00000000000..b1232195b45 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92225.c @@ -0,0 +1,19 @@ +/* PR target/92225 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -msse2 -mno-sse4" } */ + +void a (long); + +unsigned *b; + +void +c () +{ + long d = 2; + int e = 0; + + for (; e < 1024; e++) + if (b[e] > d) + d = b[e]; + a (d); +} diff --git a/gcc/testsuite/gcc.target/i386/ret-thunk-14.c b/gcc/testsuite/gcc.target/i386/ret-thunk-14.c index 3eaddee8c34..881f541772c 100644 --- a/gcc/testsuite/gcc.target/i386/ret-thunk-14.c +++ b/gcc/testsuite/gcc.target/i386/ret-thunk-14.c @@ -19,6 +19,6 @@ foo (void) /* { dg-final { scan-assembler {call[ \t]*\.?LIND} } } */ /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*bar" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_bar} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_bar\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_bar\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ret-thunk-15.c b/gcc/testsuite/gcc.target/i386/ret-thunk-15.c index 2793f72cdc1..5687440bf31 100644 --- a/gcc/testsuite/gcc.target/i386/ret-thunk-15.c +++ b/gcc/testsuite/gcc.target/i386/ret-thunk-15.c @@ -19,6 +19,6 @@ foo (void) /* { dg-final { scan-assembler-times {\tlfence} 1 } } */ /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*bar" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_bar} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_bar\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_bar\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ /* { dg-final { scan-assembler-not "pushq\[ \t\]%rax" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ret-thunk-9.c b/gcc/testsuite/gcc.target/i386/ret-thunk-9.c index 63af6741e05..3d4497000dc 100644 --- a/gcc/testsuite/gcc.target/i386/ret-thunk-9.c +++ b/gcc/testsuite/gcc.target/i386/ret-thunk-9.c @@ -17,7 +17,7 @@ foo (void) /* { dg-final { scan-assembler "_?__x86_return_thunk:" } } */ /* { dg-final { scan-assembler "mov(?:l|q)\[ \t\]*bar" { target *-*-linux* } } } */ /* { dg-final { scan-assembler {movq[ \t]*_bar} { target { lp64 && *-*-darwin* } } } } */ -/* { dg-final { scan-assembler {movl[ \t]*l_bar\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ +/* { dg-final { scan-assembler {movl[ \t]*[Ll]_bar\$non_lazy_ptr-L[0-9]+\$pb} { target { ia32 && *-*-darwin* } } } } */ /* { dg-final { scan-assembler-times {\tpause} 2 } } */ /* { dg-final { scan-assembler-times {\tlfence} 2 } } */ /* { dg-final { scan-assembler "call\[ \t\]*_?__x86_indirect_thunk_(r|e)ax" } } */ diff --git a/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c new file mode 100644 index 00000000000..24c18262b1a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mabicalls -fpic -mno-mips16 -mno-micromips" } */ +/* { dg-skip-if "needs codesize optimization" { *-*-* } { "-O0" "-O1" "-O2" "-O3" } { "" } } */ + +extern void foo (void*); + +extern void bar (void*); + +void +test (void* p) +{ + if (!p) + foo(p); + else + bar(p); +} + +/* { dg-final { scan-assembler-not "\\\.reloc\t1f,R_MIPS_JALR,foo" } } */ +/* { dg-final { scan-assembler-not "\\\.reloc\t1f,R_MIPS_JALR,bar" } } */ diff --git a/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c new file mode 100644 index 00000000000..9fd75c98773 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mabicalls -fpic -mno-mips16 -mno-micromips" } */ +/* { dg-additional-options "-fno-inline -fipa-ra -mcompact-branches=never" } */ +/* { dg-skip-if "needs codesize optimization" { *-*-* } { "-O0" "-O1" "-O2" "-O3" } { "" } } */ + +static int foo (void* p) { __asm__ (""::"r"(p):"$t0"); return 0; } + +static int bar (void* p) { return 1; } + +int +test (void* p) +{ + int res = !p ? foo(p) : bar(p); + + register int tmp __asm__("$t0") = -1; + __asm__ (""::"r"(tmp)); + + return res; +} + +/* { dg-final { scan-assembler "\\\.reloc\t1f,R_MIPS_JALR,foo" } } */ +/* { dg-final { scan-assembler "\\\.reloc\t1f,R_MIPS_JALR,bar" } } */ +/* { dg-final { scan-assembler-not "\\.set\tnomacro\n\tjalr\t\\\$25" } } */ diff --git a/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c new file mode 100644 index 00000000000..580c6ec069d --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/cfgcleanup-jalr3.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mabicalls -fpic -mno-mips16 -mno-micromips" } */ +/* { dg-additional-options "-fno-inline -fipa-ra -mcompact-branches=never" } */ +/* { dg-skip-if "needs codesize optimization" { *-*-* } { "-O0" "-O1" "-O2" "-O3" } { "" } } */ + +static int foo (void* p) { return 0; } + +static int bar (void* p) { return 1; } + +int +test (void* p) +{ + int res = !p ? foo(p) : bar(p); + + register int tmp __asm__("$t0") = -1; + __asm__ (""::"r"(tmp)); + + return res; +} + +/* { dg-final { scan-assembler-not "\\\.reloc\t1f,R_MIPS_JALR,foo" } } */ +/* { dg-final { scan-assembler-not "\\\.reloc\t1f,R_MIPS_JALR,bar" } } */ +/* { dg-final { scan-assembler "\\.set\tnomacro\n\tjalr\t\\\$25" } } */ diff --git a/gcc/testsuite/gcc.target/mips/pr91769.c b/gcc/testsuite/gcc.target/mips/pr91769.c new file mode 100644 index 00000000000..c9ad70d7f75 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr91769.c @@ -0,0 +1,19 @@ +/* PR target/91769 */ +/* { dg-do compile } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" "-g" } { "" } } */ +/* { dg-options "-EL -mgp32 -mhard-float" } */ + +NOCOMPRESSION double +foo (void) +{ + register double* pf __asm__ ("$a1"); + __asm__ __volatile__ ("":"=r"(pf)); + double f = *pf; + + if (f != f) + f = -f; + return f; +} + +/* { dg-final { scan-assembler-not "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tldc1\t\\\$.*,0\\(\\\$5\\)" } } */ +/* { dg-final { scan-assembler "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tmtc1\t\\\$4,\\\$.*\n\tmthc1\t\\\$5,\\\$.*" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/darn-3.c b/gcc/testsuite/gcc.target/powerpc/darn-3.c new file mode 100644 index 00000000000..477901fde70 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darn-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ + +static int darn32(void) { return __builtin_darn_32(); } + +int four(void) +{ + int sum = 0; + int i; + for (i = 0; i < 4; i++) + sum += darn32(); + return sum; +} + +/* { dg-final { scan-assembler-times {(?n)\mdarn .*,0\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr70010-1.c b/gcc/testsuite/gcc.target/powerpc/pr70010-1.c new file mode 100644 index 00000000000..4b3abb7d8fe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70010-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -flto -mvsx" } */ +/* { dg-require-effective-target lto } */ + +vector int c, a, b; + +static inline void __attribute__ ((__always_inline__, target ("no-vsx"))) +foo () /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ +{ + c = a + b; +} + +int +main () +{ + foo (); /* { dg-message "called from here" } */ + c = a + b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr70010-2.c b/gcc/testsuite/gcc.target/powerpc/pr70010-2.c new file mode 100644 index 00000000000..0c04c5390db --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70010-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -flto -mno-vsx" } */ +/* { dg-require-effective-target lto } */ + +vector int c, a, b; + +static inline void __attribute__ ((__always_inline__, target ("no-vsx"))) +foo () +{ + c = a + b; +} + +int +main () +{ + foo (); + c = a + b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr70010-3.c b/gcc/testsuite/gcc.target/powerpc/pr70010-3.c new file mode 100644 index 00000000000..bca31875632 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70010-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-vsx" } */ + +vector int c, a, b; + +static inline void __attribute__ ((__always_inline__, target ("no-vsx"))) +foo () +{ + c = a + b; +} + +int +main () +{ + foo (); + c = a + b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr70010-4.c b/gcc/testsuite/gcc.target/powerpc/pr70010-4.c new file mode 100644 index 00000000000..c575cff1b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70010-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mvsx" } */ + +vector int c, a, b; + +static inline void __attribute__ ((__always_inline__, target ("no-vsx"))) +foo () /* { dg-error "inlining failed in call to .* target specific option mismatch" } */ +{ + c = a + b; +} + +int +main () +{ + foo (); /* { dg-message "called from here" } */ + c = a + b; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr70010.c b/gcc/testsuite/gcc.target/powerpc/pr70010.c new file mode 100644 index 00000000000..679034fae43 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr70010.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -finline-functions -Wno-psabi -mvsx" } */ +/* { dg-final { scan-assembler {\mbl \.?vadd_no_vsx\M} } } */ + +typedef int vec_t __attribute__((vector_size(16))); + +static vec_t +__attribute__((__target__("no-vsx"))) +vadd_no_vsx (vec_t a, vec_t b) +{ + return a + b; +} + +vec_t +__attribute__((__target__("vsx"))) +call_vadd_no_vsx (vec_t x, vec_t y, vec_t z) +{ + return vadd_no_vsx (x, y) - z; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr91275.c b/gcc/testsuite/gcc.target/powerpc/pr91275.c new file mode 100644 index 00000000000..cd461158af7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr91275.c @@ -0,0 +1,26 @@ +/* Test that we generate vpmsumd correctly without a swap error. */ + +/* { dg-do run { target { p8vector_hw } } } */ +/* { dg-options "-O2 -std=gnu11" } */ + +#include <altivec.h> + +int main() { + + const unsigned long long r0l = 0x8e7dfceac070e3a0; + vector unsigned long long r0 = (vector unsigned long long) {r0l, 0}, v; + const vector unsigned long long pd + = (vector unsigned long long) {0xc2LLU << 56, 0}; + + v = __builtin_crypto_vpmsumd ((vector unsigned long long) {r0[0], 0}, pd); + +#if __LITTLE_ENDIAN__ + if (v[0] != 0x4000000000000000 || v[1] != 0x65bd7ab605a4a8ff) + __builtin_abort (); +#else + if (v[1] != 0x4000000000000000 || v[0] != 0x65bd7ab605a4a8ff) + __builtin_abort (); +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pure-builtin-redundant-load.c b/gcc/testsuite/gcc.target/powerpc/pure-builtin-redundant-load.c new file mode 100644 index 00000000000..16ab6abfc3b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pure-builtin-redundant-load.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -fdump-tree-fre-all -mvsx" } */ + +/* Verify we remove a redundant load that occurs both before and after +we call a vector load builtin. +This testcase is introduced as we updated a number of our vector load +built-ins with the attribute of PURE instead of MEM, to indicate that +those builtins only read from memory, versus reading from and writing +to the same. +This means we can identify the redundant load instructions in an earlier +pass, and optimize them away. */ + +#include <altivec.h> + +vector signed short load_data; + +vector signed short foo() +{ + vector signed short r11,r12,r13; + r11 = load_data; + r12 = vec_xl (0, &load_data[0]); + r13 = load_data; + return (r11 + r12 + r13); +} + +vector signed short biz() +{ + vector signed short r21,r22,r23; + r21 = load_data; + r22 = vec_lvehx (0, &load_data[0]); + r23 = load_data; + return (r21 + r22 + r23); +} + +vector signed short bar() +{ + vector signed short r31,r32,r33; + r31 = load_data; + r32 = vec_lvx (0, &load_data[0]); + r33 = load_data; + return (r31 + r32 + r33); +} + +/* { dg-final { scan-tree-dump-times "Removing dead stmt r13_. = load_data;" 1 "fre1" } } */ +/* { dg-final { scan-tree-dump-times "Removing dead stmt r23_. = load_data;" 1 "fre1" } } */ +/* { dg-final { scan-tree-dump-times "Removing dead stmt r33_. = load_data;" 1 "fre1" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c new file mode 100644 index 00000000000..72a45ee87ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i -mabi=ilp32 -O2" } */ + +/* One zero-extend shift can be eliminated by modifying the constant in the + greater than test. Started working after modifying the splitter + lshrsi3_zero_extend_3+1 to use a temporary reg for the first split dest. */ +int +sub (int i) +{ + i &= 0x7fffffff; + return i > 0x7f800000; +} +/* { dg-final { scan-assembler-not "srli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c new file mode 100644 index 00000000000..5b2ae89a471 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */ + +/* Fails if lshrsi3_zero_extend_3+1 uses a temp reg which has no REG_DEST + note. */ +unsigned long +sub (long l) +{ + union u { + struct s { int a : 19; unsigned int b : 13; int x; } s; + long l; + } u; + u.l = l; + return u.s.b; +} +/* { dg-final { scan-assembler "srliw" } } */ diff --git a/gcc/testsuite/gcc.target/s390/s390.exp b/gcc/testsuite/gcc.target/s390/s390.exp index 86f7e4398eb..ee94a806766 100644 --- a/gcc/testsuite/gcc.target/s390/s390.exp +++ b/gcc/testsuite/gcc.target/s390/s390.exp @@ -86,18 +86,22 @@ proc check_effective_target_s390_useable_hw { } { int main (void) { asm (".machinemode zarch" : : ); - #if __ARCH__ >= 11 - asm ("lcbb %%r2,0(%%r15),0" : : ); + #if __ARCH__ >= 13 + asm ("ncrk %%r2,%%r2,%%r2" : : : "r2"); + #elif __ARCH__ >= 12 + asm ("agh %%r2,0(%%r15)" : : : "r2"); + #elif __ARCH__ >= 11 + asm ("lochiz %%r2,42" : : : "r2"); #elif __ARCH__ >= 10 - asm ("risbgn %%r2,%%r2,0,0,0" : : ); + asm ("risbgn %%r2,%%r2,0,0,0" : : : "r2"); #elif __ARCH__ >= 9 - asm ("sgrk %%r2,%%r2,%%r2" : : ); + asm ("sgrk %%r2,%%r2,%%r2" : : : "r2"); #elif __ARCH__ >= 8 - asm ("rosbg %%r2,%%r2,0,0,0" : : ); + asm ("rosbg %%r2,%%r2,0,0,0" : : : "r2"); #elif __ARCH__ >= 7 - asm ("nilf %%r2,0" : : ); + asm ("nilf %%r2,0" : : : "r2"); #elif __ARCH__ >= 6 - asm ("lay %%r2,0(%%r15)" : : ); + asm ("lay %%r2,0(%%r15)" : : : "r2"); #elif __ARCH__ >= 5 asm ("tam" : : ); #endif @@ -107,8 +111,8 @@ proc check_effective_target_s390_useable_hw { } { asm ("etnd %0" : "=d" (nd)); } #endif - #ifdef __VX__ - asm ("vzero %%v0" : : ); + #if defined (__VX__) && defined (__zarch__) + asm ("vzero %%v0" : : : "v0"); #endif return 0; } diff --git a/gcc/testsuite/gcc.target/s390/sigfpe-eh.c b/gcc/testsuite/gcc.target/s390/sigfpe-eh.c new file mode 100644 index 00000000000..52b0bf39d9e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/sigfpe-eh.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=z196 -O2 -fexceptions -fnon-call-exceptions" } */ + +extern float f (void); +extern float g (void); + +float h (float x, float y) +{ + return x < y ? f () : g (); +} diff --git a/gcc/testsuite/gcc.target/sparc/20161111-1.c b/gcc/testsuite/gcc.target/sparc/20161111-1.c index eda8b0a9f12..8195fec8990 100644 --- a/gcc/testsuite/gcc.target/sparc/20161111-1.c +++ b/gcc/testsuite/gcc.target/sparc/20161111-1.c @@ -14,4 +14,4 @@ unsigned char ee_isdigit2(unsigned int i) return retval; } -/* { dg-final { scan-assembler-not "and\t%" } } */ +/* { dg-final { scan-assembler-not "and\t%" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/sparc/overflow-1.c b/gcc/testsuite/gcc.target/sparc/overflow-1.c index e3fa0d04573..75f69ba4f9d 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-1.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O -mcpu=v8" } */ +/* { dg-options "-O -fno-pie -mcpu=v8" } */ /* { dg-require-effective-target ilp32 } */ #include <stdbool.h> diff --git a/gcc/testsuite/gcc.target/sparc/overflow-2.c b/gcc/testsuite/gcc.target/sparc/overflow-2.c index 9e42bd214de..feb3f194828 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-2.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O -mcpu=v8" } */ +/* { dg-options "-O -fno-pie -mcpu=v8" } */ /* { dg-require-effective-target ilp32 } */ #include <stdbool.h> diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c index 86dddfb09e6..52d6ab2b688 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-3.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-O" } */ +/* { dg-options "-O -fno-pie" } */ #include <stdbool.h> #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c index 019feee335c..c6121b958c3 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-4.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-O -mno-vis3 -mno-vis4" } */ +/* { dg-options "-O -fno-pie -mno-vis3 -mno-vis4" } */ #include <stdbool.h> #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c index 67d4ac38095..f00283f6e7b 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-5.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-O -mvis3" } */ +/* { dg-options "-O -fno-pie -mvis3" } */ #include <stdbool.h> #include <stdint.h> |