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author | Peter Maydell <peter.maydell@linaro.org> | 2022-12-16 14:22:10 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2022-12-16 14:22:10 +0000 |
commit | d407570557649d5f66f425ee3fa53f9c9331250f (patch) | |
tree | df98858493d7bbfaf5414e6522f4305b228ce459 | |
parent | a0cd0b1d0bc78b8ffe3292fbb4f14e4a15e16b7b (diff) |
test9: Correct expected SYST_CSR value
In QEMU commit a40e10f1dc3e0fedd we fixed a bug in our systick timer
implementation where we always implemented a 1MHz reference clock,
whether the board had a reference clock or not. For the Stellaris
board which we run these test cases on, there is no reference clock;
the reset value of SYST_CSR has therefore changed to its correct
value of 4 (with the CLKSOURCE bit set to indicate that the systick
clock is running on the CPU clock).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | test9.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -59,7 +59,7 @@ void main(void) TEST(shpr[1], 0); TEST(shpr[2], 0); TEST(shcsr, 0); - TEST(syst_csr, 0); + TEST(syst_csr, 4); puts("# ictr "); puthex(early_state.ictr); putc('\n'); |