[ARM][v8.5A] Add speculation barriers SSBB and PSSBB

This adds two new barrier instructions which can be used to restrict
speculative execution of load instructions.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52484

12 files changed, 109 insertions, 23 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index e063ffdc36b..e1a077ef166 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -5926,6 +5926,8 @@ include "ARMInstrNEON.td"
 // Memory barriers
 def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
 def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
+def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>;
+def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>;
 def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
 // Armv8-R 'Data Full Barrier'
 def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 39525a3e28f..0c5720e0267 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -4554,6 +4554,12 @@ def : t2InstAlias<"tst${p} $Rn, $Rm",
 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
+
+// Non-predicable aliases of a predicable DSB: the predicate is (14, 0) where
+// 14 = AL (always execute) and 0 = "instruction doesn't read the CPSR".
+def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
+def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
+
 // Armv8-R 'Data Full Barrier'
 def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
 
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index c5b2d2d5968..f837db56264 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5721,7 +5721,8 @@ void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
-      Mnemonic == "sb") {
+      Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
+      Mnemonic == "pssbb") {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
@@ -6824,6 +6825,26 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
                                                "code specified");
     break;
   }
+  case ARM::DSB:
+  case ARM::t2DSB: {
+
+    if (Inst.getNumOperands() < 2)
+      break;
+
+    unsigned Option = Inst.getOperand(0).getImm();
+    unsigned Pred = Inst.getOperand(1).getImm();
+
+    // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
+    if (Option == 0 && Pred != ARMCC::AL)
+      return Error(Operands[1]->getStartLoc(),
+                   "instruction 'ssbb' is not predicable, but condition code "
+                   "specified");
+    if (Option == 4 && Pred != ARMCC::AL)
+      return Error(Operands[1]->getStartLoc(),
+                   "instruction 'pssbb' is not predicable, but condition code "
+                   "specified");
+    break;
+  }
   case ARM::VMOVRRS: {
     // Source registers must be sequential.
     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index bfc32073ba1..2f84719c4c4 100644
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -273,6 +273,21 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
   case ARM::t2TSB:
     O << "\ttsb\tcsync";
     return;
+  case ARM::t2DSB:
+    switch (MI->getOperand(0).getImm()) {
+    default:
+      if (!printAliasInstr(MI, STI, O))
+        printInstruction(MI, STI, O);
+      break;
+    case 0:
+      O << "\tssbb";
+      break;
+    case 4:
+      O << "\tpssbb";
+      break;
+    }
+    printAnnotation(O, Annot);
+    return;
   }
 
   if (!printAliasInstr(MI, STI, O))
diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s
index d4d79364b3d..e58f2926c20 100644
--- a/llvm/test/MC/ARM/basic-arm-instructions.s
+++ b/llvm/test/MC/ARM/basic-arm-instructions.s
@@ -926,11 +926,11 @@ Lforward:
 @ CHECK: dsb	nsh                     @ encoding: [0x47,0xf0,0x7f,0xf5]
 @ CHECK: dsb	nshst                   @ encoding: [0x46,0xf0,0x7f,0xf5]
 @ CHECK: dsb	#0x5                    @ encoding: [0x45,0xf0,0x7f,0xf5]
-@ CHECK: dsb	#0x4                    @ encoding: [0x44,0xf0,0x7f,0xf5]
+@ CHECK: pssbb                          @ encoding: [0x44,0xf0,0x7f,0xf5]
 @ CHECK: dsb	osh                     @ encoding: [0x43,0xf0,0x7f,0xf5]
 @ CHECK: dsb	oshst                   @ encoding: [0x42,0xf0,0x7f,0xf5]
 @ CHECK: dsb	#0x1                    @ encoding: [0x41,0xf0,0x7f,0xf5]
-@ CHECK: dsb	#0x0                    @ encoding: [0x40,0xf0,0x7f,0xf5]
+@ CHECK: ssbb                           @ encoding: [0x40,0xf0,0x7f,0xf5]
 
 @ CHECK: dsb	#0x8                    @ encoding: [0x48,0xf0,0x7f,0xf5]
 @ CHECK: dsb	nsh                     @ encoding: [0x47,0xf0,0x7f,0xf5]
diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s
index 6f81f00350d..4226b8092cf 100644
--- a/llvm/test/MC/ARM/basic-thumb2-instructions.s
+++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s
@@ -657,11 +657,11 @@ _func:
 @ CHECK: dsb	nsh                     @ encoding: [0xbf,0xf3,0x47,0x8f]
 @ CHECK: dsb	nshst                   @ encoding: [0xbf,0xf3,0x46,0x8f]
 @ CHECK: dsb	#0x5                    @ encoding: [0xbf,0xf3,0x45,0x8f]
-@ CHECK: dsb	#0x4                    @ encoding: [0xbf,0xf3,0x44,0x8f]
+@ CHECK: pssbb                          @ encoding: [0xbf,0xf3,0x44,0x8f]
 @ CHECK: dsb	osh                     @ encoding: [0xbf,0xf3,0x43,0x8f]
 @ CHECK: dsb	oshst                   @ encoding: [0xbf,0xf3,0x42,0x8f]
 @ CHECK: dsb	#0x1                    @ encoding: [0xbf,0xf3,0x41,0x8f]
-@ CHECK: dsb	#0x0                    @ encoding: [0xbf,0xf3,0x40,0x8f]
+@ CHECK: ssbb                           @ encoding: [0xbf,0xf3,0x40,0x8f]
 
 @ CHECK: dsb	sy                      @ encoding: [0xbf,0xf3,0x4f,0x8f]
 @ CHECK: dsb	st                      @ encoding: [0xbf,0xf3,0x4e,0x8f]
diff --git a/llvm/test/MC/ARM/csdb-errors.s b/llvm/test/MC/ARM/csdb-errors.s
deleted file mode 100644
index af74a46b27c..00000000000
--- a/llvm/test/MC/ARM/csdb-errors.s
+++ /dev/null
@@ -1,6 +0,0 @@
-// RUN: not llvm-mc -triple   armv8a-none-eabi %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple thumbv8a-none-eabi %s 2>&1 | FileCheck %s
-
-  it eq
-  csdbeq
-// CHECK: error: instruction 'csdb' is not predicable, but condition code specified
diff --git a/llvm/test/MC/ARM/csdb.s b/llvm/test/MC/ARM/csdb.s
deleted file mode 100644
index 4d78be40fa0..00000000000
--- a/llvm/test/MC/ARM/csdb.s
+++ /dev/null
@@ -1,8 +0,0 @@
-@ RUN:     llvm-mc -triple   armv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=ARM
-@ RUN:     llvm-mc -triple thumbv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=THUMB
-@ RUN: not llvm-mc -triple thumbv6m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-
-  csdb
-@ ARM:   csdb   @ encoding: [0x14,0xf0,0x20,0xe3]
-@ THUMB: csdb   @ encoding: [0xaf,0xf3,0x14,0x80]
-@ ERROR: error: instruction requires: thumb2
diff --git a/llvm/test/MC/ARM/speculation-barriers-errors.s b/llvm/test/MC/ARM/speculation-barriers-errors.s
new file mode 100644
index 00000000000..9ef89d4af9a
--- /dev/null
+++ b/llvm/test/MC/ARM/speculation-barriers-errors.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple   armv8a-none-eabi %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple thumbv8a-none-eabi %s 2>&1 | FileCheck %s -check-prefix=THUMB
+
+  it eq
+  csdbeq
+
+  it eq
+  ssbbeq
+
+  it eq
+  pssbbeq
+
+  it eq
+  hinteq #20
+
+  it eq
+  dsbeq #0
+
+  it eq
+  dsbeq #4
+
+// CHECK: error: instruction 'csdb' is not predicable, but condition code specified
+// CHECK: error: instruction 'ssbb' is not predicable, but condition code specified
+// CHECK: error: instruction 'pssbb' is not predicable, but condition code specified
+// CHECK: error: instruction 'csdb' is not predicable, but condition code specified
+// CHECK: error: instruction 'dsb' is not predicable, but condition code specified
+// CHECK: error: instruction 'dsb' is not predicable, but condition code specified
+
+// THUMB: error: instruction 'csdb' is not predicable, but condition code specified
+// THUMB: error: instruction 'ssbb' is not predicable, but condition code specified
+// THUMB: error: instruction 'pssbb' is not predicable, but condition code specified
+// THUMB: error: instruction 'csdb' is not predicable, but condition code specified
+// THUMB: error: instruction 'ssbb' is not predicable, but condition code specified
+// THUMB: error: instruction 'pssbb' is not predicable, but condition code specified
diff --git a/llvm/test/MC/ARM/speculation-barriers.s b/llvm/test/MC/ARM/speculation-barriers.s
new file mode 100644
index 00000000000..c9d143ab44f
--- /dev/null
+++ b/llvm/test/MC/ARM/speculation-barriers.s
@@ -0,0 +1,22 @@
+@ RUN:     llvm-mc -triple   armv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=ARM
+@ RUN:     llvm-mc -triple thumbv8a-none-eabi -show-encoding %s      | FileCheck %s --check-prefix=THUMB
+@ RUN: not llvm-mc -triple thumbv6m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+csdb
+ssbb
+pssbb
+
+@ ARM:   csdb   @ encoding: [0x14,0xf0,0x20,0xe3]
+@ ARM:   ssbb   @ encoding: [0x40,0xf0,0x7f,0xf5]
+@ ARM:   pssbb  @ encoding: [0x44,0xf0,0x7f,0xf5]
+
+@ THUMB: csdb   @ encoding: [0xaf,0xf3,0x14,0x80]
+@ THUMB: ssbb   @ encoding: [0xbf,0xf3,0x40,0x8f]
+@ THUMB: pssbb  @ encoding: [0xbf,0xf3,0x44,0x8f]
+
+@ ERROR:      error: instruction requires: thumb2
+@ ERROR-NEXT: csdb
+@ ERROR:      error: instruction requires: thumb2
+@ ERROR-NEXT: ssbb
+@ ERROR:      error: instruction requires: thumb2
+@ ERROR-NEXT: pssbb
diff --git a/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
index 335e69fe241..dc2247a1e36 100644
--- a/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
+++ b/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
@@ -553,11 +553,11 @@
 # DSB
 #------------------------------------------------------------------------------
 
-# CHECK: dsb	#0x0
+# CHECK: ssbb
 # CHECK: dsb	#0x1
 # CHECK: dsb	oshst
 # CHECK: dsb	osh
-# CHECK: dsb	#0x4
+# CHECK: pssbb
 # CHECK: dsb	#0x5
 # CHECK: dsb	nshst
 # CHECK: dsb	nsh
diff --git a/llvm/test/MC/Disassembler/ARM/thumb2.txt b/llvm/test/MC/Disassembler/ARM/thumb2.txt
index c8b40803133..986dbd52c2e 100644
--- a/llvm/test/MC/Disassembler/ARM/thumb2.txt
+++ b/llvm/test/MC/Disassembler/ARM/thumb2.txt
@@ -401,11 +401,11 @@
 #CHECK: dsb nsh
 #CHECK: dsb nshst
 #CHECK: dsb #0x5
-#CHECK: dsb #0x4
+#CHECK: pssbb
 #CHECK: dsb osh
 #CHECK: dsb oshst
 #CHECK: dsb #0x1
-#CHECK: dsb #0x0
+#CHECK: ssbb
 
 0xbf 0xf3 0x4f 0x8f
 0xbf 0xf3 0x4e 0x8f