diff options
author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-09-28 10:47:24 +0000 |
---|---|---|
committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-09-28 10:47:24 +0000 |
commit | 93dbd2e1f5c496f796e63d4c0a763e623cf6a6c7 (patch) | |
tree | 9f48b5073b3622d33ea7628d9981fea185b5f34c | |
parent | f2d8a19382725aa039812551d79e65b89b385e87 (diff) |
[llvm-mca] Remove redundant namespace prefixes. NFClinaro-local/ci/llvm-kernel-armv8l-testedlinaro-local/ci/llvm-kernel-armv8l-goodlinaro-local/ci/llvm-kernel-aarch64-testedlinaro-local/ci/llvm-kernel-aarch64-good
We are already "using" namespace llvm in all the files modified by this change.
-rw-r--r-- | llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp | 6 | ||||
-rw-r--r-- | llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp | 12 | ||||
-rw-r--r-- | llvm/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp | 2 | ||||
-rw-r--r-- | llvm/tools/llvm-mca/lib/InstrBuilder.cpp | 21 | ||||
-rw-r--r-- | llvm/tools/llvm-mca/lib/Instruction.cpp | 4 | ||||
-rw-r--r-- | llvm/tools/llvm-mca/lib/Pipeline.cpp | 12 | ||||
-rw-r--r-- | llvm/tools/llvm-mca/lib/Stages/DispatchStage.cpp | 10 | ||||
-rw-r--r-- | llvm/tools/llvm-mca/lib/Stages/ExecuteStage.cpp | 6 |
8 files changed, 36 insertions, 37 deletions
diff --git a/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp b/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp index 20db2b83036..eae160c6ffd 100644 --- a/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp +++ b/llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp @@ -24,8 +24,8 @@ using namespace llvm; namespace mca { -RegisterFile::RegisterFile(const llvm::MCSchedModel &SM, - const llvm::MCRegisterInfo &mri, unsigned NumRegs) +RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, + unsigned NumRegs) : MRI(mri), RegisterMappings(mri.getNumRegs(), {WriteRef(), RegisterRenamingInfo()}), ZeroRegisters(mri.getNumRegs(), false) { @@ -281,7 +281,7 @@ void RegisterFile::collectWrites(SmallVectorImpl<WriteRef> &Writes, } // Remove duplicate entries and resize the input vector. - llvm::sort(Writes, [](const WriteRef &Lhs, const WriteRef &Rhs) { + sort(Writes, [](const WriteRef &Lhs, const WriteRef &Rhs) { return Lhs.getWriteState() < Rhs.getWriteState(); }); auto It = std::unique(Writes.begin(), Writes.end()); diff --git a/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp b/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp index b3dcfa7b498..46a374c2102 100644 --- a/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp +++ b/llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp @@ -35,10 +35,10 @@ void DefaultResourceStrategy::skipMask(uint64_t Mask) { uint64_t DefaultResourceStrategy::select(uint64_t ReadyMask) { // This method assumes that ReadyMask cannot be zero. - uint64_t CandidateMask = llvm::PowerOf2Floor(NextInSequenceMask); + uint64_t CandidateMask = PowerOf2Floor(NextInSequenceMask); while (!(ReadyMask & CandidateMask)) { skipMask(CandidateMask); - CandidateMask = llvm::PowerOf2Floor(NextInSequenceMask); + CandidateMask = PowerOf2Floor(NextInSequenceMask); } return CandidateMask; } @@ -55,8 +55,8 @@ ResourceState::ResourceState(const MCProcResourceDesc &Desc, unsigned Index, uint64_t Mask) : ProcResourceDescIndex(Index), ResourceMask(Mask), BufferSize(Desc.BufferSize) { - if (llvm::countPopulation(ResourceMask) > 1) - ResourceSizeMask = ResourceMask ^ llvm::PowerOf2Floor(ResourceMask); + if (countPopulation(ResourceMask) > 1) + ResourceSizeMask = ResourceMask ^ PowerOf2Floor(ResourceMask); else ResourceSizeMask = (1ULL << Desc.NumUnits) - 1; ReadyMask = ResourceSizeMask; @@ -66,7 +66,7 @@ ResourceState::ResourceState(const MCProcResourceDesc &Desc, unsigned Index, bool ResourceState::isReady(unsigned NumUnits) const { return (!isReserved() || isADispatchHazard()) && - llvm::countPopulation(ReadyMask) >= NumUnits; + countPopulation(ReadyMask) >= NumUnits; } ResourceStateEvent ResourceState::isBufferAvailable() const { @@ -87,7 +87,7 @@ void ResourceState::dump() const { #endif static unsigned getResourceStateIndex(uint64_t Mask) { - return std::numeric_limits<uint64_t>::digits - llvm::countLeadingZeros(Mask); + return std::numeric_limits<uint64_t>::digits - countLeadingZeros(Mask); } static std::unique_ptr<ResourceStrategy> diff --git a/llvm/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp b/llvm/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp index 205fe84a709..ca3cc8cfafb 100644 --- a/llvm/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp +++ b/llvm/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp @@ -21,7 +21,7 @@ using namespace llvm; namespace mca { -RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM) +RetireControlUnit::RetireControlUnit(const MCSchedModel &SM) : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0), AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) { // Check if the scheduling model provides extra information about the machine diff --git a/llvm/tools/llvm-mca/lib/InstrBuilder.cpp b/llvm/tools/llvm-mca/lib/InstrBuilder.cpp index 4ada7df1e11..5195ef2fe95 100644 --- a/llvm/tools/llvm-mca/lib/InstrBuilder.cpp +++ b/llvm/tools/llvm-mca/lib/InstrBuilder.cpp @@ -64,16 +64,15 @@ static void initializeUsedResources(InstrDesc &ID, // Sort elements by mask popcount, so that we prioritize resource units over // resource groups, and smaller groups over larger groups. - llvm::sort(Worklist, - [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) { - unsigned popcntA = countPopulation(A.first); - unsigned popcntB = countPopulation(B.first); - if (popcntA < popcntB) - return true; - if (popcntA > popcntB) - return false; - return A.first < B.first; - }); + sort(Worklist, [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) { + unsigned popcntA = countPopulation(A.first); + unsigned popcntB = countPopulation(B.first); + if (popcntA < popcntB) + return true; + if (popcntA > popcntB) + return false; + return A.first < B.first; + }); uint64_t UsedResourceUnits = 0; @@ -351,7 +350,7 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI) { const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { std::string ToString; - llvm::raw_string_ostream OS(ToString); + raw_string_ostream OS(ToString); WithColor::error() << "found an unsupported instruction in the input" << " assembly sequence.\n"; MCIP.printInst(&MCI, OS, "", STI); diff --git a/llvm/tools/llvm-mca/lib/Instruction.cpp b/llvm/tools/llvm-mca/lib/Instruction.cpp index 0c847670557..7acb31665e5 100644 --- a/llvm/tools/llvm-mca/lib/Instruction.cpp +++ b/llvm/tools/llvm-mca/lib/Instruction.cpp @@ -133,7 +133,7 @@ void Instruction::execute() { void Instruction::update() { assert(isDispatched() && "Unexpected instruction stage found!"); - if (!llvm::all_of(Uses, [](const UniqueUse &Use) { return Use->isReady(); })) + if (!all_of(Uses, [](const UniqueUse &Use) { return Use->isReady(); })) return; // A partial register write cannot complete before a dependent write. @@ -147,7 +147,7 @@ void Instruction::update() { return true; }; - if (llvm::all_of(Defs, IsDefReady)) + if (all_of(Defs, IsDefReady)) Stage = IS_READY; } diff --git a/llvm/tools/llvm-mca/lib/Pipeline.cpp b/llvm/tools/llvm-mca/lib/Pipeline.cpp index 28696cae9aa..2d9aa6b2a31 100644 --- a/llvm/tools/llvm-mca/lib/Pipeline.cpp +++ b/llvm/tools/llvm-mca/lib/Pipeline.cpp @@ -31,26 +31,26 @@ void Pipeline::addEventListener(HWEventListener *Listener) { } bool Pipeline::hasWorkToProcess() { - return llvm::any_of(Stages, [](const std::unique_ptr<Stage> &S) { + return any_of(Stages, [](const std::unique_ptr<Stage> &S) { return S->hasWorkToComplete(); }); } -llvm::Error Pipeline::run() { +Error Pipeline::run() { assert(!Stages.empty() && "Unexpected empty pipeline found!"); while (hasWorkToProcess()) { notifyCycleBegin(); - if (llvm::Error Err = runCycle()) + if (Error Err = runCycle()) return Err; notifyCycleEnd(); ++Cycles; } - return llvm::ErrorSuccess(); + return ErrorSuccess(); } -llvm::Error Pipeline::runCycle() { - llvm::Error Err = llvm::ErrorSuccess(); +Error Pipeline::runCycle() { + Error Err = ErrorSuccess(); // Update stages before we start processing new instructions. for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) { const std::unique_ptr<Stage> &S = *I; diff --git a/llvm/tools/llvm-mca/lib/Stages/DispatchStage.cpp b/llvm/tools/llvm-mca/lib/Stages/DispatchStage.cpp index dc39a3a3aa5..13473f5928b 100644 --- a/llvm/tools/llvm-mca/lib/Stages/DispatchStage.cpp +++ b/llvm/tools/llvm-mca/lib/Stages/DispatchStage.cpp @@ -85,7 +85,7 @@ void DispatchStage::updateRAWDependencies(ReadState &RS, } } -llvm::Error DispatchStage::dispatch(InstRef IR) { +Error DispatchStage::dispatch(InstRef IR) { assert(!CarryOver && "Cannot dispatch another instruction!"); Instruction &IS = *IR.getInstruction(); const InstrDesc &Desc = IS.getDesc(); @@ -128,10 +128,10 @@ llvm::Error DispatchStage::dispatch(InstRef IR) { return moveToTheNextStage(IR); } -llvm::Error DispatchStage::cycleStart() { +Error DispatchStage::cycleStart() { if (!CarryOver) { AvailableEntries = DispatchWidth; - return llvm::ErrorSuccess(); + return ErrorSuccess(); } AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver; @@ -143,7 +143,7 @@ llvm::Error DispatchStage::cycleStart() { notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes); if (!CarryOver) CarriedOver = InstRef(); - return llvm::ErrorSuccess(); + return ErrorSuccess(); } bool DispatchStage::isAvailable(const InstRef &IR) const { @@ -157,7 +157,7 @@ bool DispatchStage::isAvailable(const InstRef &IR) const { return canDispatch(IR); } -llvm::Error DispatchStage::execute(InstRef &IR) { +Error DispatchStage::execute(InstRef &IR) { assert(canDispatch(IR) && "Cannot dispatch another instruction!"); return dispatch(IR); } diff --git a/llvm/tools/llvm-mca/lib/Stages/ExecuteStage.cpp b/llvm/tools/llvm-mca/lib/Stages/ExecuteStage.cpp index d280e63cdc6..6fbde9011ef 100644 --- a/llvm/tools/llvm-mca/lib/Stages/ExecuteStage.cpp +++ b/llvm/tools/llvm-mca/lib/Stages/ExecuteStage.cpp @@ -85,9 +85,9 @@ Error ExecuteStage::issueReadyInstructions() { } Error ExecuteStage::cycleStart() { - llvm::SmallVector<ResourceRef, 8> Freed; - llvm::SmallVector<InstRef, 4> Executed; - llvm::SmallVector<InstRef, 4> Ready; + SmallVector<ResourceRef, 8> Freed; + SmallVector<InstRef, 4> Executed; + SmallVector<InstRef, 4> Ready; HWS.cycleEvent(Freed, Executed, Ready); |