diff options
author | Tom Stellard <tstellar@redhat.com> | 2018-10-05 04:34:09 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2018-10-05 04:34:09 +0000 |
commit | f02d47d730c6a4547d56eb77e2bb7b7f5db5d44b (patch) | |
tree | 00fd69aca29db840e7763b4e0a4ce7c59f166516 | |
parent | d28959d5690f8e211fceaa5c874af52e74496f19 (diff) |
AMDGPU/GlobalISel: Add support for G_INTTOPTRlinaro-local/ci/tcwg-llvm-kernel-baseline-armv8l-master-stable-defconfig_nolselinaro-local/ci/tcwg-llvm-kernel-baseline-armv8l-master-stablelinaro-local/ci/tcwg-llvm-kernel-baseline-aarch64-master-lts
Summary: This is a no-op.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52916
6 files changed, 100 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index ea184fa6eb7..8eb49d49b2e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -630,6 +630,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, return selectImpl(I, CoverageInfo); case TargetOpcode::G_ADD: return selectG_ADD(I); + case TargetOpcode::G_INTTOPTR: case TargetOpcode::G_BITCAST: return selectCOPY(I); case TargetOpcode::G_CONSTANT: diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index c265283d86d..877251a3ac4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -117,6 +117,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, setAction({G_ICMP, S1}, Legal); setAction({G_ICMP, 1, S32}, Legal); + getActionDefinitionsBuilder(G_INTTOPTR) + .legalIf([](const LegalityQuery &Query) { + return true; + }); getActionDefinitionsBuilder({G_LOAD, G_STORE}) .legalIf([=, &ST](const LegalityQuery &Query) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 0524297da54..8314b4a490f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -402,6 +402,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize); break; } + case AMDGPU::G_INTTOPTR: case AMDGPU::G_BITCAST: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir new file mode 100644 index 00000000000..569a2a5ba96 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir @@ -0,0 +1,34 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN + +--- | + define amdgpu_kernel void @inttoptr(i32 addrspace(4)* %const0, i32 addrspace(0)* %flat0) {ret void} +... +--- + +name: inttoptr +legalized: true +regBankSelected: true + +# GCN-LABEL: name: inttoptr +# GCN: [[S64:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1 +# GCN: [[V64:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 +# FIXME: This extra copy is unnecessary, but is it the instruction selector's +# job to clean this up? +# GCN: [[S64_COPY:%[0-9]+]]:sreg_64 = COPY [[S64]] +# GCN: [[VAL:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S64_COPY]], 0, 0 +# GCN: [[V_VAL:%[0-9]+]]:vgpr_32 = COPY [[VAL]] +# GCN: FLAT_STORE_DWORD [[V64]], [[V_VAL]] +# + +body: | + bb.0: + liveins: $sgpr0_sgpr1, $vgpr0_vgpr1 + %0:sgpr(s64) = COPY $sgpr0_sgpr1 + %1:vgpr(s64) = COPY $vgpr0_vgpr1 + %2:sgpr(p4) = G_INTTOPTR %0 + %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0) + %4:vgpr(p0) = G_INTTOPTR %1 + %5:vgpr(s32) = COPY %3 + G_STORE %5, %4 :: (store 4 into %ir.flat0) +... +--- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir new file mode 100644 index 00000000000..a1fd6c60e57 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir @@ -0,0 +1,29 @@ +# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_inttoptr +body: | + bb.0: + liveins: $sgpr0_sgpr1, $sgpr2, $vgpr0_vgpr1, $vgpr2 + + ; CHECK-LABEL: name: test_inttoptr + ; CHECK: [[S64:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1 + ; CHECK: [[S32:%[0-9]+]]:_(s32) = COPY $sgpr2 + ; CHECK: [[V64:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[V32:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; CHECK: (p0) = G_INTTOPTR [[V64]] + ; CHECK: (p1) = G_INTTOPTR [[V64]] + ; CHECK: (p3) = G_INTTOPTR [[V32]] + ; CHECK: (p4) = G_INTTOPTR [[S64]] + ; CHECK: (p5) = G_INTTOPTR [[S32]] + %0:_(s64) = COPY $sgpr0_sgpr1 + %1:_(s32) = COPY $sgpr2 + %2:_(s64) = COPY $vgpr0_vgpr1 + %3:_(s32) = COPY $vgpr2 + %4:_(p0) = G_INTTOPTR %2 + %5:_(p1) = G_INTTOPTR %2 + %6:_(p3) = G_INTTOPTR %3 + %7:_(p4) = G_INTTOPTR %0 + %8:_(p5) = G_INTTOPTR %1 + S_ENDPGM implicit %4, implicit %5, implicit %6, implicit %7, implicit %8 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir new file mode 100644 index 00000000000..76558a31838 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: inttoptr_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: inttoptr_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 + ; CHECK: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64) + %0:_(s64) = COPY $sgpr0_sgpr1 + %1:_(p4) = G_INTTOPTR %0 +... + +--- +name: inttoptr_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + ; CHECK-LABEL: name: inttoptr_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[INTTOPTR:%[0-9]+]]:vgpr(p0) = G_INTTOPTR [[COPY]](s64) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(p0) = G_INTTOPTR %0 +... |