gcc/testsuite/

	Backport from trunk r223508.
	2015-05-21  Sandra Loosemore  <sandra@codesourcery.com>

	* gcc.target/arm/simd/simd.exp: Skip all tests if no arm_neon_ok
	effective target support.  If no arm_neon_hw support, do not attempt
	to execute the tests; only compile them.
	* gcc.target/arm/simd/vextf32_1.c: Remove explicit "dg-do run"
	and "dg-require-effective-target arm_neon_ok".
	* gcc.target/arm/simd/vextp16_1.c: Likewise.
	* gcc.target/arm/simd/vextp64_1.c: Likewise.
	* gcc.target/arm/simd/vextp8_1.c: Likewise.
	* gcc.target/arm/simd/vextQf32_1.c: Likewise.
	* gcc.target/arm/simd/vextQp16_1.c: Likewise.
	* gcc.target/arm/simd/vextQp64_1.c: Likewise.
	* gcc.target/arm/simd/vextQp8_1.c: Likewise.
	* gcc.target/arm/simd/vextQs16_1.c: Likewise.
	* gcc.target/arm/simd/vextQs32_1.c: Likewise.
	* gcc.target/arm/simd/vextQs64_1.c: Likewise.
	* gcc.target/arm/simd/vextQs8_1.c: Likewise.
	* gcc.target/arm/simd/vextQu16_1.c: Likewise.
	* gcc.target/arm/simd/vextQu32_1.c: Likewise.
	* gcc.target/arm/simd/vextQu64_1.c: Likewise.
	* gcc.target/arm/simd/vextQu8_1.c: Likewise.
	* gcc.target/arm/simd/vexts16_1.c: Likewise.
	* gcc.target/arm/simd/vexts32_1.c: Likewise.
	* gcc.target/arm/simd/vexts64_1.c: Likewise.
	* gcc.target/arm/simd/vexts8_1.c: Likewise.
	* gcc.target/arm/simd/vextu16_1.c: Likewise.
	* gcc.target/arm/simd/vextu32_1.c: Likewise.
	* gcc.target/arm/simd/vextu64_1.c: Likewise.
	* gcc.target/arm/simd/vextu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16p8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16qp8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16qs8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16qu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16s8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16u8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32p16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32p8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qp16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qp8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qs16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qs8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qu16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32s16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32s8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32u16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32u8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64f32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64p16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64p8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qf32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qp16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qp8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qs16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qs32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qs8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qu16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qu32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64s16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64s32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64s8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64u16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64u32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64u8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnf32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnp16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnp8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqf32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqp16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqp8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqs16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqs32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqs8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqu16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqu32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqu8_1.c: Likewise.
	* gcc.target/arm/simd/vtrns16_1.c: Likewise.
	* gcc.target/arm/simd/vtrns32_1.c: Likewise.
	* gcc.target/arm/simd/vtrns8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnu16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnu32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnu8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpf32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpp16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpp8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqf32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqp16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqp8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqs16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqs32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqs8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqu16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqu32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqu8_1.c: Likewise.
	* gcc.target/arm/simd/vuzps16_1.c: Likewise.
	* gcc.target/arm/simd/vuzps32_1.c: Likewise.
	* gcc.target/arm/simd/vuzps8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpu16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpu32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpu8_1.c: Likewise.
	* gcc.target/arm/simd/vzipf32_1.c: Likewise.
	* gcc.target/arm/simd/vzipp16_1.c: Likewise.
	* gcc.target/arm/simd/vzipp8_1.c: Likewise.
	* gcc.target/arm/simd/vzipqf32_1.c: Likewise.
	* gcc.target/arm/simd/vzipqp16_1.c: Likewise.
	* gcc.target/arm/simd/vzipqp8_1.c: Likewise.
	* gcc.target/arm/simd/vzipqs16_1.c: Likewise.
	* gcc.target/arm/simd/vzipqs32_1.c: Likewise.
	* gcc.target/arm/simd/vzipqs8_1.c: Likewise.
	* gcc.target/arm/simd/vzipqu16_1.c: Likewise.
	* gcc.target/arm/simd/vzipqu32_1.c: Likewise.
	* gcc.target/arm/simd/vzipqu8_1.c: Likewise.
	* gcc.target/arm/simd/vzips16_1.c: Likewise.
	* gcc.target/arm/simd/vzips32_1.c: Likewise.
	* gcc.target/arm/simd/vzips8_1.c: Likewise.
	* gcc.target/arm/simd/vzipu16_1.c: Likewise.
	* gcc.target/arm/simd/vzipu32_1.c: Likewise.
	* gcc.target/arm/simd/vzipu8_1.c: Likewise.

Change-Id: Iff2ac73df9a851db93cae44d799c2457b4d1b0a3

115 files changed, 13 insertions, 226 deletions

diff --git a/gcc/testsuite/gcc.target/arm/simd/simd.exp b/gcc/testsuite/gcc.target/arm/simd/simd.exp
index 3afb537f27c..fddf02faa4c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/simd.exp
+++ b/gcc/testsuite/gcc.target/arm/simd/simd.exp
@@ -27,9 +27,22 @@ load_lib gcc-dg.exp
 # Initialize `dg'.
 dg-init
 
+# If the target hardware supports NEON, the default action is "run", otherwise
+# just "compile".
+global dg-do-what-default
+set save-dg-do-what-default ${dg-do-what-default}
+if {![check_effective_target_arm_neon_ok]} then {
+  return
+} elseif {[is-effective-target arm_neon_hw]} then {
+  set dg-do-what-default run
+} else {
+  set dg-do-what-default compile
+}
+
 # Main loop.
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
 	"" ""
 
 # All done.
+set dg-do-what-default ${save-dg-do-what-default}
 dg-finish
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
index c1da6d38a5d..41efba0b187 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
index adc086181b9..643aa2f2c13 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
index e8b688da2b3..5cd1693fa47 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
@@ -1,6 +1,5 @@
 /* Test the `vextQp64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
 /* { dg-require-effective-target arm_crypto_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_crypto } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
index 5f2cc53e367..24fe651dfd9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
index c0d791dcef3..702da6cf0d9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
index ed5b21091cc..b8dc896fd99 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
index dbbee47c58b..a0a28a0ff9d 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
index 0ebdce38165..ac905d8837f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
index 136f2b8741f..2b5bbf37985 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
index 66ce035c5a2..21a536a5148 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
index ebe4abd069f..1f09987ebc2 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
index 432ac0a5674..ddc0911ec77 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
index 99e0bad0ed0..d25a1ae0362 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
index 00695bf6419..5312fde4ff5 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
index 8783e166ea7..2121fab901b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
@@ -1,6 +1,5 @@
 /* Test the `vextp64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
 /* { dg-require-effective-target arm_crypto_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_crypto } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
index 2ba72c1ac0c..544ac03ea6c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
index 4fa57d6b696..2e9e8912f76 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
index 3cd59360e28..cca78e8481e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
index 10053a5e398..0737ba21985 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
index 194e198b98e..ed3f50be8f9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
index f69c2bdc77f..7d9cc51a104 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
index b76e383cadb..48effc05bc6 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
index eeb0be2732c..b4d4f870d29 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
index a9d62b31dff..aacfb39f0c0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
index fddb32fbb8b..7eec89236b1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
index b4634b8dbde..073b7c4da84 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16q_p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
index 691799b6b94..9d36c7af8ec 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16q_s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
index f6ab4ac5cd1..bbcf1717f07 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16q_u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
index 0a03721f29c..f7d0f7af69f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
index 7e5f54808ac..e94b7089ace 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
index f3643fa96da..b3d170210e9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
index d823e59ff1c..664cae83e69 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
index f8ba8a916ef..0f462d07b23 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
index 0ddf6081a82..44f4be30c9e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
index 30d0314c202..8ad01ea1c27 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
index 03ddd2be25c..b04959359f1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
index 71765437b65..7c2602ac3bb 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
index 403292c7cd8..0d98d19a2ed 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
index e182ab988ce..8642c79f8bb 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
index a48c4155176..37411b13e83 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
index 076f8ab885b..2293f499cf3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
index 240d4596e8c..5d7190513a3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
index f5d3bcae564..d393baf7321 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64f32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
index 8c685c0f8ca..d61cdb8e886 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
index 67ac1e49117..6ac5281f3bd 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
index 74130b7d821..8e576a1f8c7 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_f32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
index 71f3b4ba4b7..b60a005b58f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
index 324a738c660..c50ea03e442 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
index 9a373ec4100..f294c2f277e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
index 0f10c6cb078..f1c953f8424 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_s32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
index cf380143be6..42a59a02595 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
index 010d6dbb805..14f576962b5 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
index 908769cc682..8ad81e8355d 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_u32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
index 2fa07d12980..f094926d836 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
index f14319c3214..d448e48c2dd 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
index ead57225f3e..8cfee433d28 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64s32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
index 29d684dcd1c..685bfa34097 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
index feddacce2b5..7b871489121 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
index 92a81f44041..589d6780688 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64u32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
index f904af5ca77..9bd14bd99a1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
index 0f9b6c9b8bd..91be87149bd 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
index 0ff43198109..695c208a739 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
index 2b047e4d759..5124f61e1df 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
index dd4e8836f3c..bad97a5041b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
index 374eee396de..26a6cf4c1d4 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
index b252fd5f3b0..e883523ab3c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
index 5f06d2a3b12..19bbb48eca9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
index 221175c46c6..348bd96b24e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
index 9352b37a783..3b607181d35 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
index 7f40109b2a3..e12bad130e0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
index 1c61fc34f7c..9d051204b94 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
index 82f911d5a78..a59a908909d 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
index af2c68f381f..330af22eb33 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrns16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
index 35a98ea9551..b20a752afa7 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrns32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
index 395015d1330..ce268169b43 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrns8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
index df0d963a5fa..a8343ae3b71 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
index 764ed623f07..7d2f36d7eff 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
index f5b4d68966e..65521f9c410 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
index 723c86a16be..845d20390cb 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
index c7ad757b55e..09226233b8f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
index 670b5506779..916e39615e6 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
index 53147f1a43e..bcdf30378ed 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
index feef15af27e..4d3aeab30d9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
index db98f353354..9288c4ba11b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
index 808d562732b..9c7e10efdcd 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
index 7adf5f9b91f..60a79c91d50 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
index 9d0256a632a..4757eac7703 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
index 23106edf529..cb33d4a4616 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
index 0002fdfcbd9..ebaeea04ad8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
index f8d19dc5582..221cde604dc 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
index 6e3f2eb118b..77ccb47ffe9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzps16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
index 372c3938754..42a763bda6c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzps32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
index 3338477778e..5a9242e46b8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzps8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
index 378b5a9df91..b43df716f90 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
index ebb0d6b5fa6..0e746c88e13 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
index 82719a503c4..fbdcec7d723 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
index efaa96ea955..55cb956cf9f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
index 4154333a7f7..7b674579dcc 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
index 9fe2384c9f9..8222857ea66 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
index 8c547a79f5b..34f8afcefe3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
index e2af10b2af1..f0ef7feb2be 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
index 11a13298563..2e78311f61a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
index 0576c0033e6..89ed05e9be3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
index 6cf24396d20..9f4ed6e448f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
index 0244374e001..9bb0d772fe1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
index 3c406f514d2..6a5b6a92244 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
index ba1393c6c92..e46681ba4b8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
index 023ecac3a52..882169bd05f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
index b6c3c2fe897..5c2b680c906 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzips16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
index 1a6f1709342..5deb49b7693 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzips32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
index 8569357817b..69a1b65c9e2 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzips8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
index 23bfcc4d962..0c478963b0e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
index 6a753f25a9c..8b666a3b38e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
index 972af74237f..f7878a6986a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */