RISC-V: Add testcases for vector unsigned SAT_SUB form 2HEADtrunkmaster

The previous RISC-V backend .SAT_SUB enabling patch missed the form 2
testcases of vector modes.  Aka:

Form 2:
  #define DEF_VEC_SAT_U_SUB_FMT_2(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = (x - y) & (-(T)(x > y));                              \
      }                                                                \
  }

This patch would like to make it up to ensure form 2 of .SAT_SUB vector
is covered.

Passed the rv64gcv rvv.exp tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions