gcc.git - Linaro gcc mirror (git://gcc.gnu.org/git/gcc.git) + linaro-local branches

Age	Commit message (Expand)	Author
8 days	Add AVX10.1 target_clones support	Haochen Jiang
2024-05-20	i386: Remove Xeon Phi ISA support	Haochen Jiang
2024-05-16	RISC-V: Add Zvfbfwma extension to the -march= option	Xiao Zeng
2024-05-06	[PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option	Xiao Zeng
2024-04-29	RISC-V: Fix parsing of Zic* extensions	Christoph Müllner
2024-04-22	i386: Fix Sierra Forest auto dispatch	Haochen Jiang
2024-03-31	RISC-V: Fix one unused varable in riscv_subset_list::parse	Pan Li
2024-03-22	RISC-V: Bugfix function target attribute pollution	Pan Li
2024-03-22	RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))	Pan Li
2024-03-18	[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P	Mary Bennett
2024-03-18	Add AMD znver5 processor enablement with scheduler model	Jan Hubicka
2024-02-29	AVR: target/114100 - Better indirect accesses for reduced Tiny	Georg-Johann Lay
2024-02-16	RISC-V: Add new option -march=help to print all supported extensions	Kito Cheng
2024-02-01	RISC-V: Add minimal support for 7 new unprivileged extensions	Monk Chiang
2024-01-25	RISC-V: Add support for XCVsimd extension in CV32E40P	Mary Bennett
2024-01-24	RISC-V: Don't make Ztso imply A	Palmer Dabbelt
2024-01-19	RISC-V: Add the Zihpm and Zicntr extensions	Palmer Dabbelt
2024-01-19	RISC-V: Remove unused function in riscv_subset_list [NFC]	Kito Cheng
2024-01-19	RISC-V: Relax the -march string for accept any order	Kito Cheng
2024-01-19	RISC-V: Extract part parsing base ISA logic into a standalone function [NFC]	Kito Cheng
2024-01-18	RISC-V: Introduce XTheadVector as a subset of V1.0.0	Jun Sha (Joshua)
2024-01-03	Update copyright years.	Jakub Jelinek
2023-12-16	[aarch64] Add function multiversioning support	Andrew Carlotti
2023-12-16	aarch64: Fix +nopredres, +nols64 and +nomops	Andrew Carlotti
2023-12-16	aarch64: Fix +nocrypto handling	Andrew Carlotti
2023-12-15	[PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P	Mary Bennett
2023-12-15	[PATCH] RISC-V: Add Zvfbfmin extension to the -march= option	Xiao Zeng
2023-12-13	RISC-V:Add crypto vector implied ISA info.	Feng Wang
2023-12-07	aarch64: Add an early RA for strided registers	Richard Sandiford
2023-12-05	RISC-V: Check if zcd conflicts with zcmt and zcmp	Kito Cheng
2023-12-04	RISC-V: Update crypto vector ISA info with latest spec	Feng Wang
2023-12-04	RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional i...	Kito Cheng
2023-12-04	RISC-V: Refine riscv_subset_list::parse [NFC]	Kito Cheng
2023-12-04	i386: Fix CPUID of USER_MSR.	Hu, Lin1
2023-11-27	RISC-V: Initial RV64E and LP64E support	Tsukasa OI
2023-11-20	Initial support for AVX10.1	Haochen Jiang
2023-11-15	RISC-V: Fix ICE in non-canonical march parsing	Patrick O'Neill
2023-10-30	i386: Zhaoxin yongfeng enablement	Mayshao
2023-10-22	RISC-V: Prohibit combination of 'E' and 'H'	Tsukasa OI
2023-10-22	RISC-V: 'Zfa' extension is now ratified	Tsukasa OI
2023-10-18	Initial Panther Lake Support	Haochen Jiang
2023-10-18	Initial Clearwater Forest Support	Haochen Jiang
2023-10-12	Support Intel USER_MSR	Hu, Lin1
2023-10-11	RISC-V: Extend riscv_subset_list, preparatory for target attribute support	Kito Cheng
2023-10-11	[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett
2023-10-11	[PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett
2023-10-09	Initial support for -mevex512	Haochen Jiang
2023-10-07	[APX_EGPR] Initial support for APX_F	Kong Lingling
2023-09-08	LoongArch: Enable -fsched-pressure by default at -O1 and higher.	Guo Jie
2023-09-07	RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support	Tsukasa OI