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Age	Commit message (Expand)	Author
7 days	RISC-V: Implement .SAT_SUB for unsigned vector int	Pan Li
10 days	RISC-V: Implement .SAT_SUB for unsigned scalar int	Pan Li
2024-05-21	RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]	Vineet Gupta
2024-05-18	RISC-V: Implement IFN SAT_ADD for both the scalar and vector	Pan Li
2024-05-17	RISC-V: Add initial cost handling for segment loads/stores.	Robin Dapp
2024-05-15	[v2,1/2] RISC-V: Add cmpmemsi expansion	Christoph Müllner
2024-05-14	RISC-V: avoid LUI based const materialization ... [part of PR/106265]	Vineet Gupta
2024-05-14	[PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero	Christoph Müllner
2024-04-30	This is almost exclusively Jivan's work. His original post:	Jivan Hakobyan
2024-04-08	RISC-V: Implement TLS Descriptors.	Tatsuyuki Ishi
2024-04-08	RISC-V: Allow RVV intrinsic for more function target	Pan Li
2024-03-07	RISC-V: Refactor expand_vec_cmp [NFC]	demin.han
2024-02-16	RISC-V: Add new option -march=help to print all supported extensions	Kito Cheng
2024-02-07	RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty args	Pan Li
2024-01-22	RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x	Juzhe-Zhong
2024-01-19	RISC-V: Fix RVV_VLMAX	Juzhe-Zhong
2024-01-18	RISC-V: Adds the prefix "th." for the instructions of XTheadVector.	Jun Sha (Joshua)
2024-01-15	RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark...	Juzhe-Zhong
2024-01-12	RISC-V: Adjust scalar_to_vec cost	Juzhe-Zhong
2024-01-10	RISC-V: T-HEAD: Add support for the XTheadInt ISA extension	Jin Ma
2024-01-10	RISC-V: Refine unsigned avg_floor/avg_ceil	Juzhe-Zhong
2024-01-06	RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move	Juzhe-Zhong
2024-01-03	Update copyright years.	Jakub Jelinek
2023-12-20	RISC-V: Support -mcmodel=large.	Kuan-Lin Chen
2023-12-14	expmed: Use GET_MODE_PRECISION and expander's output mode.	Robin Dapp
2023-12-14	RISC-V: Add RVV builtin vectorization cost model	Juzhe-Zhong
2023-12-12	RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]	Juzhe-Zhong
2023-12-08	RISC-V: Add vectorized strcmp and strncmp.	Robin Dapp
2023-12-08	RISC-V: Add vectorized strlen.	Robin Dapp
2023-12-08	RISC-V: Support interleave vector with different step sequence	Juzhe-Zhong
2023-12-05	RISC-V: Add blocker for gather/scatter auto-vectorization	Juzhe-Zhong
2023-11-27	RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p	Juzhe-Zhong
2023-11-23	RISC-V: Add wrapper for emit vec_extract[NFC]	Juzhe-Zhong
2023-11-22	RISC-V: Handle FP NE operator via inversion in cond-operation expansion	Maciej W. Rozycki
2023-11-22	RISC-V: Implement `riscv_emit_unary' helper	Maciej W. Rozycki
2023-11-19	[committed] RISC-V: Infrastructure for instruction fusion	Philipp Tomsich
2023-11-16	RISC-V: Implement target attribute	Kito Cheng
2023-11-13	RISC-V: Support FP l/ll round and rint HF mode autovec	Pan Li
2023-11-10	RISC-V: Add combine optimization by slideup for vec_init vectorization	Juzhe-Zhong
2023-11-06	RISC-V: Early expand DImode vec_duplicate in RV32 system	Juzhe-Zhong
2023-11-06	internal-fn: Add VCOND_MASK_LEN.	Robin Dapp
2023-11-06	RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic	xuli
2023-11-03	RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326]	Juzhe-Zhong
2023-10-31	riscv: thead: Add support for the XTheadMemIdx ISA extension	Christoph Müllner
2023-10-30	RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32	Juzhe-Zhong
2023-10-27	RISC-V: Add rawmemchr expander.	Robin Dapp
2023-10-27	RISC-V: Add AVL propagation PASS for RVV auto-vectorization	Juzhe-Zhong
2023-10-25	RISC-V: Export some functions from riscv-vsetvl to riscv-v[NFC]	Juzhe-Zhong
2023-10-25	RISC-V: Change MD attribute avl_type into avl_type_idx[NFC]	Juzhe-Zhong
2023-10-23	RISC-V: Add popcount fallback expander.	Robin Dapp