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31 files changed, 3907 insertions, 0 deletions
diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiSsdtRootPci.asl b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiSsdtRootPci.asl new file mode 100644 index 0000000..42f8907 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiSsdtRootPci.asl @@ -0,0 +1,171 @@ +/** @file + Differentiated System Description Table Fields (SSDT) + + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ArmPlatform.h" + +/* + See Reference [1] 6.2.12 + "There are two ways that _PRT can be used. ... + In the second model, the PCI interrupts are hardwired to specific interrupt + inputs on the interrupt controller and are not configurable. In this case, + the Source field in _PRT does not reference a device, but instead contains + the value zero, and the Source Index field contains the global system + interrupt to which the PCI interrupt is hardwired." +*/ +#define PRT_ENTRY(Address, Pin, Interrupt) \ + Package (4) { \ + Address, /* uses the same format as _ADR */ \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \ + Zero, /* allocated from the global interrupt pool. */ \ + Interrupt /* global system interrupt number */ \ + } + +/* + See Reference [1] 6.1.1 + "High word–Device #, Low word–Function #. (for example, device 3, function 2 is + 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)." +*/ +#define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt) + // Device 0 for Bridge. + + +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-ASHBROOK", EFI_ACPI_ARM_OEM_REVISION) { + Scope(_SB) { + // + // PCI Root Complex + // + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1) + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, 168), // INTA + ROOT_PRT_ENTRY(1, 169), // INTB + ROOT_PRT_ENTRY(2, 170), // INTC + ROOT_PRT_ENTRY(3, 171), // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x50000000, // Min Base Address + 0x57FFFFFF, // Max Base Address + 0x00000000, // Translate + 0x08000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x4000000000, // Min Base Address + 0x40FFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x100000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x5f800000, // Min Base Address + 0x5fffffff, // Max Base Address + 0x5f800000, // Translate + 0x00800000 // Length + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method(_OSC,4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If(LNotEqual(And(SUPP, 0x16), 0x16)) { + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } +} diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiTables.inf b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiTables.inf new file mode 100644 index 0000000..b540b7a --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiTables.inf @@ -0,0 +1,53 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AshbrookAcpiTables + FILE_GUID = a1dd808e-1e95-4399-abc0-653c82e8530c + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt.asl + Facs.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + AcpiSsdtRootPci.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec + OpenPlatformPkg/Platforms/ARM/Ashbrook/Ashbrook.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Dsdt.asl b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Dsdt.asl new file mode 100644 index 0000000..a634972 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Dsdt.asl @@ -0,0 +1,237 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ArmPlatform.h" + +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-ASHBROOK", EFI_ACPI_ARM_OEM_REVISION) { + Scope(_SB) { + // + // A72x4 Processor declaration + // + Device(CP00) { // A72-0: Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + Device(CP01) { // A72-0: Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + Device(CP02) { // A72-0: Cluster 0, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + Device(CP03) { // A72-0: Cluster 0, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device(CP04) { // A72-0: Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + Device(CP05) { // A72-0: Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + Device(CP06) { // A72-0: Cluster 1, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + Device(CP07) { // A72-0: Cluster 1, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 7) + } + + Device(CP08) { // A72-0: Cluster 2, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 8) + } + Device(CP09) { // A72-0: Cluster 2, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 9) + } + Device(CP10) { // A72-0: Cluster 2, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 10) + } + Device(CP11) { // A72-0: Cluster 2, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 11) + } + + Device(CP12) { // A72-0: Cluster 3, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 12) + } + Device(CP13) { // A72-0: Cluster 3, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 13) + } + Device(CP14) { // A72-0: Cluster 3, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 14) + } + Device(CP15) { // A72-0: Cluster 3, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 15) + } + + Device(CP16) { // A72-0: Cluster 4, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 16) + } + Device(CP17) { // A72-0: Cluster 4, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 17) + } + Device(CP18) { // A72-0: Cluster 4, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 18) + } + Device(CP19) { // A72-0: Cluster 4, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 19) + } + + Device(CP20) { // A72-0: Cluster 5, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 20) + } + Device(CP21) { // A72-0: Cluster 5, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 21) + } + Device(CP22) { // A72-0: Cluster 5, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 22) + } + Device(CP23) { // A72-0: Cluster 5, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 23) + } + + Device(CP24) { // A72-0: Cluster 6, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 24) + } + Device(CP25) { // A72-0: Cluster 6, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 25) + } + Device(CP26) { // A72-0: Cluster 6, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 26) + } + Device(CP27) { // A72-0: Cluster 6, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 27) + } + + Device(CP28) { // A72-0: Cluster 7, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 28) + } + Device(CP29) { // A72-0: Cluster 7, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 29) + } + Device(CP30) { // A72-0: Cluster 7, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 30) + } + Device(CP31) { // A72-0: Cluster 7, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 31) + } + + Device(CP32) { // A72-0: Cluster 8, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 32) + } + Device(CP33) { // A72-0: Cluster 8, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 33) + } + Device(CP34) { // A72-0: Cluster 8, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 34) + } + Device(CP35) { // A72-0: Cluster 8, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 35) + } + + Device(CP36) { // A72-0: Cluster 9, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 36) + } + Device(CP37) { // A72-0: Cluster 9, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 37) + } + Device(CP38) { // A72-0: Cluster 9, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 38) + } + Device(CP39) { // A72-0: Cluster 9, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 39) + } + + Device(CP40) { // A72-0: Cluster 10, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 40) + } + Device(CP41) { // A72-0: Cluster 10, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 41) + } + Device(CP42) { // A72-0: Cluster 10, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 42) + } + Device(CP43) { // A72-0: Cluster 10, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 43) + } + + Device(CP44) { // A72-0: Cluster 11, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 44) + } + Device(CP45) { // A72-0: Cluster 11, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 45) + } + Device(CP46) { // A72-0: Cluster 11, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 46) + } + Device(CP47) { // A72-0: Cluster 11, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 47) + } + + // UART PL011 + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "PL011") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 147 } + }) + } + } // Scope(_SB) +} diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Facs.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Facs.aslc new file mode 100644 index 0000000..329a19a --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Facs.aslc @@ -0,0 +1,66 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length + 0xA152, // UINT32 HardwareSignature + 0, // UINT32 FirmwareWakingVector + 0, // UINT32 GlobalLock + 0, // UINT32 Flags + 0, // UINT64 XFirmwareWakingVector + EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + { + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] + EFI_ACPI_RESERVED_BYTE // UINT8 Reserved0[2] + }, + 0, // UINT32 OspmFlags "Platform firmware must + // initialize this field to zero." + { + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[23] + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs; diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Fadt.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Fadt.aslc new file mode 100644 index 0000000..d69e1b0 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Fadt.aslc @@ -0,0 +1,87 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_0_HW_REDUCED_ACPI | EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 HypervisorVendorIdentity; +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Gtdt.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Gtdt.aslc new file mode 100644 index 0000000..af0eb39 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Gtdt.aslc @@ -0,0 +1,83 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + + #pragma pack (1) + + typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[ASHBROOK_WATCHDOG_COUNT]; + } EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES; + + #pragma pack () + + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ARM_ACPI_HEADER( + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + ASHBROOK_WATCHDOG_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), + EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + } + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Madt.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Madt.aslc new file mode 100644 index 0000000..a63db94 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/Madt.aslc @@ -0,0 +1,220 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +// +// Multiple APIC Description Table +// + #pragma pack (1) + + typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdClusterCount) * FixedPcdGet32 (PcdCoreCount)]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributor; + } EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + + #pragma pack () + + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of + // ACPI v6.0). + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-0 + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-1 + 0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-2 + 0, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-3 + 0, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-4 + 0, 4, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-5 + 0, 5, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-6 + 0, 6, GET_MPID(1, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-7 + 0, 7, GET_MPID(1, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-8 + 0, 8, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-9 + 0, 9, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-10 + 0, 10, GET_MPID(2, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-11 + 0, 11, GET_MPID(2, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-12 + 0, 12, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-13 + 0, 13, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-14 + 0, 14, GET_MPID(3, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-15 + 0, 15, GET_MPID(3, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-16 + 0, 16, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-17 + 0, 17, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-18 + 0, 18, GET_MPID(4, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-19 + 0, 19, GET_MPID(4, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-20 + 0, 20, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-21 + 0, 21, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-22 + 0, 22, GET_MPID(5, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-23 + 0, 23, GET_MPID(5, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-24 + 0, 24, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-25 + 0, 25, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-26 + 0, 26, GET_MPID(6, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-27 + 0, 27, GET_MPID(6, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-28 + 0, 28, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-29 + 0, 29, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-30 + 0, 30, GET_MPID(7, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-31 + 0, 31, GET_MPID(7, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-32 + 0, 32, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-33 + 0, 33, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-34 + 0, 34, GET_MPID(8, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-35 + 0, 35, GET_MPID(8, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-36 + 0, 36, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-37 + 0, 37, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-38 + 0, 38, GET_MPID(9, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-39 + 0, 39, GET_MPID(9, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-40 + 0, 40, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-41 + 0, 41, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-42 + 0, 42, GET_MPID(10, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-43 + 0, 43, GET_MPID(10, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-44 + 0, 44, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-45 + 0, 45, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-46 + 0, 46, GET_MPID(11, 2), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A72-47 + 0, 47, GET_MPID(11, 3), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + }, + // GIC Distributor Entry + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3), + // GIC Redistributor + EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), 0x600000) + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiSsdtRootPci.asl b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiSsdtRootPci.asl new file mode 100644 index 0000000..f8d637b --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiSsdtRootPci.asl @@ -0,0 +1,171 @@ +/** @file + Differentiated System Description Table Fields (SSDT) + + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ArmPlatform.h" + +/* + See Reference [1] 6.2.12 + "There are two ways that _PRT can be used. ... + In the second model, the PCI interrupts are hardwired to specific interrupt + inputs on the interrupt controller and are not configurable. In this case, + the Source field in _PRT does not reference a device, but instead contains + the value zero, and the Source Index field contains the global system + interrupt to which the PCI interrupt is hardwired." +*/ +#define PRT_ENTRY(Address, Pin, Interrupt) \ + Package (4) { \ + Address, /* uses the same format as _ADR */ \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \ + Zero, /* allocated from the global interrupt pool. */ \ + Interrupt /* global system interrupt number */ \ + } + +/* + See Reference [1] 6.1.1 + "High word–Device #, Low word–Function #. (for example, device 3, function 2 is + 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)." +*/ +#define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt) + // Device 0 for Bridge. + + +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-ASHBROOK_5", EFI_ACPI_ARM_OEM_REVISION) { + Scope(_SB) { + // + // PCI Root Complex + // + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1) + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, 168), // INTA + ROOT_PRT_ENTRY(1, 169), // INTB + ROOT_PRT_ENTRY(2, 170), // INTC + ROOT_PRT_ENTRY(3, 171), // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x50000000, // Min Base Address + 0x57FFFFFF, // Max Base Address + 0x00000000, // Translate + 0x08000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x4000000000, // Min Base Address + 0x40FFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x100000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x5f800000, // Min Base Address + 0x5fffffff, // Max Base Address + 0x5f800000, // Translate + 0x00800000 // Length + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method(_OSC,4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If(LNotEqual(And(SUPP, 0x16), 0x16)) { + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } +} diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiTables.inf b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiTables.inf new file mode 100644 index 0000000..b540b7a --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiTables.inf @@ -0,0 +1,53 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AshbrookAcpiTables + FILE_GUID = a1dd808e-1e95-4399-abc0-653c82e8530c + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt.asl + Facs.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + AcpiSsdtRootPci.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec + OpenPlatformPkg/Platforms/ARM/Ashbrook/Ashbrook.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Dsdt.asl b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Dsdt.asl new file mode 100644 index 0000000..d494a74 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Dsdt.asl @@ -0,0 +1,141 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ArmPlatform.h" + +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-ASHBROOK_5", EFI_ACPI_ARM_OEM_REVISION) { + Scope(_SB) { + // + // A53x4 Processor declaration + // + Device(CP00) { // A53-0: Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + Device(CP01) { // A53-0: Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + + Device(CP04) { // A53-0: Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + Device(CP05) { // A53-0: Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device(CP08) { // A53-0: Cluster 2, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + Device(CP09) { // A53-0: Cluster 2, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + + Device(CP12) { // A53-0: Cluster 3, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + Device(CP13) { // A53-0: Cluster 3, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 7) + } + + Device(CP16) { // A53-0: Cluster 4, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 8) + } + Device(CP17) { // A53-0: Cluster 4, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 9) + } + + Device(CP20) { // A53-0: Cluster 5, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 10) + } + Device(CP21) { // A53-0: Cluster 5, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 11) + } + + Device(CP24) { // A53-0: Cluster 6, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 12) + } + Device(CP25) { // A53-0: Cluster 6, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 13) + } + + Device(CP28) { // A53-0: Cluster 7, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 14) + } + Device(CP29) { // A53-0: Cluster 7, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 15) + } + + Device(CP32) { // A53-0: Cluster 8, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 16) + } + Device(CP33) { // A53-0: Cluster 8, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 17) + } + + Device(CP36) { // A53-0: Cluster 9, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 18) + } + Device(CP37) { // A53-0: Cluster 9, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 19) + } + + Device(CP40) { // A53-0: Cluster 10, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 20) + } + Device(CP41) { // A53-0: Cluster 10, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 21) + } + + Device(CP44) { // A53-0: Cluster 11, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 22) + } + Device(CP45) { // A53-0: Cluster 11, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 23) + } + + // UART PL011 + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "PL011") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 147 } + }) + } + } // Scope(_SB) +} diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Facs.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Facs.aslc new file mode 100644 index 0000000..329a19a --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Facs.aslc @@ -0,0 +1,66 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length + 0xA152, // UINT32 HardwareSignature + 0, // UINT32 FirmwareWakingVector + 0, // UINT32 GlobalLock + 0, // UINT32 Flags + 0, // UINT64 XFirmwareWakingVector + EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + { + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] + EFI_ACPI_RESERVED_BYTE // UINT8 Reserved0[2] + }, + 0, // UINT32 OspmFlags "Platform firmware must + // initialize this field to zero." + { + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[23] + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs; diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Fadt.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Fadt.aslc new file mode 100644 index 0000000..d69e1b0 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Fadt.aslc @@ -0,0 +1,87 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_0_HW_REDUCED_ACPI | EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 HypervisorVendorIdentity; +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Gtdt.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Gtdt.aslc new file mode 100644 index 0000000..af0eb39 --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Gtdt.aslc @@ -0,0 +1,83 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + + #pragma pack (1) + + typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[ASHBROOK_WATCHDOG_COUNT]; + } EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES; + + #pragma pack () + + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ARM_ACPI_HEADER( + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + ASHBROOK_WATCHDOG_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), + EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + } + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Madt.aslc b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Madt.aslc new file mode 100644 index 0000000..109f7ec --- /dev/null +++ b/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/Madt.aslc @@ -0,0 +1,148 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +// +// Multiple APIC Description Table +// + #pragma pack (1) + + typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdClusterCount) * FixedPcdGet32 (PcdCoreCount)]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributor; + } EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + + #pragma pack () + + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of + // ACPI v6.0). + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0 + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-1 + 0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-2 + 0, 2, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-3 + 0, 3, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-4 + 0, 4, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-5 + 0, 5, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-6 + 0, 6, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-7 + 0, 7, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-8 + 0, 8, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-9 + 0, 9, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-10 + 0, 10, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-11 + 0, 11, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-12 + 0, 12, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-13 + 0, 13, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-14 + 0, 14, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-15 + 0, 15, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-16 + 0, 16, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-17 + 0, 17, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-18 + 0, 18, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-19 + 0, 19, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-20 + 0, 20, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-21 + 0, 21, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-22 + 0, 22, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-23 + 0, 23, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */), + }, + // GIC Distributor Entry + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3), + // GIC Redistributor + EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), 0x300000) + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Platforms/ARM/Ashbrook/Ashbrook.dec b/Platforms/ARM/Ashbrook/Ashbrook.dec new file mode 100644 index 0000000..482b7ac --- /dev/null +++ b/Platforms/ARM/Ashbrook/Ashbrook.dec @@ -0,0 +1,32 @@ +# +# Copyright (c) 2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = Ashbrook + PACKAGE_GUID = 577d6941-aea1-40b4-9093-2a8661725a57 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gAshbrookTokenSpaceGuid = { 0x577d6941, 0xaea1, 0x40b4, { 0x90, 0x93, 0x2a, 0x86, 0x61, 0x72, 0x5a, 0x57 } } diff --git a/Platforms/ARM/Ashbrook/Ashbrook.dsc b/Platforms/ARM/Ashbrook/Ashbrook.dsc new file mode 100644 index 0000000..6ee5f19 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Ashbrook.dsc @@ -0,0 +1,286 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] +!if $(ASHBROOK_VARIANT) == 2 + PLATFORM_NAME = Ashbrook_DevPlatform + PLATFORM_GUID = 947f8411-9b98-4807-9fee-1e1c04af717b +!else + PLATFORM_NAME = Ashbrook_5_DevPlatform + PLATFORM_GUID = a8180daa-fb8b-11e5-ab24-9fc3167c073d +!endif + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64|ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = OpenPlatformPkg/Platforms/ARM/Ashbrook/Ashbrook.fdf + +# On RTSM, most peripherals are VExpress Motherboard peripherals +!include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc + +[LibraryClasses.common] + ArmPlatformLib|OpenPlatformPkg/Platforms/ARM/Ashbrook/Library/AshbrookLib/AshbrookLib.inf + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|OpenPlatformPkg/Platforms/ARM/Ashbrook/Library/NorFlashAshbrookLib/NorFlashAshbrookLib.inf + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + +[LibraryClasses.ARM] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + +[LibraryClasses.AARCH64] + ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf + +[LibraryClasses.common.SEC] + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + +[BuildOptions] +!ifdef $(ASHBROOK_EMULATOR) + *_*_*_ARCHCC_FLAGS = -DASHBROOK_EMULATOR=1 + *_*_*_PP_FLAGS = -DASHBROOK_EMULATOR=1 +!endif + *_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/ARM/Ashbrook/Include + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Ashbrook" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Ashbrook" + + # + # NV Storage PCDs. Use base of 0x08000000 for NOR0, 0xC0000000 for NOR 1 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0BFC0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0BFD0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0BFE0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 + + # Ashbrook 12-Cluster profile +!if $(ASHBROOK_VARIANT) == 2 + gArmPlatformTokenSpaceGuid.PcdCoreCount|4 +!else + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 +!endif + gArmPlatformTokenSpaceGuid.PcdClusterCount|12 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # + # ARM PrimeCell + # + + ## PL011 - Serial Terminal + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 +!ifdef $(ASHBROOK_EMULATOR) + gArmPlatformTokenSpaceGuid.PL011UartInteger|1 + gArmPlatformTokenSpaceGuid.PL011UartFractional|0 +!else + gArmPlatformTokenSpaceGuid.PL011UartInteger|4 + gArmPlatformTokenSpaceGuid.PL011UartFractional|0 +!endif + + ## PL180 MMC/SD card controller + + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30400000 +!ifdef $(ASHBROOK_EMULATOR) + !if $(ASHBROOK_VARIANT) == 2 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30200000 + !endif +!else + !if $(ASHBROOK_VARIANT) == 2 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30800000 + !endif +!endif + + # List of Device Paths that support BootMonFs + gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)" + + # + # ARM OS Loader + # + + # Configured for Default Mainline Linux Kernel Boot + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from DRAM" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(30F57E4A-69CE-4FB7-B7A1-4C7CE49D57A6)/MemoryMapped(0x0,0x80080000,0x81000000)" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"initrd=0x88000000,0x00200000 acpi=force console=ttyAMA0,115200 earlycon=pl011,0x7ff80000 earlyprintk=pl011,0x7ff80000 root=/dev/ram1 rootwait verbose debug" +!ifdef $(ASHBROOK_EMULATOR) + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 +!endif + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM Architectural Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|10000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000000 + +[PcdsPatchableInModule] + # Console Resolution (Full HD) + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|1080 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePi/PeiMPCore.inf + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + +!ifdef $(ASHBROOK_EMULATOR) + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf +!else + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf +!endif + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf +!if $(ASHBROOK_VARIANT) == 2 + OpenPlatformPkg/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiTables.inf +!else + OpenPlatformPkg/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiTables.inf +!endif + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +!ifndef $(ASHBROOK_EMULATOR) + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf +!endif + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # Semi-hosting filesystem + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # Multimedia Card Interface + # + + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # Networking stack + + # + # Ashbrook development platform driver + # + OpenPlatformPkg/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + ArmPlatformPkg/Bds/Bds.inf diff --git a/Platforms/ARM/Ashbrook/Ashbrook.fdf b/Platforms/ARM/Ashbrook/Ashbrook.fdf new file mode 100644 index 0000000..6a8d7a0 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Ashbrook.fdf @@ -0,0 +1,336 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_AP_UEFI] +BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0xF0 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x000F0000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf +!ifdef $(ASHBROOK_EMULATOR) + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf +!else + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf +!endif + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +!if $(ASHBROOK_VARIANT) == 2 + INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_2/AcpiTables.inf +!else + INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/ARM/Ashbrook/AcpiTables/Ashbrook_5/AcpiTables.inf +!endif + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + #INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + #INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + #INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + +!ifndef $(ASHBROOK_EMULATOR) + # NOR Flash driver + INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + + # Semi-hosting filesystem + INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + # Versatile Express FileSystem + INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # FV FileSystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # + # Networking stack + # + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf + + # + # UEFI applications + # + #INF ShellBinPkg/UefiShell/UefiShell.inf + INF ShellPkg/Application/Shell/Shell.inf + + # + # Ashbrook development platform driver + # + INF OpenPlatformPkg/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiMPCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +# +# These SEC rules are used for ArmPlatformPkg/PrePi module. +# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the +# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint +# +[Rule.ARM.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.AARCH64.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +# A shim specific rule is required to ensure the alignment is 4K. +# Otherwise BaseTools pick up the AArch32 alignment (ie: 32) +[Rule.ARM.SEC.SHIM] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.c b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.c new file mode 100644 index 0000000..00aed04 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.c @@ -0,0 +1,95 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "AshbrookDxeInternal.h" +#include <Library/ArmShellCmdLib.h> + +// This GUID must match the FILE_GUID in ArmPlatformPkg/AshbrookPkg/AcpiTables/AcpiTables.inf +STATIC CONST EFI_GUID mAshbrookAcpiTableFile = { 0xa1dd808e, 0x1e95, 0x4399, { 0xab, 0xc0, 0x65, 0x3c, 0x82, 0xe8, 0x53, 0x0c } }; + +EFI_STATUS +EFIAPI +AshbrookEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS HypBase; + + Status = InitDramBlockIo (); + ASSERT_EFI_ERROR (Status); + + if (EFI_ERROR (Status)) { + return Status; + } + + // + // If a hypervisor has been declared then we need to make sure its region is protected at runtime + // + // Note: This code is only a workaround for our dummy hypervisor (ArmPkg/Extra/AArch64ToAArch32Shim/) + // that does not set up (yet) the stage 2 translation table to hide its own memory to EL1. + // + if (FixedPcdGet32 (PcdHypFvSize) != 0) { + // Ensure the hypervisor region is strictly contained into a EFI_PAGE_SIZE-aligned region. + // The memory must be a multiple of EFI_PAGE_SIZE to ensure we do not reserve more memory than the hypervisor itself. + // A UEFI Runtime region size granularity cannot be smaller than EFI_PAGE_SIZE. If the hypervisor size is not rounded + // to this size then there is a risk some non-runtime memory could be visible to the OS view. + if (((FixedPcdGet32 (PcdHypFvSize) & EFI_PAGE_MASK) == 0) && ((FixedPcdGet32 (PcdHypFvBaseAddress) & EFI_PAGE_MASK) == 0)) { + // The memory needs to be declared because the DXE core marked it as reserved and removed it from the memory space + // as it contains the Firmware. + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeSystemMemory, + FixedPcdGet32 (PcdHypFvBaseAddress), FixedPcdGet32 (PcdHypFvSize), + EFI_MEMORY_WB | EFI_MEMORY_RUNTIME + ); + if (!EFI_ERROR (Status)) { + // We allocate the memory to ensure it is marked as runtime memory + HypBase = FixedPcdGet32 (PcdHypFvBaseAddress); + Status = gBS->AllocatePages (AllocateAddress, EfiRuntimeServicesCode, + EFI_SIZE_TO_PAGES (FixedPcdGet32 (PcdHypFvSize)), &HypBase); + } + } else { + // The hypervisor must be contained into a EFI_PAGE_SIZE-aligned region and its size must also be aligned + // on a EFI_PAGE_SIZE boundary (ie: 4KB). + Status = EFI_UNSUPPORTED; + ASSERT_EFI_ERROR (Status); + } + + if (EFI_ERROR (Status)) { + return Status; + } + } + + // Install dynamic Shell command to run baremetal binaries. + Status = ShellDynCmdRunAxfInstall (ImageHandle); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "AshbrookDxe: Failed to install ShellDynCmdRunAxf\n")); + } + + // Try to install the ACPI Tables + Status = LocateAndInstallAcpiFromFv (&mAshbrookAcpiTableFile); + if (EFI_ERROR (Status)) { + return Status; + } + + // Try to install the Flat Device Tree (FDT). This function actually installs the + // UEFI Driver Binding Protocol. + /*Status = AshbrookFdtInstall (ImageHandle); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "AshbrookDxe: Failed to install Fdt\n")); + }*/ + + return Status; +} diff --git a/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.inf b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.inf new file mode 100644 index 0000000..acf4d71 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxe.inf @@ -0,0 +1,69 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AshbrookDxe + FILE_GUID = 1484ebe8-2681-45f1-a2e5-12ecad893b62 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AshbrookEntryPoint + +[Sources.common] + AshbrookDxe.c + DramBlockIo.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + OpenPlatformPkg/Platforms/ARM/Ashbrook/Ashbrook.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + AcpiLib + ArmShellCmdRunAxfLib + BaseMemoryLib + BdsLib + DebugLib + DmaLib + DxeServicesTableLib + FdtLib + IoLib + PcdLib + PrintLib + SerialPortLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiLib + UefiDriverEntryPoint + +[Guids] + #gArmGlobalVariableGuid + gEfiEndOfDxeEventGroupGuid + gEfiFileInfoGuid + gFdtTableGuid + +[Protocols] + gEfiBlockIoProtocolGuid + gEfiDevicePathFromTextProtocolGuid + gEfiSimpleFileSystemProtocolGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmTokenSpaceGuid.PcdHypFvBaseAddress + gArmTokenSpaceGuid.PcdHypFvSize + +[Depex] + TRUE diff --git a/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxeInternal.h b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxeInternal.h new file mode 100644 index 0000000..696d01d --- /dev/null +++ b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/AshbrookDxeInternal.h @@ -0,0 +1,37 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ASHBROOK_DXE_INTERNAL_H__ +#define __ASHBROOK_DXE_INTERNAL_H__ + +#include <Uefi.h> + +#include <Library/AcpiLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <IndustryStandard/Acpi.h> + +EFI_STATUS +InitDramBlockIo ( + VOID + ); + +EFI_STATUS +AshbrookFdtInstall ( + IN EFI_HANDLE ImageHandle + ); + +#endif // __ASHBROOK_DXE_INTERNAL_H__ diff --git a/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/DramBlockIo.c b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/DramBlockIo.c new file mode 100644 index 0000000..d125e4b --- /dev/null +++ b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/DramBlockIo.c @@ -0,0 +1,185 @@ +/** @file +* +* Copyright (c) 2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "AshbrookDxeInternal.h" + +#include <Protocol/BlockIo.h> + +#include <Library/BaseMemoryLib.h> + +#define DRAM_SIGNATURE SIGNATURE_32('d', 'r', 'a', 'm') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + + EFI_BLOCK_IO_PROTOCOL BlockIoProtocol; + EFI_BLOCK_IO_MEDIA Media; + + struct { + VENDOR_DEVICE_PATH Vendor; + EFI_DEVICE_PATH_PROTOCOL End; + } DevicePath; +} DRAM_INSTANCE; + +#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, DRAM_INSTANCE, BlockIoProtocol, DRAM_SIGNATURE) + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset +// +EFI_STATUS +EFIAPI +DramBlockIoReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + ASSERT (0); + return EFI_UNSUPPORTED; +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks +// +EFI_STATUS +EFIAPI +DramBlockIoReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ) +{ + DRAM_INSTANCE *Instance; + + // The instance and buffer pointers must be valid + if ((This == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // We must have some bytes to read + if (BufferSizeInBytes == 0) { + return EFI_BAD_BUFFER_SIZE; + } + + // Check the instance is ours + Instance = INSTANCE_FROM_BLKIO_THIS (This); + if (Instance->Signature != DRAM_SIGNATURE) { + return EFI_INVALID_PARAMETER; + } + + // The size of the buffer must be a multiple of the block size + if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) { + return EFI_BAD_BUFFER_SIZE; + } + + CopyMem (Buffer, (VOID*)((UINTN)FixedPcdGet64 (PcdSystemMemoryBase) + (UINTN)Lba), BufferSizeInBytes); + return EFI_SUCCESS; +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks +// +EFI_STATUS +EFIAPI +DramBlockIoWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer + ) +{ + ASSERT (0); + return EFI_UNSUPPORTED; +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks +// +EFI_STATUS +EFIAPI +DramBlockIoFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ) +{ + ASSERT (0); + return EFI_UNSUPPORTED; +} + +STATIC DRAM_INSTANCE mDramInstance = { + DRAM_SIGNATURE, // Signature + NULL, // Handle + + { + EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision + NULL, // Media ... NEED TO BE FILLED + DramBlockIoReset, // Reset; + DramBlockIoReadBlocks, // ReadBlocks + DramBlockIoWriteBlocks, // WriteBlocks + DramBlockIoFlushBlocks // FlushBlocks + }, // BlockIoProtocol + + { + 0, // MediaId + FALSE, // RemovableMedia + TRUE, // MediaPresent + FALSE, // LogicalPartition + TRUE, // ReadOnly + FALSE, // WriteCaching; + 0x1, // BlockSize + 4, // IoAlign + FixedPcdGet64 (PcdSystemMemorySize), // LastBlock + 0, // LowestAlignedLba + 1, // LogicalBlocksPerPhysicalBlock + }, //Media; + + { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { (UINT8)(sizeof (VENDOR_DEVICE_PATH)), (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) }, + }, + // 30f57e4a-69ce-4fb7-b7a1-4c7ce49d57a6 + { 0x30f57e4a, 0x69ce, 0x4fb7, { 0xb7, 0xa1, 0x4c, 0x7c, 0xe4, 0x9d, 0x57, 0xa6 } }, + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } + } + } // DevicePath +}; + +EFI_STATUS +InitDramBlockIo ( + VOID + ) +{ + EFI_STATUS Status; + + // Initialize instance + mDramInstance.BlockIoProtocol.Media = &mDramInstance.Media; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &mDramInstance.Handle, + &gEfiDevicePathProtocolGuid, &mDramInstance.DevicePath, + &gEfiBlockIoProtocolGuid, &mDramInstance.BlockIoProtocol, + NULL + ); + + return Status; +} diff --git a/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/InstallFdt.c b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/InstallFdt.c new file mode 100644 index 0000000..f00c4f4 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Drivers/AshbrookDxe/InstallFdt.c @@ -0,0 +1,345 @@ +/** @file +* +* Copyright (c) 2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "AshbrookDxeInternal.h" + +#include <Protocol/BlockIo.h> +#include <Protocol/DevicePathFromText.h> +#include <Protocol/DriverBinding.h> +#include <Protocol/SimpleFileSystem.h> + +#include <Library/BaseMemoryLib.h> +#include <Library/BdsLib.h> +#include <Library/DevicePathLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PrintLib.h> +#include <Library/SerialPortLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> + +#include <Guid/ArmGlobalVariableHob.h> +#include <Guid/EventGroup.h> +#include <Guid/Fdt.h> +#include <Guid/FileInfo.h> + +#include <libfdt.h> + +#define FDT_DEFAULT_FILENAME L"ashbrook" + +#define IS_DEVICE_PATH_NODE(node,type,subtype) (((node)->Type == (type)) && ((node)->SubType == (subtype))) + +// Hardware Vendor Device Path node for the Ashbrook NOR Flash. We use the Ashbrook NOR Flash if the user +// has not specified another filesystem location into the UEFI Variable 'Fdt'. +// The Ashbrook NOR Flash has its own filesystem format (supported by ArmPlatformPkg/FileSystem/BootMonFs). +STATIC CONST struct { + VENDOR_DEVICE_PATH NorGuid; + EFI_DEVICE_PATH End; +} mAshbrookNorFlashDevicePath = { + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } }, + {0xEBF0B9DF, 0x17d0, 0x4812, { 0xA9, 0x59, 0xCF, 0xD7, 0x92, 0xEE, 0x31, 0x13} } + }, + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } } +}; + +STATIC EFI_DEVICE_PATH* mFdtFileSystemDevicePath = NULL; +STATIC CHAR16* mFdtFileName = NULL; + +STATIC BOOLEAN mFdtTableInstalled = FALSE; + +/** + See definition EFI_DRIVER_BINDING_PROTOCOL.Supported() +**/ +EFI_STATUS +EFIAPI +AshbrookFdtSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + // + // Check if the Handle support the Block IO Protocol + // + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiBlockIoProtocolGuid, + NULL, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + // Check if a DevicePath is attached to the handle + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiDevicePathProtocolGuid, + (VOID **)&DevicePath, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Check if the Device Path is the one from the NOR Flash + if (CompareMem (mFdtFileSystemDevicePath, DevicePath, GetDevicePathSize (mFdtFileSystemDevicePath)) != 0) { + return EFI_NOT_FOUND; + } + + gBS->CloseProtocol (ControllerHandle, &gEfiDevicePathProtocolGuid, gImageHandle, ControllerHandle); + return Status; +} + +/** + See definition EFI_DRIVER_BINDING_PROTOCOL.Start () +**/ +EFI_STATUS +EFIAPI +AshbrookFdtStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL + ) +{ + EFI_STATUS Status; + UINTN Size; + EFI_PHYSICAL_ADDRESS FdtBlob[4096]; + + if (mFdtTableInstalled) { + return EFI_ALREADY_STARTED; + } + + Size = 0x1000; + + // The FDT blob is attached to the Configuration Table. It is better to load it as Runtime Service Data + // to prevent the kernel to overwrite its data + //Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES (Size), &FdtBlob); + //if (!EFI_ERROR (Status)) { + CopyMem (&FdtBlob[0], (VOID*)((UINTN)FixedPcdGet64 (PcdSystemMemoryBase) + (UINTN) 0x3000000), (UINTN) Size); + + // Install the FDT into the Configuration Table + Status = gBS->InstallConfigurationTable (&gFdtTableGuid, (VOID*)(UINTN)(&FdtBlob[0])); + if (!EFI_ERROR (Status)) { + mFdtTableInstalled = TRUE; + } + //} + + return Status; +} + +/** + See definition EFI_DRIVER_BINDING_PROTOCOL.Stop() +**/ +EFI_STATUS +EFIAPI +AshbrookFdtStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ) +{ + UINTN Index; + VOID* FdtBlob; + UINTN FdtSize; + + // Look for FDT Table + for (Index = 0; Index < gST->NumberOfTableEntries; Index++) { + // Check for correct GUID type + if (CompareGuid (&gFdtTableGuid, &(gST->ConfigurationTable[Index].VendorGuid))) { + FdtBlob = gST->ConfigurationTable[Index].VendorTable; + FdtSize = (UINTN)fdt_totalsize (FdtBlob); + + // Uninstall the FDT Configuration Table + gBS->InstallConfigurationTable (&gFdtTableGuid, NULL); + + // Free the memory + gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)FdtBlob, EFI_SIZE_TO_PAGES (FdtSize)); + + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +// +// Driver Binding Protocol for Ashbrook FDT support +// +EFI_DRIVER_BINDING_PROTOCOL mAshbrookFdtBinding = { + AshbrookFdtSupported, + AshbrookFdtStart, + AshbrookFdtStop, + 0xa, + NULL, + NULL +}; + +/** + Notification function of EFI_END_OF_DXE_EVENT_GROUP_GUID event group. + + This is a notification function registered on EFI_END_OF_DXE_EVENT_GROUP_GUID event group. + + @param Event Event whose notification function is being invoked. + @param Context Pointer to the notification function's context. + +**/ +STATIC +VOID +EFIAPI +OnEndOfDxe ( + EFI_EVENT Event, + VOID *Context + ) +{ + EFI_DEVICE_PATH *DevicePathNode; + EFI_HANDLE Handle; + EFI_STATUS Status; + UINTN VariableSize; + CHAR16* FdtDevicePathStr; + EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol; + + + // + // Read the 'FDT' UEFI Variable to know where we should we read the blob from. + // The 'Fdt' variable contains either the full device path or only the filename of the FDT. + // If 'Fdt' only contains the filename then we assume its location is on the NOR Flash. + // + VariableSize = 0; + Status = gRT->GetVariable (L"Fdt", &gArmGlobalVariableGuid, NULL, &VariableSize, mFdtFileSystemDevicePath); + if (Status == EFI_BUFFER_TOO_SMALL) { + // Get the environment variable value + mFdtFileSystemDevicePath = AllocatePool (VariableSize); + if (mFdtFileSystemDevicePath != NULL) { + Status = gRT->GetVariable (L"Fdt", &gArmGlobalVariableGuid, NULL, &VariableSize, mFdtFileSystemDevicePath); + if (EFI_ERROR (Status)) { + FreePool (mFdtFileSystemDevicePath); + ASSERT_EFI_ERROR (Status); + return; + } + } else { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return; + } + } else if (Status == EFI_NOT_FOUND) { + // If the 'Fdt' variable does not exist then we get the FDT location from the PCD + //FdtDevicePathStr = (CHAR16*)PcdGetPtr (PcdFdtDevicePath); + FdtDevicePathStr = (CHAR16*) ("VenHw(30F57E4A-69CE-4FB7-B7A1-4C7CE49D57A6)/MemoryMapped(0x0,0x83000000,0x83200000)"); + + Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + // Conversion of the Device Path string into EFI Device Path + mFdtFileSystemDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath(FdtDevicePathStr); + } + + if (mFdtFileSystemDevicePath != NULL) { + // Look for the FDT filename that should be contained into the FilePath device path node + DevicePathNode = mFdtFileSystemDevicePath; + while (!IsDevicePathEnd (DevicePathNode)) { + if (IS_DEVICE_PATH_NODE (DevicePathNode, MEDIA_DEVICE_PATH, MEDIA_FILEPATH_DP)) { + // Extract the name from the File Path Node. The name of the Filename is the size of the + // device path node minus the size of the device path node header. + mFdtFileName = AllocateCopyPool ( + DevicePathNodeLength (DevicePathNode) - sizeof(EFI_DEVICE_PATH_PROTOCOL), + ((FILEPATH_DEVICE_PATH*)DevicePathNode)->PathName); + if (mFdtFileName == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return; + } + + // We remove the FilePath device path node from the FileSystem Device Path + // because it will never match a device path installed by the FileSystem driver + SetDevicePathEndNode (DevicePathNode); + break; + } + DevicePathNode = NextDevicePathNode (DevicePathNode); + } + + // The UEFI Variable might just contain the FDT filename. In this case we assume the FileSystem is + // the NOR Flash based one (ie: BootMonFs). + // If it was only containing the FilePath device node then the previous condition should have + // replaced it by the End Device Path Node. + //if (IsDevicePathEndType (mFdtFileSystemDevicePath)) { + //mFdtFileSystemDevicePath = (EFI_DEVICE_PATH*)&mAshbrookNorFlashDevicePath; + //} + } else { + // Fallback on the NOR Flash filesystem + mFdtFileSystemDevicePath = (EFI_DEVICE_PATH*)&mAshbrookNorFlashDevicePath; + } + + // If the FDT FileName has been provided during the FileSystem identification + if (mFdtFileName == NULL) { + mFdtFileName = AllocateCopyPool (StrSize (FDT_DEFAULT_FILENAME), FDT_DEFAULT_FILENAME); + if (mFdtFileName == NULL) { + ASSERT_EFI_ERROR (Status); + return; + } + } + + // Install the Binding protocol to verify when the FileSystem that contains the FDT has been installed + Status = gBS->InstallMultipleProtocolInterfaces ( + &gImageHandle, + &gEfiDriverBindingProtocolGuid, &mAshbrookFdtBinding, + NULL + ); + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + //AshbrookFdtStart(&mAshbrookFdtBinding, gImageHandle, mFdtFileSystemDevicePath); + + // + // Force to connect the FileSystem that contains the FDT + // + BdsConnectDevicePath (mFdtFileSystemDevicePath, &Handle, NULL); +} + +EFI_STATUS +AshbrookFdtInstall ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + // Register the event handling function to set the End Of DXE flag. + // We wait until the end of the DXE phase to load the FDT to make sure + // all the required drivers (NOR Flash, UEFI Variable, BootMonFs) are dispatched + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OnEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platforms/ARM/Ashbrook/Include/ArmPlatform.h b/Platforms/ARM/Ashbrook/Include/ArmPlatform.h new file mode 100644 index 0000000..682fb4f --- /dev/null +++ b/Platforms/ARM/Ashbrook/Include/ArmPlatform.h @@ -0,0 +1,99 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_ASHBROOK_H__ +#define __ARM_ASHBROOK_H__ + +#include <VExpressMotherBoard.h> + +/*********************************************************************************** +// Platform Memory Map +************************************************************************************/ + +// NOR Flash 0 +#define ARM_VE_SMB_NOR0_BASE 0x08000000 +#define ARM_VE_SMB_NOR0_SZ SIZE_128MB + +// Motherboard Peripheral and On-chip peripheral +#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000 +#define ARM_VE_BOARD_PERIPH_BASE_SZ SIZE_2MB + +// SP810 Controller +#undef SP810_CTRL_BASE +#define SP810_CTRL_BASE 0x1C020000 + +// Off-Chip peripherals (Ethernet, VRAM) +#define ARM_VE_SMB_PERIPH_BASE 0x18000000 +#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB + +// On-Chip non-secure ROM +#define ASHBROOK_NON_SECURE_ROM_BASE 0x1F000000 +#define ASHBROOK_NON_SECURE_ROM_SZ SIZE_512KB + +// On-Chip Peripherals +#define ASHBROOK_PERIPHERALS_BASE 0x20000000 +#define ASHBROOK_PERIPHERALS_SZ 0x0E000000 + +// On-Chip non-secure SRAM +#define ASHBROOK_NON_SECURE_SRAM_BASE 0x2E000000 +#define ASHBROOK_NON_SECURE_SRAM_SZ SIZE_32KB + +// GIC-500 +#define ASHBROOK_GIC_500_BASE 0x30000000 +#define ASHBROOK_GIC_500_BASE_SZ SIZE_256KB + +//#define ASHBROOK_GIC_500_RBASE 0x30800000 +#define ASHBROOK_GIC_500_RBASE_SZ SIZE_8MB + +// SOC peripherals (HDLCD, UART, I2C, I2S, SMC-PL354, etc) +#define ASHBROOK_SOC_PERIPHERALS_BASE 0x7FF50000 +#define ASHBROOK_SOC_PERIPHERALS_SZ (SIZE_64KB * 10) + +// 16 MB ARM-TF System Memory +#define ASHBROOK_ARM_TF_SYSTEM_MEMORY_BASE 0xFF000000 +#define ASHBROOK_ARM_TF_SYSTEM_MEMORY_SZ SIZE_16MB + +// Extra DRAM +// FVP supports 1 more bank of DRAM from 0x8 8000 0000. +// Emulator/TB have not implemented this bank +// Hence use 1 GB (approx) from 0xC000 0000 +#define ASHBROOK_EXTRA_SYSTEM_MEMORY_BASE 0xC0000000 +#define ASHBROOK_EXTRA_SYSTEM_MEMORY_SZ (SIZE_1GB - SIZE_16MB) + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','S','H','B','R','O','O','K') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x20140727 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099 + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define ASHBROOK_WATCHDOG_COUNT 2 + +#endif diff --git a/Platforms/ARM/Ashbrook/Library/AshbrookLib/AArch64/AshbrookHelper.S b/Platforms/ARM/Ashbrook/Library/AshbrookLib/AArch64/AshbrookHelper.S new file mode 100644 index 0000000..a8ad887 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Library/AshbrookLib/AArch64/AshbrookHelper.S @@ -0,0 +1,74 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask) + + +PrimaryCoreMpid: .word 0x0 + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + ldr x0, =PrimaryCoreMpid + ldrh w0, [x0] + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1) + ldrh w1, [x1] + and x0, x0, x1 + + ldr x1, =PrimaryCoreMpid + ldrh w1, [x1] + + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret + +ASM_PFX(ArmPlatformPeiBootAction): + // The trusted firmware passes the primary CPU MPID through x0 register. + // Save it in a variable. + ldr x1, =PrimaryCoreMpid + str w0, [x1] + ret diff --git a/Platforms/ARM/Ashbrook/Library/AshbrookLib/Arm/AshbrookHelper.S b/Platforms/ARM/Ashbrook/Library/AshbrookLib/Arm/AshbrookHelper.S new file mode 100644 index 0000000..184c1a8 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Library/AshbrookLib/Arm/AshbrookHelper.S @@ -0,0 +1,105 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask) + + +PrimaryCoreMpid: .word 0x0 + +// +// Return the core position from the value of its MpId register +// +// This function returns the core position from the position 0 in the processor. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + ldr r0, =PrimaryCoreMpid + ldr r0, [r0] + bx lr + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary core. +// The primary core is the core responsible to initialize the hardware and run UEFI. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1) + ldr r1, [r1] + and r0, r0, r1 + + ldr r1, =PrimaryCoreMpid + ldr r1, [r1] + + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + // The trusted firmware passes the primary CPU MPID through r0 register. + // Save it in a variable. + ldr r1, =PrimaryCoreMpid + str r0, [r1] + bx lr diff --git a/Platforms/ARM/Ashbrook/Library/AshbrookLib/Ashbrook.c b/Platforms/ARM/Ashbrook/Library/AshbrookLib/Ashbrook.c new file mode 100644 index 0000000..c9fbc18 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Library/AshbrookLib/Ashbrook.c @@ -0,0 +1,167 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmGicLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> + +#include <Ppi/ArmMpCoreInfo.h> +#include <Drivers/SP804Timer.h> +#include <ArmPlatform.h> + +ARM_CORE_INFO mAshbrookInfoTable[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 0 + 0x1, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 1 + 0x1, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 2 + 0x1, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 3 + 0x1, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + } +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + // REF CLK Init + //MmioOr32(0x2A430000, 0x01); + //MmioOr32(0x2A830000, 0x01); + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + // Only support one cluster + *CoreCount = sizeof(mAshbrookInfoTable) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mAshbrookInfoTable; + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Platforms/ARM/Ashbrook/Library/AshbrookLib/AshbrookLib.inf b/Platforms/ARM/Ashbrook/Library/AshbrookLib/AshbrookLib.inf new file mode 100644 index 0000000..a27dc87 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Library/AshbrookLib/AshbrookLib.inf @@ -0,0 +1,55 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AshbrookLib + FILE_GUID = 87c525cd-e1a2-469e-994c-c28cd0c7bd0d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + OpenPlatformPkg/Platforms/ARM/Ashbrook/Ashbrook.dec + +[LibraryClasses] + IoLib + ArmLib + HobLib + MemoryAllocationLib + SerialPortLib + +[Sources.common] + Ashbrook.c + AshbrookMem.c + +[Sources.AARCH64] + AArch64/AshbrookHelper.S | GCC + +[Sources.ARM] + Arm/AshbrookHelper.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask diff --git a/Platforms/ARM/Ashbrook/Library/AshbrookLib/AshbrookMem.c b/Platforms/ARM/Ashbrook/Library/AshbrookLib/AshbrookMem.c new file mode 100644 index 0000000..9e9473f --- /dev/null +++ b/Platforms/ARM/Ashbrook/Library/AshbrookLib/AshbrookMem.c @@ -0,0 +1,167 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> + +#include <ArmPlatform.h> + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + + ASSERT (VirtualMemoryMap != NULL); + + // + // Declared the additional 6GB of memory + // + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + ASHBROOK_EXTRA_SYSTEM_MEMORY_BASE, + ASHBROOK_EXTRA_SYSTEM_MEMORY_SZ); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // SMB CS0 - NOR0 Flash + VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].Length = SIZE_256KB * 255; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // Environment Variables region + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255); + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255); + VirtualMemoryTable[Index].Length = SIZE_64KB * 4; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SMB CS2 & CS3 - Off-chip (motherboard) peripherals + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Off-chip (motherboard) System Registers + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_BOARD_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_BOARD_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_BOARD_PERIPH_BASE_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Ashbrook OnChip non-secure ROM + VirtualMemoryTable[++Index].PhysicalBase = ASHBROOK_NON_SECURE_ROM_BASE; + VirtualMemoryTable[Index].VirtualBase = ASHBROOK_NON_SECURE_ROM_BASE; + VirtualMemoryTable[Index].Length = ASHBROOK_NON_SECURE_ROM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // Ashbrook OnChip peripherals + VirtualMemoryTable[++Index].PhysicalBase = ASHBROOK_PERIPHERALS_BASE; + VirtualMemoryTable[Index].VirtualBase = ASHBROOK_PERIPHERALS_BASE; + VirtualMemoryTable[Index].Length = ASHBROOK_PERIPHERALS_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Ashbrook OnChip non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase = ASHBROOK_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ASHBROOK_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].Length = ASHBROOK_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // Ashbrook GIC-500 + VirtualMemoryTable[++Index].PhysicalBase = ASHBROOK_GIC_500_BASE; + VirtualMemoryTable[Index].VirtualBase = ASHBROOK_GIC_500_BASE; + VirtualMemoryTable[Index].Length = ASHBROOK_GIC_500_BASE_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdGicRedistributorsBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdGicRedistributorsBase); + VirtualMemoryTable[Index].Length = ASHBROOK_GIC_500_RBASE_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // Ashbrook SOC peripherals + VirtualMemoryTable[++Index].PhysicalBase = ASHBROOK_SOC_PERIPHERALS_BASE; + VirtualMemoryTable[Index].VirtualBase = ASHBROOK_SOC_PERIPHERALS_BASE; + VirtualMemoryTable[Index].Length = ASHBROOK_SOC_PERIPHERALS_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // DDR - 1 GB + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // Extra DDR - (1GB - 16MB) + VirtualMemoryTable[++Index].PhysicalBase = ASHBROOK_EXTRA_SYSTEM_MEMORY_BASE; + VirtualMemoryTable[Index].VirtualBase = ASHBROOK_EXTRA_SYSTEM_MEMORY_BASE; + VirtualMemoryTable[Index].Length = ASHBROOK_EXTRA_SYSTEM_MEMORY_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // ARM-TF - 16 MB + VirtualMemoryTable[++Index].PhysicalBase = ASHBROOK_ARM_TF_SYSTEM_MEMORY_BASE; + VirtualMemoryTable[Index].VirtualBase = ASHBROOK_ARM_TF_SYSTEM_MEMORY_BASE; + VirtualMemoryTable[Index].Length = ASHBROOK_ARM_TF_SYSTEM_MEMORY_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Platforms/ARM/Ashbrook/Library/NorFlashAshbrookLib/NorFlashAshbrook.c b/Platforms/ARM/Ashbrook/Library/NorFlashAshbrookLib/NorFlashAshbrook.c new file mode 100644 index 0000000..e3586ea --- /dev/null +++ b/Platforms/ARM/Ashbrook/Library/NorFlashAshbrookLib/NorFlashAshbrook.c @@ -0,0 +1,68 @@ +/** @file + + Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#include <PiDxe.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/NorFlashPlatformLib.h> +#include <ArmPlatform.h> + +NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { + { + ARM_VE_SMB_NOR0_BASE, + ARM_VE_SMB_NOR0_BASE, + SIZE_256KB * 255, + SIZE_256KB, + {0xEBF0B9DF, 0x17d0, 0x4812, { 0xA9, 0x59, 0xCF, 0xD7, 0x92, 0xEE, 0x31, 0x13} } + }, + { + ARM_VE_SMB_NOR0_BASE, + ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255, + SIZE_64KB * 4, + SIZE_64KB, + {0x98C111C6, 0xB322, 0x4C33, { 0x95, 0xD5, 0xAF, 0x56, 0xAF, 0x90, 0x18, 0x6A } } + }, +}; + +EFI_STATUS +NorFlashPlatformInitialization ( + VOID + ) +{ + // Everything seems ok so far, so now we need to disable the platform-specific + // flash write protection for Versatile Express + if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) { + // Writing to NOR FLASH is disabled, so enable it + MmioWrite32 (ARM_VE_SYS_FLASH, 1); + DEBUG((DEBUG_BLKIO, "NorFlashPlatformInitialization: informational - Had to enable HSYS_FLASH flag.\n" )); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DESCRIPTION **NorFlashDevices, + OUT UINT32 *Count + ) +{ + if ((NorFlashDevices == NULL) || (Count == NULL)) { + return EFI_INVALID_PARAMETER; + } + + *NorFlashDevices = mNorFlashDevices; + *Count = sizeof (mNorFlashDevices) / sizeof (NOR_FLASH_DESCRIPTION); + + return EFI_SUCCESS; +} diff --git a/Platforms/ARM/Ashbrook/Library/NorFlashAshbrookLib/NorFlashAshbrookLib.inf b/Platforms/ARM/Ashbrook/Library/NorFlashAshbrookLib/NorFlashAshbrookLib.inf new file mode 100644 index 0000000..8578c6e --- /dev/null +++ b/Platforms/ARM/Ashbrook/Library/NorFlashAshbrookLib/NorFlashAshbrookLib.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = NorFlashAshbrookLib + FILE_GUID = e420f33e-fcf1-48af-9c44-89592d26acc2 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = NorFlashPlatformLib + +[Sources.common] + NorFlashAshbrook.c + +[Packages] + MdePkg/MdePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib diff --git a/Platforms/ARM/Ashbrook/Makefile b/Platforms/ARM/Ashbrook/Makefile new file mode 100644 index 0000000..2f68171 --- /dev/null +++ b/Platforms/ARM/Ashbrook/Makefile @@ -0,0 +1,89 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +# Define the following variables to specify an alternative toolchain to the one located in your PATH: +# - RVCT_TOOLS_PATH: for RVCT and RVCTLINUX toolchains +# - ARMGCC_TOOLS_PATH: for ARMGCC toolchain +# - ARMLINUXGCC_TOOLS_PATH: for ARMLINUXGCC + +EDK2_TOOLCHAIN ?= GCC49 +GCC49_AARCH64_PREFIX ?= aarch64-none-elf- +EDK2_ARCH ?= AARCH64 +EDK2_BUILD ?= DEBUG +EDK2_DSC = OpenPlatformPkg/Platforms/ARM/Ashbrook/Ashbrook.dsc +DEST_BIN_ROOT ?= + +ifeq ($(EDK2_DSC),"") + $(error The Makefile macro 'EDK2_DSC' must be defined with an EDK2 DSC file.) +endif + +ifeq ("$(OS)","Windows_NT") +export WORKSPACE?=$(PWD) +export EDK_TOOLS_PATH ?= $(WORKSPACE)\BaseTools +else +export WORKSPACE?=$(PWD) +endif + +# Define the destination of the Firmware Image Package (FIP) if not defined +ifndef ASHBROOK_FIP + ifdef DEST_BIN_ROOT + ASHBROOK_FIP=$(DEST_BIN_ROOT)/fip.bin + else + ASHBROOK_FIP=fip.bin + endif +endif + +SHELL := /bin/bash +SILENT ?= @ +ECHO ?= echo +MAKE ?= make -i -k +RM ?= rm -f +CP ?= cp + +.PHONY: all clean + +EDK2_CONF = Conf/BuildEnv.sh Conf/build_rule.txt Conf/target.txt Conf/tools_def.txt + +all: $(EDK2_CONF) +ifeq ("$(OS)","Windows_NT") + build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) +else + . ./edksetup.sh; GCC49_AARCH64_PREFIX=$(GCC49_AARCH64_PREFIX) build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) +endif +ifeq ("$(OS)","Windows_NT") + $(SILENT)$(ECHO) "Warning: The UEFI Firmware must be added to the Firmware Image Package (FIP)." +else + $(SILENT)which fip_create ; \ + if [ $$? -ne 0 ]; then \ + $(ECHO) "Warning: 'fip_create' tool is not in the PATH. The UEFI binary will not be added in the Firmware Image Package (FIP)."; \ + else \ + fip_create --bl33 $(WORKSPACE)/Build/Ashbrook_DevPlatform/$(EDK2_BUILD)_$(EDK2_TOOLCHAIN)/FV/BL33_AP_UEFI.fd --dump $(ASHBROOK_FIP); \ + fi +endif + +$(EDK2_CONF): +ifeq ("$(OS)","Windows_NT") + copy $(EDK_TOOLS_PATH)\Conf\build_rule.template Conf\build_rule.txt + copy $(EDK_TOOLS_PATH)\Conf\FrameworkDatabase.template Conf\FrameworkDatabase.txt + copy $(EDK_TOOLS_PATH)\Conf\target.template Conf\target.txt + copy $(EDK_TOOLS_PATH)\Conf\tools_def.template Conf\tools_def.txt +else + . ./edksetup.sh; $(MAKE) -C BaseTools +endif + +clean: +ifeq ("$(OS)","Windows_NT") + build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall +else + . ./edksetup.sh; build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall; \ + rm -Rf $(EDK2_CONF) Conf/.cache +endif |