diff options
| author | Carles Cufi <carles.cufi@nordicsemi.no> | 2017-01-11 17:46:38 +0100 |
|---|---|---|
| committer | Kumar Gala <kumar.gala@linaro.org> | 2017-01-23 15:15:54 -0600 |
| commit | 88bbd6ccb110bc4aacc4fa07bd1b1fbe0c3a842b (patch) | |
| tree | 587d749a4d94fb7d248d55f671d4a2e1e0ab328f /arch | |
| parent | 457a5988c4efed83796334ac7acdd2aa0f643b25 (diff) | |
arm: cmsis: Convert enable_floating_point to use CMSIS
As a first step towards removing the custom ARM Cortex-M Core code
present in Zephyr in benefit of using CMSIS, this change replaces
the use of the custom core code with CMSIS macros in
enable_floating_point().
Jira: ZEP-1568
Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/core/cortex_m/prep_c.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index a8c918ba5..d4ed18670 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -21,6 +21,7 @@ #include <toolchain.h> #include <linker-defs.h> #include <nano_internal.h> +#include <arch/arm/cortex_m/cmsis.h> #ifdef CONFIG_ARMV6_M static inline void relocate_vector_table(void) { /* do nothing */ } @@ -50,17 +51,14 @@ static inline void enable_floating_point(void) * Upon reset, the Co-Processor Access Control Register is 0x00000000. * Enable CP10 and CP11 coprocessors to enable floating point. */ - __scs.cpacr.val = (_SCS_CPACR_CP10_FULL_ACCESS | - _SCS_CPACR_CP11_FULL_ACCESS); - + SCB->CPACR |= CPACR_CP10_FULL_ACCESS | CPACR_CP11_FULL_ACCESS; /* * Upon reset, the FPU Context Control Register is 0xC0000000 * (both Automatic and Lazy state preservation is enabled). * Disable lazy state preservation so the volatile FP registers are * always saved on exception. */ - __scs.fpu.ccr.val = (_SCS_FPU_CCR_ASPEN_ENABLE | - _SCS_FPU_CCR_LSPEN_DISABLE); + FPU->FPCCR = FPU_FPCCR_ASPEN_Msk; /* FPU_FPCCR_LSPEN = 0 */ /* * Although automatic state preservation is enabled, the processor |