boards: arm: Add board for MPS2 with AN383

ARM's Cortex-M Prototyping System (MPS2) is a board with an FPGA that
can be programmed with different 'SoCs'. To use these in Zephyr we need
a set of board files for each variant.

This adds a board for a variant which implements a Cortex-M3 CPU; the
naming of this matches that used for the Zephyr SoC (which is itself
based on ARM's documentation nomenclature).

Change-Id: Ie02a67a03016b8aeee31e3694f0edbcc37f9ee64
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>

7 files changed, 276 insertions, 0 deletions

diff --git a/boards/arm/mps2_an385/Kconfig.board b/boards/arm/mps2_an385/Kconfig.board
new file mode 100644
index 000000000..5800b37a5
--- /dev/null
+++ b/boards/arm/mps2_an385/Kconfig.board
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2017 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_MPS2_AN385
+	bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)"
+	depends on SOC_MPS2_AN385
diff --git a/boards/arm/mps2_an385/Kconfig.defconfig b/boards/arm/mps2_an385/Kconfig.defconfig
new file mode 100644
index 000000000..8040fcd57
--- /dev/null
+++ b/boards/arm/mps2_an385/Kconfig.defconfig
@@ -0,0 +1,39 @@
+#
+# Copyright (c) 2017 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_MPS2_AN385
+
+config BOARD
+	default mps2_an385
+
+if SERIAL
+
+config UART_CMSDK_APB
+	def_bool y
+
+config UART_INTERRUPT_DRIVEN
+	def_bool y
+
+config UART_CMSDK_APB_PORT0
+	def_bool y
+
+config UART_CMSDK_APB_PORT1
+	def_bool y
+
+config UART_CMSDK_APB_PORT2
+	def_bool y
+
+config UART_CMSDK_APB_PORT3
+	def_bool y
+
+config UART_CMSDK_APB_PORT4
+	def_bool y
+
+endif # SERIAL
+
+
+
+endif
diff --git a/boards/arm/mps2_an385/Makefile b/boards/arm/mps2_an385/Makefile
new file mode 100644
index 000000000..87680c01d
--- /dev/null
+++ b/boards/arm/mps2_an385/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2016 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# Force build system to create built-in.o even though we do not (yet)
+# have any C files to compile
+obj- += dummy.o
diff --git a/boards/arm/mps2_an385/board.h b/boards/arm/mps2_an385/board.h
new file mode 100644
index 000000000..56de65d89
--- /dev/null
+++ b/boards/arm/mps2_an385/board.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+#endif /* __INC_BOARD_H */
diff --git a/boards/arm/mps2_an385/doc/img/mps2.png b/boards/arm/mps2_an385/doc/img/mps2.png
new file mode 100644
index 000000000..bf5dfbb7e
--- /dev/null
+++ b/boards/arm/mps2_an385/doc/img/mps2.png
diff --git a/boards/arm/mps2_an385/doc/mps2_an385.rst b/boards/arm/mps2_an385/doc/mps2_an385.rst
new file mode 100644
index 000000000..fc47f7601
--- /dev/null
+++ b/boards/arm/mps2_an385/doc/mps2_an385.rst
@@ -0,0 +1,188 @@
+.. _mps2_an385_board:
+
+ARM V2M MPS2
+############
+
+Overview
+********
+
+The mps2_an385 board configuration is used by Zephyr applications that run on
+the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and
+the following devices:
+
+- Nested Vectored Interrupt Controller (NVIC)
+- System Tick System Clock (SYSTICK)
+- Cortex-M System Design Kit UART
+
+.. image:: img/mps2.png
+     :width: 442px
+     :align: center
+     :height: 335px
+     :alt: ARM V2M MPS2
+
+More information about the board can be found at the `V2M MPS2 Website`_.
+
+The Application Note AN385 can be found at `Application Note AN385`_.
+
+Hardware
+********
+
+ARM V2M MPS2 provides the following hardware components:
+
+- ARM Cortex-M3 (AN385)
+- ARM IoT Subsystem for Cortex-M
+- Form factor: 140x120cm
+- SRAM: 8MB single cycle SRAM, 16MB PSRAM
+- Video: QSVGA touch screen panel, 4bit RGB VGA connector
+- Audio: Audio Codec
+- Debug:
+
+  - ARM JTAG20 connector
+  - ARM parallel trace connector (MICTOR38)
+  - 20 pin Cortex debug connector
+  - 10 pin Cortex debug connector
+  - ILA connector for FPGA debug
+
+- Expansion
+
+  - GPIO
+  - SPI
+
+
+Supported Features
+==================
+
+The mps2_an385 board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not currently supported by the port.
+See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
+features.
+
+The default configuration can be found in the defconfig file:
+
+.. code-block:: console
+
+   boards/arm/mps2_an385/mps2_an385_defconfig
+
+Interrupt Controller
+====================
+
+MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs.
+
+A Cortex-M3/4-based board uses vectored exceptions. This means each exception
+calls a handler directly from the vector table.
+
+Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here
+identifies the handlers used for each exception.
+
++------+------------+----------------+--------------------------+
+| Exc# | Name       | Remarks        | Used by Zephyr Kernel    |
++======+============+================+==========================+
+| 1    | Reset      |                | system initialization    |
++------+------------+----------------+--------------------------+
+| 2    | NMI        |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 3    | Hard fault |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 4    | MemManage  | MPU fault      | system fatal error       |
++------+------------+----------------+--------------------------+
+| 5    | Bus        |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 6    | Usage      | undefined      | system fatal error       |
+|      | fault      | instruction,   |                          |
+|      |            | or switch      |                          |
+|      |            | attempt to ARM |                          |
+|      |            | mode           |                          |
++------+------------+----------------+--------------------------+
+| 11   | SVC        |                | context switch and       |
+|      |            |                | software interrupts      |
++------+------------+----------------+--------------------------+
+| 12   | Debug      |                | system fatal error       |
+|      | monitor    |                |                          |
++------+------------+----------------+--------------------------+
+| 14   | PendSV     |                | context switch           |
++------+------------+----------------+--------------------------+
+| 15   | SYSTICK    |                | system clock             |
++------+------------+----------------+--------------------------+
+
+Pin Mapping
+===========
+
+The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible
+for pin muxing, input/output, pull-up, etc.
+
+For mode details please refer to `MPS2 Technical Reference Manual (TRM)`_.
+
+System Clock
+============
+
+The V2M MPS2 main clock is 24 MHz.
+
+Serial Port
+===========
+
+The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for
+RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by
+default, is utilizing UART0.
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+V2M MPS2 provides:
+
+- A USB connection to the host computer, which exposes a Mass Storage and an
+  USB Serial Port.
+- A Serial Flash device, which implements the USB flash disk file storage.
+- A physical UART connection which is relayed over interface USB Serial port.
+
+Flashing an application to V2M MPS2
+-----------------------------------
+
+The sample application hello_world is being used in this tutorial:
+
+.. code-block:: console
+
+   $ZEPHYR_BASE/samples/hello_world
+
+To build the Zephyr kernel and application, enter:
+
+.. code-block:: console
+
+   $ cd $ZEPHYR_BASE
+   $ . zephyr-env.sh
+   $ cd $ZEPHYR_BASE/samples/hello_world/
+   $ make BOARD=mps2_an385
+
+Connect the V2M MPS2 to your host computer using the USB port and you should
+see a USB connection which exposes a Mass Storage and a USB Serial Port.
+Copy the generated zephyr.bin in the exposed drive.
+Reset the board and you should be able to see on the corresponding Serial Port
+the following message:
+
+.. code-block:: console
+
+   Hello World! arm
+
+
+.. _V2M MPS2 Website:
+   https://developer.mbed.org/platforms/ARM-MPS2/
+
+.. _MPS2 Technical Reference Manual (TRM):
+   http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf
+
+.. _Application Note AN385:
+   http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf
diff --git a/boards/arm/mps2_an385/mps2_an385_defconfig b/boards/arm/mps2_an385/mps2_an385_defconfig
new file mode 100644
index 000000000..c2ea006ff
--- /dev/null
+++ b/boards/arm/mps2_an385/mps2_an385_defconfig
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2017 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_ARM=y
+CONFIG_SOC_FAMILY_ARM=y
+CONFIG_SOC_SERIES_MPS2=y
+CONFIG_SOC_MPS2_AN385=y
+CONFIG_BOARD_MPS2_AN385=y
+CONFIG_CORTEX_M_SYSTICK=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CMSDK_APB=y
+CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE=38400