gpio: Support drive strength configuration.

Provide a mechanism to configure different pin drive strengths on
hardware with that capability.

Configuration flags are provided to select each of DFLT, ALT and
DISCONNECT drive strengths independently for low and high outputs.

This provides sufficient flexbility to configure all of the drive
strength capability in at least nRF5 hardware.

The flags are chosen such that in the absence of a drive strength
flag a driver selects DFLT drive strength.  This ensures that an
existing application that omits a flag continues to observe the
preexisting behaviour.

The behaviour of the drive strength flags is documented such that a
driver for hardware that does not support a particular drive strength
will simply defalt to the standard drive strength for that hardware.

Change-Id: I9894cc5e739a1899a4ecf795f2a5980b95b0c7a0
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>

1 files changed, 68 insertions, 0 deletions

diff --git a/include/gpio.h b/include/gpio.h
index e6075dc13..36bf84be7 100644
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -134,6 +134,74 @@ extern "C" {
 #define GPIO_PP_OD_MASK		(1 << GPIO_PP_OD_POS)
 /** @endcond */
 
+/* GPIO_DS_* are for pin drive strength configuration.
+ *
+ * The drive strength of individual pins can be configured
+ * independently for when the pin output is low and high.
+ *
+ * The GPIO_DS_*_LOW enumerations define the drive strength of a pin
+ * when output is low.
+
+ * The GPIO_DS_*_HIGH enumerations define the drive strength of a pin
+ * when output is high.
+ *
+ * The DISCONNECT drive strength indicates that the pin is placed in a
+ * high impediance state and not driven, this option is used to
+ * configure hardware that supports a open collector drive mode.
+ *
+ * The interface supports two different drive strengths:
+ * DFLT - The lowest drive strength supported by the HW
+ * ALT - The highest drive strength supported by the HW
+ *
+ * On hardware that supports only one standard drive strength, both
+ * DFLT and ALT have the same behaviour.
+ *
+ * On hardware that does not support a disconnect mode, DISCONNECT
+ * will behave the same as DFLT.
+ */
+
+/** @cond INTERNAL_HIDDEN */
+#define GPIO_DS_LOW_POS 13
+#define GPIO_DS_LOW_MASK (0x3 << GPIO_DS_LOW_POS)
+/** @endcond */
+
+/** Default drive strength standard when GPIO pin output is low.
+ */
+#define GPIO_DS_DFLT_LOW (0x0 << GPIO_DS_LOW_POS)
+
+/** Alternative drive strength when GPIO pin output is low.
+ * For hardware that does not support configurable drive strength
+ * use the default drive strength.
+ */
+#define GPIO_DS_ALT_LOW (0x1 << GPIO_DS_LOW_POS)
+
+/** Disconnect pin when GPIO pin output is low.
+ * For hardware that does not support disconnect use the default
+ * drive strength.
+ */
+#define GPIO_DS_DISCONNECT_LOW (0x3 << GPIO_DS_LOW_POS)
+
+/** @cond INTERNAL_HIDDEN */
+#define GPIO_DS_HIGH_POS 15
+#define GPIO_DS_HIGH_MASK (0x3 << GPIO_DS_HIGH_POS)
+/** @endcond */
+
+/** Default drive strength when GPIO pin output is high.
+ */
+#define GPIO_DS_DFLT_HIGH (0x0 << GPIO_DS_HIGH_POS)
+
+/** Alternative drive strength when GPIO pin output is high.
+ * For hardware that does not support configurable drive strengths
+ * use the default drive strength.
+ */
+#define GPIO_DS_ALT_HIGH (0x1 << GPIO_DS_HIGH_POS)
+
+/** Disconnect pin when GPIO pin output is high.
+ * For hardware that does not support disconnect use the default
+ * drive strength.
+ */
+#define GPIO_DS_DISCONNECT_HIGH (0x3 << GPIO_DS_HIGH_POS)
+
 struct gpio_callback;
 
 /**