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authorCarles Cufi <carles.cufi@nordicsemi.no>2017-01-11 17:46:38 +0100
committerKumar Gala <kumar.gala@linaro.org>2017-01-23 15:15:54 -0600
commit88bbd6ccb110bc4aacc4fa07bd1b1fbe0c3a842b (patch)
tree587d749a4d94fb7d248d55f671d4a2e1e0ab328f /include
parent457a5988c4efed83796334ac7acdd2aa0f643b25 (diff)
arm: cmsis: Convert enable_floating_point to use CMSIS
As a first step towards removing the custom ARM Cortex-M Core code present in Zephyr in benefit of using CMSIS, this change replaces the use of the custom core code with CMSIS macros in enable_floating_point(). Jira: ZEP-1568 Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/arch/arm/cortex_m/cmsis.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/include/arch/arm/cortex_m/cmsis.h b/include/arch/arm/cortex_m/cmsis.h
index cb778c7fe..097fe011e 100644
--- a/include/arch/arm/cortex_m/cmsis.h
+++ b/include/arch/arm/cortex_m/cmsis.h
@@ -20,6 +20,22 @@ extern "C" {
#include <soc.h>
+/* CP10 Access Bits */
+#define CPACR_CP10_Pos 20U
+#define CPACR_CP10_Msk (3UL << _SCS_CPACR_CP10_Pos)
+#define CPACR_CP10_NO_ACCESS (0UL << _SCS_CPACR_CP10_Pos)
+#define CPACR_CP10_PRIV_ACCESS (1UL << _SCS_CPACR_CP10_Pos)
+#define CPACR_CP10_RESERVED (2UL << _SCS_CPACR_CP10_Pos)
+#define CPACR_CP10_FULL_ACCESS (3UL << _SCS_CPACR_CP10_Pos)
+
+/* CP11 Access Bits */
+#define CPACR_CP11_Pos 22U
+#define CPACR_CP11_Msk (3UL << _SCS_CPACR_CP11_Pos)
+#define CPACR_CP11_NO_ACCESS (0UL << _SCS_CPACR_CP11_Pos)
+#define CPACR_CP11_PRIV_ACCESS (1UL << _SCS_CPACR_CP11_Pos)
+#define CPACR_CP11_RESERVED (2UL << _SCS_CPACR_CP11_Pos)
+#define CPACR_CP11_FULL_ACCESS (3UL << _SCS_CPACR_CP11_Pos)
+
/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
* Use __NVIC_PRIO_BITS as it is required and simple to check, but
* ultimately all SoCs will define their own CMSIS types and constants.